7 nanometer

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In semiconductor manufacturing, the International Technology Roadmap for Semiconductors defines the 7 nanometer (7 nm) node as the technology node following the 10 nm node.

Single transistor 7 nm scale devices were first produced in the early 2000s. However, the node designation of "7nm" has no physical meaning at the time of its production ramp.

As of June 2018, mass production of 7 nm devices has begun, but products have not reached the consumer market.[1] The first 7 nm consumer device will be Apple's A12 ARM SoC (system on a chip),[2][3] the successor to the A11 ARM SoC.

History[edit]

Technology demos[edit]

In July 2015, IBM announced that they had built the first functional transistors with 7 nm technology, using a silicon-germanium process.[4][5]

By early 2017, TSMC had produced 256 Mbit SRAM cells at their 7 nm process with a cell area of 0.027 µm2 (550 F2) with reasonable risk production yields.[6]

Expected commercialization and technologies[edit]

In April 2016, TSMC announced that 7 nm trial production would begin in the first half of 2017.[7] In March 2017, TSMC announced 7 nm risk production starting by June 2018.[8] TSMC's 7 nm production plans, as of early 2017, were to use EUV or immersion lithography initially on this process node, and transition from risk to commercial volume manufacturing from Q2 2017 to Q2 2018. Also, their later generation 7 nm production is planned to use EUV multiple patterning and to have an estimated transition from risk to volume manufacturing between 2018 and 2019.[9]

In September 2016, GlobalFoundries announced trial production in the second half of 2017 and risk production in early 2018, with test chips already running.[10]

In February 2017, Intel announced Fab 42 in Arizona will produce microprocessors using 7 nm manufacturing process.[11]

In April 2018, TSMC announced volume production of 7nm chips. In June 2018, the company announced mass production ramp up.[12]

In June 2018, AMD announced 7nm Radeon Instinct GPUs launching in the second half of 2018.[13]

7nm patterning difficulties[edit]

Pitch splitting issues. Successive litho-etch patterning is subject to overlay errors as well as the CD errors from different exposures.
Spacer patterning issues. Spacer patterning has excellent CD control for features directly patterned by the spacer, but the spaces between spacers may be split into core and gap populations.
Overlay error impact on line cut. An overlay error on a cut hole exposure could distort the line ends (top) or infringe on an adjacent line (bottom).
Two-bar EUV patterning issues. In EUV lithography, a pair of features may not have both features in focus at the same time; one will have different size from the other, and both will shift differently through focus as well.
EUV stochastic failure. A random missing contact hole is a stochastic defect that can occur in EUV lithography.
Difference of best focus among different pitches. Features at different pitches also focus differently due to the EUV mask.

The 7nm foundry node is expected to utilize any of or a combination of the following patterning technologies: pitch splitting, self-aligned patterning, and EUV lithography. Each of these technologies carries significant challenges in critical dimension (CD) control as well as pattern placement, all involving neighboring features.

Pitch splitting[edit]

Pitch splitting involves splitting features which are too close together onto different masks, which are exposed successively, followed by litho-etch processing. Due to the use of different exposures, there is always the risk of overlay error between the two exposures, as well as different CDs resulting from the different exposures.

Spacer patterning[edit]

Spacer patterning involves depositing a layer onto pre-patterned features, then etching back to form spacers on the sidewalls of those features, referred to as core features. After removing the core features, the spacers are used as an etch mask to define trenches in the underlying layer. While the spacer CD control is generally excellent, the trench CD may fall into one of two populations, due to the two possibilities of being located where a core feature was located or in the remaining gap. This is known as 'pitch walking'.[14] Generally pitch = core CD + gap CD + 2 * spacer CD, but this does not guarantee core CD = gap CD. For FEOL features like gate or active area isolation (e.g., fins), the trench CD is not as critical as the spacer-defined CD, in which case, spacer patterning is actually the preferred patterning approach.

When self-aligned quadruple patterning (SAQP) is used, there is a second spacer that is utilized, replacing the first one. In this case, the core CD is replaced by core CD - 2* 2nd spacer CD, and the gap CD is replaced by gap CD - 2 * 2nd spacer CD. Thus, some feature dimensions are strictly defined by the second spacer CD, while the remaining feature dimensions are defined by the core CD, core pitch, and first and second spacer CD's. The core CD and core pitch are defined by conventional lithography, while the spacer CDs are independent of lithography. This is actually expected to have less variation than pitch splitting, where an additional exposure defines its own CD, both directly and through overlay.

Spacer-defined lines also require cutting. The cut spots may shift at exposure, resulting in distorted line ends or intrusions into adjacent lines.

EUV lithography[edit]

EUV lithography is capable of resolving features below 20 nm in conventional lithography style. However, the 3D reflective nature of the EUV mask results in new anomalies in the imaging. One particular nuisance is the two-bar effect, where a pair of identical bar-shaped features do not focus identically. One feature is essentially in the 'shadow' of the other. Consequently, the two features generally have different CDs which change through focus, and these features also shift position through focus.[15][16] This effect may be similar to what may be encountered with pitch splitting. A related issue is the difference of best focus among features of different pitches.[17]

EUV also has issues with reliably printing all features in a large population; some contacts may be completely missing or lines bridged. These are known as stochastic printing failures.[18] The defect level is on the order of 1K/mm2.[19]

The tip-to-tip gap is hard to control for EUV, largely due to the illumination constraint.[20] A separate exposure(s) for cutting lines is preferred.

Comparison with previous nodes[edit]

Due to these challenges, 7nm poses unprecedented patterning difficulty in the BEOL. The previous high-volume, long-lived foundry node (Samsung 10nm, TSMC 16nm) used pitch splitting for the tighter pitch metal layers.[21][22][23]

7 nm process nodes[edit]

The naming of process nodes by different major manufacturers (TSMC, Intel, Samsung, GlobalFoundries) is partially marketing driven and not directly related to any measurable distance on a chip – for example TSMC's 7 nm node is similar in some key dimensions to Intel's 10 nm node. Nevertheless, as of 2017, the technological race to the greatest density was still competitive between the main players, with TSMC, Samsung, and Intel all holding leading positions between the years 2016 and 2017 when measured by the smallest feature size on chip.[24]

ITRS Logic Device

Ground Rules

Samsung

(proposed)

TSMC

(proposed)

GlobalFoundries

(proposed)

Process name 8/7 nm 7 nm 7 nm 7 nm
Transistor Gate Pitch (nm) 42 54 54 56
Interconnect Pitch (nm) 24 36 40 40

Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch).[25][26]

References[edit]

  1. ^ https://www.digitimes.com/news/a20180622PD204.html
  2. ^ Apple's 'A12' chip reportedly in production using 7nm process from TSMC
  3. ^ https://wccftech.com/apple-7nm-a12-2018-iphone-mass-production-tsmc/ Apple’s 7nm A12 Processor For 2018 iPhone Lineup Enters Mass Production As TSMC Ramps Up 7nm Production Suggests Source
  4. ^ IBM Research builds functional 7nm processor
  5. ^ IBM Discloses Working Version of a Much Higher-Capacity Chip - NYTimes.com
  6. ^ Merritt, Rick (8 Feb 2017), "TSMC, Samsung Diverge at 7nm", www.eetimes.com 
  7. ^ Parish, Kevin (20 Apr 2016). "Watch out Intel and Samsung: TSMC is gearing up for 7nm processing with trial production". www.digitaltrends.com. 
  8. ^ "TSMC Tips 7+, 12, 22nm Nodes | EE Times". EETimes. Retrieved 2017-03-17. 
  9. ^ Shilov, Anton (5 May 2017), "Samsung and TSMC Roadmaps: 8 and 6 nm Added, Looking at 22ULP and 12FFC", www.anandtech.com, p. 2 
  10. ^ "GLOBALFOUNDRIES to Deliver Industry's Leading-Performance Offering of 7nm FinFET Technology" (Press release). September 15, 2016. Retrieved April 8, 2017. 
  11. ^ Intel Supports American Innovation with $7 Billion Investment in Next-Generation Semiconductor Factory in Arizona: Intel’s Fab 42 will Target Advanced 7 nm Technology and Create More Than 10,000 Jobs in Arizona
  12. ^ https://www.digitimes.com/news/a20180622PD204.html
  13. ^ "Pushing Boundaries for CPUs and GPUs, AMD Shows Next-Generation of Ryzen, Radeon and EPYC Product Leadership at Computex 2018" (Press release). June 5, 2018. 
  14. ^ M. J. Maslow et al., Proc. SPIE 10587, 1058704 (2018).
  15. ^ Y. Nakajima et al., EUVL Symposium 2007, Sapporo.
  16. ^ L. de Winter et al., Proc. SPIE 9661, 96610A (2015).
  17. ^ M. Burkhardt and A. Raghunathan, Proc. SPIE 9422, 94220X (2015).
  18. ^ P. De Bisschop and E. Hendrickx, Proc. SPIE 10583, 105831K (2018).
  19. ^ S. Larivière et al., Proc. SPIE 10583, 105830U (2018).
  20. ^ E. van Setten et al., Proc. SPIE 9661. 96610G (2015).
  21. ^ Samsung's 2nd generation 10nm by LELELELE
  22. ^ tsmc 10nm starts
  23. ^ 16nm FinFET CMOS
  24. ^ Merrit, Rick (16 Jan 2017), "15 Views from a Silicon Summit", www.eetimes.com 
  25. ^ "International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report" (PDF). 
  26. ^ "7 nm lithography process". 


Preceded by
10 nm
CMOS manufacturing processes Succeeded by
5 nm