This article needs attention from an expert on the subject. The specific problem is: Still an issue regarding 7nm/10nm terminology that isn't addressed in the 10 nanometer and 7 nanometer is a deviation from the International Technology Roadmap for Semiconductors definitions. In short, 7 nm Samsung/TSMC is equivalent to 10 nm Intel. Thus treating 7 nm Samsung/TSMC and 10 nm Intel in different articles due to marketing material and not real measurements seems to be incorrect, specially when the pages refer to ITRS roadmap (duplicate note at other affected article.
In semiconductor manufacturing, the International Technology Roadmap for Semiconductors defines the 7 nanometer (7 nm) node as the technology node following the 10 nm node. Single transistor 7 nm scale devices were first produced in the early 2000s. However, the node designation of "7 nm" had no physical meaning at the time of its production ramp.
As of June 2018, mass production of 7 nm devices has begun. One of the first 7 nm mobile processor, the A12 Bionic, was announced by Apple at their September event. The chip is manufactured by TSMC. AMD is currently working on their "Rome" workstation processors, which are based on the 7 nanometer node and feature up to 64 cores. The Kirim 980 is also based on the 7 nanometer process.
Expected commercialization and technologies
In April 2016, TSMC announced that 7 nm trial production would begin in the first half of 2017. In March 2017, TSMC announced 7 nm risk production starting by June 2018. TSMC's 7 nm production plans, as of early 2017, were to use EUV or immersion lithography initially on this process node, and transition from risk to commercial volume manufacturing from Q2 2017 to Q2 2018. Also, their later generation 7 nm production is planned to use EUV multiple patterning and to have an estimated transition from risk to volume manufacturing between 2018 and 2019.
In February 2017, Intel announced Fab 42 in Arizona will produce microprocessors using 7 nm manufacturing process. The company has not published any expected values for feature lengths at this process node.
In April 2018, TSMC announced volume production of 7 nm chips. In June 2018, the company announced mass production ramp up.
7 nm patterning difficulties
The 7nm foundry node is expected to utilize any of or a combination of the following patterning technologies: pitch splitting, self-aligned patterning, and EUV lithography. Each of these technologies carries significant challenges in critical dimension (CD) control as well as pattern placement, all involving neighboring features.
Pitch splitting involves splitting features which are too close together onto different masks, which are exposed successively, followed by litho-etch processing. Due to the use of different exposures, there is always the risk of overlay error between the two exposures, as well as different CDs resulting from the different exposures.
Spacer patterning involves depositing a layer onto pre-patterned features, then etching back to form spacers on the sidewalls of those features, referred to as core features. After removing the core features, the spacers are used as an etch mask to define trenches in the underlying layer. While the spacer CD control is generally excellent, the trench CD may fall into one of two populations, due to the two possibilities of being located where a core feature was located or in the remaining gap. This is known as 'pitch walking'. Generally pitch = core CD + gap CD + 2 * spacer CD, but this does not guarantee core CD = gap CD. For FEOL features like gate or active area isolation (e.g., fins), the trench CD is not as critical as the spacer-defined CD, in which case, spacer patterning is actually the preferred patterning approach.
When self-aligned quadruple patterning (SAQP) is used, there is a second spacer that is utilized, replacing the first one. In this case, the core CD is replaced by core CD - 2* 2nd spacer CD, and the gap CD is replaced by gap CD - 2 * 2nd spacer CD. Thus, some feature dimensions are strictly defined by the second spacer CD, while the remaining feature dimensions are defined by the core CD, core pitch, and first and second spacer CD's. The core CD and core pitch are defined by conventional lithography, while the spacer CDs are independent of lithography. This is actually expected to have less variation than pitch splitting, where an additional exposure defines its own CD, both directly and through overlay.
Spacer-defined lines also require cutting. The cut spots may shift at exposure, resulting in distorted line ends or intrusions into adjacent lines.
EUV lithography is capable of resolving features below 20 nm in conventional lithography style. However, the 3D reflective nature of the EUV mask results in new anomalies in the imaging. One particular nuisance is the two-bar effect, where a pair of identical bar-shaped features do not focus identically. One feature is essentially in the 'shadow' of the other. Consequently, the two features generally have different CDs which change through focus, and these features also shift position through focus. This effect may be similar to what may be encountered with pitch splitting. A related issue is the difference of best focus among features of different pitches.
EUV also has issues with reliably printing all features in a large population; some contacts may be completely missing or lines bridged. These are known as stochastic printing failures. The defect level is on the order of 1K/mm2.
The tip-to-tip gap is hard to control for EUV, largely due to the illumination constraint. A separate exposure(s) for cutting lines is preferred.
Attenuated phase shift masks have been used in production for 90nm node for adequate focus windows for arbitrarily pitched contacts with the ArF laser wavelength (193 nm), whereas this resolution enhancement is not available for EUV.
Comparison with previous nodes
Due to these challenges, 7nm poses unprecedented patterning difficulty in the BEOL. The previous high-volume, long-lived foundry node (Samsung 10nm, TSMC 16nm) used pitch splitting for the tighter pitch metal layers.
7 nm process nodes
The naming of process nodes by different major manufacturers (TSMC, Intel, Samsung, GlobalFoundries) are partially direct lies (aka “marketing”) and not directly related to any measurable distance on a chip – for example TSMC's 7 nm node is similar in some key dimensions to Intel's 10 nm node. Nevertheless, as of 2017, the technological race to the greatest density was still competitive between the main players, with TSMC, Samsung, and Intel all holding leading positions between the years 2016 and 2017 when measured by the smallest feature size on chip.
|ITRS Logic Device
|Process name||8/7 nm||11/10 nm||7 nm||7 nm|
|Transistor Gate Pitch (nm)||42||48||54||54|
|Interconnect Pitch (nm)||24||36||36||40|
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