The Intel 80286 is a 16-bit microprocessor, introduced on February 1, 1982. It was the first 8086-based CPU with separate, non-multiplexed address and data buses and the first with memory management and wide protection abilities; the 80286 used 134,000 transistors in its original nMOS incarnation and, just like the contemporary 80186, it could execute most software written for the earlier Intel 8086 and 8088 processors. The 80286 was employed for the IBM PC/AT, introduced in 1984, widely used in most PC/AT compatible computers until the early 1990s. Intel's first 80286 chips were specified for a maximum clockrate of 4, 6 or 8 MHz and releases for 12.5 MHz. AMD and Harris produced 16 MHz, 20 MHz and 25 MHz parts, respectively. Intersil and Fujitsu designed static CMOS versions of Intel's original depletion-load nMOS implementation aimed at battery-powered devices. On average, the 80286 was measured to have a speed of about 0.21 instructions per clock on "typical" programs, although it could be faster on optimized code and in tight loops, as many instructions could execute in 2 clock cycles each.
The 6 MHz, 10 MHz and 12 MHz models were measured to operate at 0.9 MIPS, 1.5 MIPS and 2.66 MIPS respectively. The E-stepping level of the 80286 was free of the several significant errata that caused problems for programmers and operating-system writers in the earlier B-step and C-step CPUs; the 80286 was designed for multi-user systems with multitasking applications, including communications and real-time process control. It had 134,000 transistors and consisted of four independent units: address unit, bus unit, instruction unit and execution unit, organized into a loosely coupled pipeline just as in the 8086; the increased performance over the 8086 was due to the non-multiplexed address and data buses, more address-calculation hardware and a faster multiplier. It was produced in a 68-pin package, including LCC and PGA packages; the performance increase of the 80286 over the 8086 could be more than 100% per clock cycle in many programs. This was a large increase comparable to the speed improvements around a decade when the i486 or the original Pentium were introduced.
This was due to the non-multiplexed address and data buses, but to the fact that address calculations were less expensive. They were performed by a dedicated unit in the 80286, while the older 8086 had to do effective address computation using its general ALU, consuming several extra clock cycles in many cases; the 80286 was more efficient in the prefetch of instructions, execution of jumps, in complex microcoded numerical operations such as MUL/DIV than its predecessor. The 80286 included, in addition to all of the 8086 instructions, all of the new instructions of the 80186: ENTER, LEAVE, BOUND, INS, OUTS, PUSHA, POPA, PUSH immediate, IMUL immediate, immediate shifts and rotates; the 80286 added new instructions for protected mode: ARPL, CLTS, LAR, LGDT, LIDT, LLDT, LMSW, LSL, LTR, SGDT, SIDT, SLDT, SMSW, STR, VERR, VERW. Some of the instructions for protected mode can be used in real mode to set up and switch to protected mode, a few are useful for real mode itself; the Intel 80286 had a 24-bit address bus and was able to address up to 16 MB of RAM, compared to the 1 MB addressability of its predecessor.
However, memory cost and the initial rarity of software using the memory above 1 MB meant that 80286 computers were shipped with more than one megabyte of RAM. Additionally, there was a performance penalty involved in accessing extended memory from real mode, as noted below; the 286 was the first of the x86 CPU family to support protected virtual-address mode called "protected mode". In addition, it was the first commercially available microprocessor with on-chip MMU capabilities; this would allow IBM compatibles to have advanced multitasking OSes for the first time and compete in the Unix-dominated server/workstation market. Several additional instructions were introduced in protected mode of 80286, which are helpful for multitasking operating systems. Another important feature of 80286 is prevention of unauthorized access; this is achieved by: Forming different segments for data and stack, preventing their overlapping. Assigning privilege levels to each segment. Segment with lower privilege level cannot access the segment with higher privilege level.
In 80286, arithmetic operations can be performed on the following different types of numbers: unsigned packed decimal, unsigned binary, unsigned unpacked decimal, signed binary, floating-point numbers. By design, the 286 could not revert from protected mode to the basic 8086-compatible real address mode without a hardware-initiated reset. In the PC/AT introduced in 1984, IBM added external circuitry, as well as specialized code in the ROM BIOS and the 8042 peripheral microcontroller to enable software to cause the reset, allowing real-mode reentry while retaining active memory and returning control to the program that initiated the reset. (The BIOS is involved because it obtains control di
Geode is a series of x86-compatible system-on-a-chip microprocessors and I/O companions produced by AMD, targeted at the embedded computing market. The series was launched by National Semiconductor as the Geode family in 1999; the original Geode processor core itself is derived from the Cyrix MediaGX platform, acquired in National's merger with Cyrix in 1997. AMD bought the Geode business from National in August 2003 to augment its existing line of embedded x86 processor products. AMD expanded the Geode series to two classes of processor: the MediaGX-derived Geode GX and LX, the modern Athlon-derived Geode NX. Geode processors are optimized for low power consumption and low cost while still remaining compatible with software written for the x86 platform; the MediaGX-derived processors lack modern features such as SSE and a large on-die L1 cache but these are offered on the more recent Athlon-derived Geode NX. Geode processors integrate some of the functions provided by a separate chipset, such as the northbridge.
Whilst the processor family is best suited for thin client, set top box and embedded computing applications, it can be found in unusual applications such as the Nao robot and the Win Enterprise IP-PBX The One Laptop per Child project used the GX series Geode processor in OLPC XO-1 prototypes, but moved to the Geode LX for production. The Linutop is based on the Geode LX. 3Com Audrey was powered by a 200 MHz Geode GX1. The SCxxxx range of Geode devices are a single-chip version, comparable to the SiS 552, VIA CoreFusion or Intel's Tolapai, which integrate the CPU, memory controller, graphics and I/O devices into one package. Single processor boards based on these processors are manufactured by Artec Group, PC Engines and Win Enterprises. Cyrix MediaGXm clone. Returns "CyrixInstead" on CPUID. MediaGX-derived core 0.35 µm, four-layer metal CMOS MMX instructions 3.3 V I/O, 2.9 V core 12 KB direct-mapped write-through unified L1 cache, 4 KB I/O scratchpad SRAM 25–33 MHz 32-bit 486 bus PCI controller 32-bit EDO DRAM memory interface CS5530 companion chip VSA architecture 1280×1024×8 or 1024×768×16 display MediaGX-derived core 0.25 µm, four-layer metal CMOS 3.3 V I/O 2.2, 2.5, 2.9 V core 12 KB direct-mapped write-through unified L1 cache, 4 KB I/O scratchpad SRAM Fully static design 1.0 W at 2.2 V/166 MHz, 2.5 W at 2.9 V/266 MHz MediaGX-derived core 0.18 µm CMOS 200–333 MHz 1.6–2.2 V core 16 KB four-way set associative write-back unified L1 cache, 2 or 4 KB of which can be reserved as I/O scratchpad RAM for use by the integrated graphics core 33 MHz PCI bus interconnect with CPU bus Integrated northbridge and memory controller 0.8–1.2 W typical 16–64-bit SDRAM memory, 111 MHz CS5530A companion chip 60 Hz VGA refresh rateNational Semiconductor/AMD SC1100 is based on the Cyrix GX1 core and the CS5530 support chip.
Announced by National Semiconductor Corporation October, 2001 at Microprocessor Forum. First demonstration at COMPUTEX Taiwan, June, 2002. 0.15 µm process technology MMX and 3DNow! Instructions 16 KB Instruction and 16 B Data caches GeodeLink architecture, 6 GB/s on-chip bandwidth, up to 2 GB/s memory bandwidth Integrated 64-bit PC133 SDRAM and DDR266 controller Clockrate: 266, 333, 400 MHz 33 MHz PCI bus interconnect with CPU bus 3 PCI masters supported 1600×1200 24-bit display with video scaling CRT DACs and an UMA DSTN/TFT controller. Geode CS5535 or CS5536 companion chip Developed by National Tel Aviv based on IP from Longmont and other sources. Applications: The SC3200 was used in the Tatung TWN-5213 CU. In 2002, AMD introduced the Geode GX series, a re-branding of the National Semiconductor GX2; this was followed by the Geode LX, running up to 667 MHz. LX brought many improvements, such as higher speed DDR, a re-designed instruction pipe, a more powerful display controller; the upgrade from the CS5535 I/O Companion to the CS5536 brought higher speed USB.
Geode GX and LX processors are found in devices such as thin clients and industrial control systems. However, they have come under competitive pressure from VIA on the x86 side, ARM processors from various vendors taking much of the low-end business; because of the relative performance, albeit higher PPW, of the GX and LX core design, AMD introduced the Geode NX, an embedded version of the Athlon processor, K7. Geode NX is quite similar to the Athlon XP-M that use this core; the Geode NX includes 256 KB of level 2 cache, runs fanless at up to 1 GHz in the NX1500@6 W version. The NX2001 part runs at 1.8 GHz, the NX1750 part runs at 1.4 GHz, the NX1250 runs at 667 MHz. The Geode NX, with its strong FPU, is suited for embedded devices with graphical performance requirements, such as information kiosks and casino gaming machines, such as video slots. However, it was reported that the specific design team for Geode processors in Longmont, has been closed, 75 employees are being relocated to the new development facility in Fort Collins, Colorado.
It is expected that the Geode line of processors will be updated less due to the closure of the Geode design center. In 2009, comments by AMD indicated that there are no plans for any future micro architecture upgrades to the processor and that there will be no successor. In 2016 AMD updated the product roadmap announcing extension of last time buy and shipment for the LX series to 2019. In early 2018 hardware manufacturer congatec announced an agreement with AMD for a further extension of availability of congatec's Geode based platforms. Features: Low powe
The AMD Family 10h, or K10, is a microprocessor microarchitecture by AMD based on the K8 microarchitecture. Though there were once reports that the K10 had been canceled, the first third-generation Opteron products for servers were launched on September 10, 2007, with the Phenom processors for desktops following and launching on November 11, 2007 as the immediate successors to the K8 series of processors, it is perceived by the PC community that from the time after the use of the codename K8 for the AMD K8 or Athlon 64 processor family, AMD no longer uses K-nomenclatures since no K-nomenclature naming convention beyond K8 has appeared in official AMD documents and press releases after the beginning of 2005. The name "K8L" was first coined by Charlie Demerjian, one of the writers of The Inquirer back in 2005, was used by the wider IT community as a convenient shorthand while according to AMD official documents, the processor family was termed "AMD Next Generation Processor Technology"; the microarchitecture has been referred to as Stars, as the codenames for desktop line of processors was named under stars or constellations.
In a video interview, Giuseppe Amato confirmed that the codename is K10. It was revealed, by The Inquirer itself, that the codename "K8L" referred to a low-power version of the K8 family named Turion 64, that K10 was the official codename for the microarchitecture. AMD refers to it as Family 10h Processors. 10h and 0Fh refer to the main result of the CPUID x86 processor instruction. In hexadecimal numbering, 0Fh equals the decimal number 15, 10h equals decimal 16. In 2003, AMD outlined the features for upcoming generations of microprocessors after the K8 family of processors in various events and analyst meetings, including the Microprocessor Forum 2003; the outlined features to be deployed by the next-generation microprocessors are as follows: Threaded architectures. Chip level multiprocessing. Huge scale MP machines. 10 GHz operation. Much higher performance superscalar, out of order CPU core. Huge caches. Media/vector processing extensions. Branch and memory hints. Security and virtualization. Enhanced Branch Predictors.
Static and dynamic power management. On April 13, 2006, Henri Richard, AMD executive vice president and chief officer for marketing and sales, acknowledged the existence of the new microarchitecture in an interview. In June 2006, AMD executive vice president Henri Richard had another interview with DigiTimes commented on the upcoming processor developments: Q: What is your broad perspective on the development of AMD processor technology over the next three to four years? A: Well, as Dirk Meyer commented at our analysts meeting, we're not standing still. We've talked about the refresh of the current K8 architecture that will come in'07, with significant improvements in many different areas of the processor, including integer performance, floating point performance, memory bandwidth, interconnections and so on. On July 21, 2006, AMD President and Chief operating officer Dirk Meyer and Senior VP Marty Seyer confirmed that the launch date of new microprocessors of Revision H under the new microarchitecture is slated for the middle of 2007.
Some of the Revision H Opterons shipped in 2007 will have a thermal design power of 68 W. On August 15, 2006, at the launch of the first Socket F dual-core Opterons, AMD announced that the firm had reached the final design stage of quad-core Opteron parts; the next stages are validation, with sampling to follow after several months. On June 29, 2007, AMD stated that server processors codenamed Barcelona will ship in August 2007, corresponding server systems from partners will ship in September of the same year. On August 13, the reported ship dates for the first Barcelona processors were set for September 10, 2007, they announced the Opteron 2350 will have core frequencies of 1.9 GHz and 2.0 GHz. In November 2007 AMD stopped delivery of Barcelona processors after a bug in the translation lookaside buffer of stepping B2 was discovered that could lead to a race condition and thus a system lockup. A patch in BIOS or software worked around the bug by disabling cache for page tables, but it was connected to a 5 to 20% performance penalty.
Kernel patches that would completely avoid this penalty were published for Linux. In April 2008, the new stepping B3 was brought to the market by AMD, including a fix for the bug plus other minor enhancements; as of November 2006, reports leaked the upcoming desktop part codenames Agena, Agena FX, the core speeds of the parts range from 2.4 GHz - 2.9 GHz 512 KB L2 cache each core, 2 MB L3 cache, using HyperTransport 3.0, with a TDP of 125 W. In recent reports, single core variants and dual core with or without L3 cache are available under the same microarchitecture. During the AMD Analyst Day 2006 on December 14, 2006, AMD announced their official timeline for server and mobile processors. For the servers segment, AMD will unveil two new processors based on the architecture codenamed "Barcelona" and "Budapest" for 8/4/2-way and 1-way servers respectively. For the second half of 2007, HyperTransport 3.0 and Socket AM2+ will be unveiled, which are designed for the specific implementation of the aforementioned consu
Advanced Micro Devices
Advanced Micro Devices, Inc. is an American multinational semiconductor company based in Santa Clara and Austin, Texas that develops computer processors and related technologies for business and consumer markets. While it manufactured its own processors, the company outsourced its manufacturing, a practice known as fabless, after GlobalFoundries was spun off in 2009. AMD's main products include microprocessors, motherboard chipsets, embedded processors and graphics processors for servers and personal computers, embedded systems applications. AMD is the second-largest supplier and only significant rival to Intel in the market for x86-based microprocessors. Since acquiring ATI in 2006, AMD and its competitor Nvidia have maintained a duopoly in the discrete Graphics Processing Unit market. Advanced Micro Devices was formally incorporated on May 1, 1969, by Jerry Sanders, along with seven of his colleagues from Fairchild Semiconductor. Sanders, an electrical engineer, the director of marketing at Fairchild, like many Fairchild executives, grown frustrated with the increasing lack of support and flexibility within the company, decided to leave to start his own semiconductor company.
The previous year Robert Noyce, who had invented the first practical integrated circuit or the microchip in 1959 at Fairchild, had left Fairchild together with Gordon Moore and founded the semiconductor company Intel in July 1968. In September 1969, AMD moved from its temporary location in Santa Clara to California. To secure a customer base, AMD became a second source supplier of microchips designed by Fairchild and National Semiconductor. AMD first focused on producing logic chips; the company guaranteed quality control to United States Military Standard, an advantage in the early computer industry since unreliability in microchips was a distinct problem that customers – including computer manufacturers, the telecommunications industry, instrument manufacturers – wanted to avoid. In November 1969, the company manufactured its first product, the Am9300, a 4-bit MSI shift register, which began selling in 1970. In 1970, AMD produced its first proprietary product, the Am2501 logic counter, successful.
Its best-selling product in 1971 was the Am2505, the fastest multiplier available. In 1971, AMD entered the RAM chip market, beginning with the Am3101, a 64-bit bipolar RAM; that year AMD greatly increased the sales volume of its linear integrated circuits, by year end the company's total annual sales reached $4.6 million. AMD went public in September 1972; the company was a second source for Intel MOS/LSI circuits by 1973, with products such as Am14/1506 and Am14/1507, dual 100-bit dynamic shift registers. By 1975, AMD was producing 212 products – of which 49 were proprietary, including the Am9102 and three low-power Schottky MSI circuits: Am25LS07, Am25LS08, Am25LS09. Intel had created the first microprocessor, its 4-bit 4004, in 1971. By 1975, AMD entered the microprocessor market with the Am9080, a reverse-engineered clone of the Intel 8080, the Am2900 bit-slice microprocessor family; when Intel began installing microcode in its microprocessors in 1976, it entered into a cross-licensing agreement with AMD, granting AMD a copyright license to the microcode in its microprocessors and peripherals, effective October 1976.
In 1977, AMD entered into a joint venture with Siemens, a German engineering conglomerate wishing to enhance its technology expertise and enter the U. S. market. Siemens purchased 20 % of AMD's stock; that year the two companies jointly established Advanced Micro Computers, located in Silicon Valley and in Germany, giving AMD an opportunity to enter the microcomputer development and manufacturing field, in particular based on AMD's second-source Zilog Z8000 microprocessors. When the two companies' vision for Advanced Micro Computers diverged, AMD bought out Siemens' stake in the U. S. division in 1979. AMD closed its Advanced Micro Computers subsidiary in late 1981, after switching focus to manufacturing second-source Intel x86 microprocessors. Total sales in fiscal year 1978 topped $100 million, in 1979, AMD debuted on the New York Stock Exchange. In 1979, production began in AMD's new semiconductor fab in Austin, Texas. In 1980, AMD began supplying semiconductor products for telecommunications, an industry undergoing rapid expansion and innovation.
Intel had introduced the first x86 microprocessors in 1978. In 1981, IBM created its PC, wanted Intel's x86 processors, but only under the condition that Intel provide a second-source manufacturer for its patented x86 microprocessors. Intel and AMD entered into a 10-year technology exchange agreement, first signed in October 1981 and formally executed in February 1982; the terms of the agreement were that each company could acquire the right to become a second-source manufacturer of semiconductor products developed by the other. The technical information and licenses needed to make and sell a part would be exchanged for a royalty to the developing company; the 1982 agreement extended the 1976 AMD–Intel cross-licensing agreement through 1995. The agreement included the right to invoke arbitration of disagreements, after five years the right of either party to end the agreement with one year's notice; the main result of the 1982 agreeme
ARM Advanced RISC Machine Acorn RISC Machine, is a family of reduced instruction set computing architectures for computer processors, configured for various environments. Arm Holdings develops the architecture and licenses it to other companies, who design their own products that implement one of those architectures—including systems-on-chips and systems-on-modules that incorporate memory, radios, etc, it designs cores that implement this instruction set and licenses these designs to a number of companies that incorporate those core designs into their own products. Processors that have a RISC architecture require fewer transistors than those with a complex instruction set computing architecture, which improves cost, power consumption, heat dissipation; these characteristics are desirable for light, battery-powered devices—including smartphones and tablet computers, other embedded systems. For supercomputers, which consume large amounts of electricity, ARM could be a power-efficient solution.
ARM Holdings periodically releases updates to the architecture. Architecture versions ARMv3 to ARMv7 support 32-bit arithmetic; the Thumb version supports a variable-length instruction set that provides both 32- and 16-bit instructions for improved code density. Some older cores can provide hardware execution of Java bytecodes. Released in 2011, the ARMv8-A architecture added support for a 64-bit address space and 64-bit arithmetic with its new 32-bit fixed-length instruction set. With over 100 billion ARM processors produced as of 2017, ARM is the most used instruction set architecture and the instruction set architecture produced in the largest quantity; the used Cortex cores, older "classic" cores, specialized SecurCore cores variants are available for each of these to include or exclude optional capabilities. The British computer manufacturer Acorn Computers first developed the Acorn RISC Machine architecture in the 1980s to use in its personal computers, its first ARM-based products were coprocessor modules for the BBC Micro series of computers.
After the successful BBC Micro computer, Acorn Computers considered how to move on from the simple MOS Technology 6502 processor to address business markets like the one, soon dominated by the IBM PC, launched in 1981. The Acorn Business Computer plan required that a number of second processors be made to work with the BBC Micro platform, but processors such as the Motorola 68000 and National Semiconductor 32016 were considered unsuitable, the 6502 was not powerful enough for a graphics-based user interface. According to Sophie Wilson, all the processors tested at that time performed about the same, with about a 4 Mbit/second bandwidth. After testing all available processors and finding them lacking, Acorn decided it needed a new architecture. Inspired by papers from the Berkeley RISC project, Acorn considered designing its own processor. A visit to the Western Design Center in Phoenix, where the 6502 was being updated by what was a single-person company, showed Acorn engineers Steve Furber and Sophie Wilson they did not need massive resources and state-of-the-art research and development facilities.
Wilson developed the instruction set, writing a simulation of the processor in BBC BASIC that ran on a BBC Micro with a 6502 second processor. This convinced Acorn engineers. Wilson approached Acorn's CEO, Hermann Hauser, requested more resources. Hauser assembled a small team to implement Wilson's model in hardware; the official Acorn RISC Machine project started in October 1983. They chose VLSI Technology as the silicon partner, as they were a source of ROMs and custom chips for Acorn. Wilson and Furber led the design, they implemented it with a similar efficiency ethos as the 6502. A key design goal was achieving low-latency input/output handling like the 6502; the 6502's memory access architecture had let developers produce fast machines without costly direct memory access hardware. The first samples of ARM silicon worked properly when first received and tested on 26 April 1985; the first ARM application was as a second processor for the BBC Micro, where it helped in developing simulation software to finish development of the support chips, sped up the CAD software used in ARM2 development.
Wilson subsequently rewrote BBC BASIC in ARM assembly language. The in-depth knowledge gained from designing the instruction set enabled the code to be dense, making ARM BBC BASIC an good test for any ARM emulator; the original aim of a principally ARM-based computer was achieved in 1987 with the release of the Acorn Archimedes. In 1992, Acorn once more won the Queen's Award for Technology for the ARM; the ARM2 featured 26-bit address space and 27 32-bit registers. Eight bits from the program counter register were available for other purposes; the address bus was extended to 32 bits in the ARM6, but program code still had to lie within the first 64 MB of memory in 26-bit compatibility mode, due to the reserved bits for the status flags. The ARM2 had a transistor count of just 30,000, compared to Motorola's six-year-older 68000 model with around 40,000. Much of this simplicity came from the lack of mic
Epyc is a brand of x86-64 microprocessors designed and marketed by AMD based on the company's Zen microarchitecture targeted for server and embedded system markets. It was introduced in June 2017. Epyc processors share the same microarchitecture as its regular desktop-grade counterparts but have enterprise-graded features such as higher core counts, more PCI Express lanes, support for larger amounts of RAM, larger cache memory, it supports multi-chip and dual-socket system configurations through the Infinity Fabric interchip interconnect. In March 2017 AMD announced a server platform based on the Zen microarchitecture, codenamed Naples, revealed it under the brand name Epyc in May; that June, AMD launched Epyc by releasing the Epyc 7000 series processors. The platform includes one- and two-socket systems. In multi-processor configurations, two Epyc CPUs communicate via AMD's Infinity Fabric; each server chip supports 8 channels of memory and 128 PCIe 3.0 lanes, of which 64 lanes from each are used for CPU-to-CPU communication through Infinity Fabric when installed in a dual-processor configuration.
All Epyc processors are composed of four eight-core Zeppelin dies in a multi-chip module, with the varying product core counts produced by symmetrically disabling cores of each core complex on each Zeppelin die. Initial reception to Epyc was positive. Epyc was found to outperform Intel CPUs in cases where the cores could work independently, such as in high-performance computing and big-data applications. Epyc fell behind in database tasks compared to Intel's Xeon parts due to higher cache latency. In November 2018 AMD announced Epyc 2 at their Next Horizon event, the second generation of Epyc processors code-named "Rome" and based on the Zen 2 microarchitecture; the processors feature up to eight 7 nm-based "chiplet" processors with a 14 nm-based IO chip in the center interconnected via Infinity fabric. The processors support up to 8 channels of DDR4 RAM up to 4TB, introduce support for PCIe 4.0. These processors have up to 64 cores with 128 SMT threads per socket. In February 2018, AMD announced the EPYC 3000 series of embedded Zen CPUs.
A variant created for the Chinese server market by a AMD–Chinese joint venture is the Hygon Dhyana system on a chip. It is noted to be a variant of the AMD EPYC, is so similar that "there is little to no differentiation between the chips", it has been noted that there is "less than 200 lines of new kernel code" for Linux kernel support, that the Dhyana is "mostly a re-branded Zen CPU for the Chinese server market"
HyperTransport known as Lightning Data Transport, is a technology for interconnection of computer processors. It is a bidirectional serial/parallel high-bandwidth, low-latency point-to-point link, introduced on April 2, 2001; the HyperTransport Consortium is in charge of developing HyperTransport technology. HyperTransport is best known as the system bus architecture of modern AMD central processing units and the associated Nvidia nForce motherboard chipsets. HyperTransport has been used by IBM and Apple for the Power Mac G5 machines, as well as a number of modern MIPS systems; the current specification HTX3.1 remains competitive for 2014 high speed DDR4 RAM and slower terabyte technology—a wider range of RAM speeds on a common CPU bus than any Intel front-side bus. Intel technologies require each speed range of RAM to have its own interface, resulting in a more complex motherboard layout but with fewer bottlenecks. HTX 3.1 at 26 GB/s can continue to serve as a unified bus for as many as four DDR4 sticks running at the fastest proposed speeds.
Beyond that DDR4 RAM may require two or more HTX 3.1 buses diminishing its value as unified transport. HyperTransport comes in four versions—1.x, 2.0, 3.0, 3.1—which run from 200 MHz to 3.2 GHz. It is a DDR or "double data rate" connection, meaning it sends data on both the rising and falling edges of the clock signal; this allows for a maximum data rate of 6400 MT/s. The operating frequency is autonegotiated with the motherboard chipset in current computing. HyperTransport supports an autonegotiated bit width. With the advent of version 3.1, using full 32-bit links and utilizing the full HyperTransport 3.1 specification's operating frequency, the theoretical transfer rate is 25.6 GB/s per direction, or 51.2 GB/s aggregated throughput, making it faster than most existing bus standard for PC workstations and servers as well as making it faster than most bus standards for high-performance computing and networking. Links of various widths can be mixed together in a single system configuration as in one 16-bit link to another CPU and one 8-bit link to a peripheral device, which allows for a wider interconnect between CPUs, a lower bandwidth interconnect to peripherals as appropriate.
It supports link splitting, where a single 16-bit link can be divided into two 8-bit links. The technology typically has lower latency than other solutions due to its lower overhead. Electrically, HyperTransport is similar to low-voltage differential signaling operating at 1.2 V. HyperTransport 2.0 added post-cursor transmitter deemphasis. HyperTransport 3.0 added scrambling and receiver phase alignment as well as optional transmitter precursor deemphasis. HyperTransport is packet-based, where each packet consists of a set of 32-bit words, regardless of the physical width of the link; the first word in a packet always contains a command field. Many packets contain a 40-bit address. An additional 32-bit control packet is prepended; the data payload is sent after the control packet. Transfers are always padded to a multiple of 32 bits, regardless of their actual length. HyperTransport packets enter the interconnect in segments known as bit times; the number of bit times required depends on the link width.
HyperTransport supports system management messaging, signaling interrupts, issuing probes to adjacent devices or processors, I/O transactions, general data transactions. There are two kinds of write commands supported: non-posted. Posted writes do not require a response from the target; this is used for high bandwidth devices such as uniform memory access traffic or direct memory access transfers. Non-posted writes require a response from the receiver in the form of a "target done" response. Reads require a response, containing the read data. HyperTransport supports the PCI consumer/producer ordering model. HyperTransport facilitates power management as it is compliant with the Advanced Configuration and Power Interface specification; this means that changes in processor sleep states can signal changes in device states, e.g. powering off disks when the CPU goes to sleep. HyperTransport 3.0 added further capabilities to allow a centralized power management controller to implement power management policies.
The primary use for HyperTransport is to replace the Intel-defined front-side bus, different for every type of Intel processor. For instance, a Pentium cannot be plugged into a PCI Express bus directly, but must first go through an adapter to expand the system; the proprietary front-side bus must connect through adapters for the various standard buses, like AGP or PCI Express. These are included in the respective controller functions, namely the northbridge and southbridge. In contrast, HyperTransport is an open specification, published by a multi-company consortium. A single HyperTransport adapter chip will work with a wide spectrum of HyperTransport enabled microprocessors. AMD uses HyperTransport to replace the front-side bus in their Opteron, Athlon 64, Athlon II, Sempron 64, Turion 64, Phenom II and FX families of microprocessors. Another use for HyperTransport is as an interconnect for NUMA multiprocessor computers. AMD uses HyperTransport with a proprietary cache coherency extension as part of their Direct Connect Architecture in their Opteron and Athlon 64 FX line of processors.