ARC (processor)

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ARC (Argonaut RISC Core) embedded processors are a family of 32-bit central processing units (CPUs) originally designed by ARC International.

ARC processors can be optimized for a wide range of uses, and are widely used in System on a chip (SoC) devices for storage, home, mobile, automotive, and Internet of things (IoT) applications. They have been licensed by more than 200 organizations and are shipped in more than 1.5 billion products per year.[1]

ARC processors use reduced instruction set computing (RISC), and employ the 16-/32-bit ARCompact instruction set architecture (ISA) that provides good performance and code density for embedded and host SoC applications.

History[edit]

The ARC concept was developed initially within Argonaut Games through a series of 3D pipeline development projects starting with the Super FX chip for the Super Nintendo Entertainment System.

In 1995, Argonaut was split into Argonaut Technologies Limited (ATL), which had a variety of technology projects, and Argonaut Software Limited (ASL).

At the start of 1996, the General Manager of Argonaut, John Edelson, started reducing ATL projects such as BRender and motion capture and investing in the development of the ARC concept. In September 1996 Rick Clucas decided that the value of the ARC processor was in other people using it rather than Argonaut doing projects using it and asked Bob Terwilliger to join as CEO, Rick Clucas then took on the role of CTO.

In 1997, following investment by Apax Partners, ATL became ARC International and totally independent from Argonaut Games. Prior to their initial public offering on the London Stock Exchange, underwritten by Goldman Sachs and five other investment banks, three related technology companies were acquired: Metaware in Santa Cruz, California (development and modeling software), VAutomation in Nashua, New Hampshire (peripheral semiconductor IP), and Precise Software in Nepean, Ontario (RTOS).

ARC International was acquired by Synopsys in 2010, and ARC processors are now part of the Synopsys DesignWare series.

Design Configuration[edit]

Designers can differentiate their products by using patented configuration technology to tailor each ARC processor instance to meet specific performance, power and area requirements.

Configuration of the ARC processors occurs at design time, using the ARChitect processor configurator.[2] The core was designed to be extensible, allowing designers to add their own custom instructions that can significantly increase performance or reduce power consumption.

Unlike most embedded microprocessors, extra instructions, registers and functionality can be added, in a modular fashion. Customers analyse the task, break down the operations, and then choose the appropriate extensions, or develop their own, to create their own custom microprocessor. They might optimise for speed, energy efficiency or code density. Extensions can include, for example, an memory management unit (MMU), a fast multiplier–accumulator, a USB Host, a Viterbi path decoder, or a user's proprietary RTL functions.

The processors are synthesizable and can be implemented in any foundry or process, and are supported by a complete suite of development tools.[3]

References[edit]

  1. ^ "Overcoming the power/performance paradox in processor IP". techdesignforums.com. Retrieved 2014-08-13. 
  2. ^ "ARChitect Processor Configurator". Arc.com. Retrieved 2014-03-02. 
  3. ^ "Accelerating Development of Performance-Efficient SoCs". synopsys.com. Retrieved 2014-08-13. 

Further reading[edit]

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