Chemical mechanical polishing/planarization is a process of smoothing surfaces with the combination of chemical and mechanical forces. It can be thought of as a hybrid of free abrasive polishing; the process uses an abrasive and corrosive chemical slurry in conjunction with a polishing pad and retaining ring of a greater diameter than the wafer. The pad and wafer are pressed together by a dynamic polishing head and held in place by a plastic retaining ring; the dynamic polishing head is rotated with different axes of rotation. This removes material and tends to out any irregular topography, making the wafer flat or planar; this may be necessary to set up the wafer for the formation of additional circuit elements. For example, CMP can bring the entire surface within the depth of field of a photolithography system, or selectively remove material based on its position. Typical depth-of-field requirements are down to Angstrom levels for the latest 22 nm technology. Typical CMP tools, such as the ones seen on the right, consist of a rotating and flat plate, covered by a pad.
The wafer, being polished is mounted upside-down in a carrier/spindle on a backing film. The retaining ring keeps the wafer in the correct horizontal position. During the process of loading and unloading the wafer onto the tool, the wafer is held by vacuum by the carrier to prevent unwanted particles from building up on the wafer surface. A slurry introduction mechanism deposits the slurry on the pad, represented by the slurry supply in Figure 1. Both the plate and the carrier are rotated and the carrier is kept oscillating. A downward pressure/down force is applied to the carrier. Down force depends on the contact area which, in turn, is dependent on the structures of both the wafer and the pad; the pads have a roughness of 50 µm. In CMP, the mechanical properties of the wafer itself must be considered too. If the wafer has a bowed structure, the pressure will be greater on the edges than it would on the center, which causes non-uniform polishing. In order to compensate for the wafer bow, pressure can be applied to the wafer's backside which, in turn, will equalize the centre-edge differences.
The pads used in the CMP tool should be rigid. However, these rigid pads must be kept in alignment with the wafer at all times. Therefore, real pads are just stacks of soft and hard materials that conform to wafer topography to some extent; these pads are made from porous polymeric materials with a pore size between 30-50 µm, because they are consumed in the process, they must be reconditioned. In most cases the pads are much proprietary, are referred to by their trademark names rather than their chemical or other properties. Before about 1990 CMP was viewed as too "dirty" to be included in high-precision fabrication processes, since abrasion tends to create particles and the abrasives themselves are not without impurities. Since that time, the integrated circuit industry has moved from aluminum to copper conductors; this required the development of an additive patterning process, which relies on the unique abilities of CMP to remove material in a planar and uniform fashion and to stop repeatably at the interface between copper and oxide insulating layers.
Adoption of this process has made CMP processing much more widespread. In addition to aluminum and copper, CMP processes have been developed for polishing tungsten, silicon dioxide, carbon nanotubes. There are several limitations of CMP that appear during the polishing process requiring optimization of a new technology. In particular, an improvement in wafer metrology is required. In addition, it was discovered that the CMP process has several potential defects including stress cracking, delaminating at weak interfaces, corrosive attacks from slurry chemicals; the oxide polishing process, the oldest and most used in today's industry, has one problem: a lack of end points requires blind polishing, making it hard to determine when the desired amount of material has been removed or the desired degree of planarization has been obtained. If the oxide layer has not been sufficiently thinned and/or the desired degree of planarity has not been achieved during this process the wafer can be repolished, but in a practical sense this is unattractive in production and is to be avoided if at all possible.
If the oxide thickness is too thin or too non-uniform the wafer must be reworked, an less attractive process and one, to fail. This method is time-consuming and costly since technicians have to be more attentive while performing this process. Shallow trench isolation, a process used to fabricate semiconductor devices, is a technique used to enhance the isolation between devices and active areas. Moreover, STI has a higher degree of planarity making it essential in photolithographic applications, depth of focus budget by decreasing minimum line width. To planarize shallow trenches, a common method should be used such as the combination of resist etching-back and chemical mechanical polishing; this process comes in a sequence pattern. First, the isolation trench pattern is transferred to the silicon wafer. Oxide is deposited on the wafer in the shape of trenches. A photo
Integrated circuit packaging
In electronics manufacturing, integrated circuit packaging is the final stage of semiconductor device fabrication, in which the block of semiconductor material is encapsulated in a supporting case that prevents physical damage and corrosion. The case, known as a "package", supports the electrical contacts which connect the device to a circuit board. In the integrated circuit industry, the process is referred to as packaging. Other names include semiconductor device assembly, encapsulation or sealing; the packaging stage is followed by testing of the integrated circuit. The term is sometimes confused with electronic packaging, the mounting and interconnecting of integrated circuits onto printed-circuit boards; the current-carrying traces that run out of the die, through the package, into the printed circuit board have different electrical properties compared to on-chip signals. They require special design techniques and need much more electric power than signals confined to the chip itself. Therefore, it is important that the materials used as electrical contacts exhibit characteristics like low resistance, low capacitance and low inductance.
Both the structure and materials must prioritize signal transmission properties, while minimizing any parasitic elements that could negatively affect the signal. Controlling these characteristics is becoming important as the rest of technology begins to speed up. Packaging delays have the potential to make up half of a high-performance computer's delay, this bottleneck on speed is expected to increase; the integrated circuit package is responsible for keeping the chip safe from all sorts of potential damage. The package must resist physical breakage, provide an airtight seal to keep out moisture, provide effective heat dissipation away from the chip. At the same time, it must have effective means of connecting to a PCB, which can change drastically depending on the package type; the materials used for the body of the package are either plastic or ceramic. They both can offer decent mechanical strength. Ceramic has more preferable characteristics, but is more expensive. Increasing the surface area of the package allows for better heat transfer via convection, some packages utilize metallic fins to enhance heat transfer further at the cost of valuable space.
Larger sizes allow for a greater number of mechanical connections. However, these factors are balanced out by the fact that the package needs to be kept as small as possible. Cost is a major limiting factor for many designs. Choices such as package material and level of precision must be balanced by the economic viability of the end product. Depending on the needs of the system, opting for lower-cost materials is an acceptable solution to economic constraints. An inexpensive plastic package can dissipate heat up to 2W, sufficient for many simple applications, though a similar ceramic package can dissipate up to 50W in the same scenario; as the chips inside the package get smaller and faster, they tend to get hotter. As the subsequent need for more effective heat dissipation increases, the cost of packaging rises along with it; the smaller and more complex the package needs to be, the more expensive it is to manufacture. The earliest integrated circuits were packaged in ceramic flat packs, which the military used for many years for their reliability and small size.
The other type of packaging used in the 1970s, called the ICP, was the ceramic package, with the conductors on one side, co-axially with the package axe. Commercial circuit packaging moved to the dual in-line package, first in ceramic and in plastic. In the 1980s VLSI pin counts exceeded the practical limit for DIP packaging, leading to pin grid array and leadless chip carrier packages. Surface mount packaging appeared in the early 1980s and became popular in the late 1980s, using finer lead pitch with leads formed as either gull-wing or J-lead, as exemplified by small-outline integrated circuit — a carrier which occupies an area about 30 – 50% less than an equivalent DIP, with a typical thickness, 70% less; the next big innovation was the area array package, which places the interconnection terminals throughout the surface area of the package, providing a greater number of connections than previous package types where only the outer perimeter is used. The first area array package was a ceramic pin grid array package.
Not long after, the plastic ball grid array, another type of area array package, became one of the most used packaging techniques. In the late 1990s, plastic quad flat pack and thin small-outline packages replaced PGA packages as the most common for high pin count devices, though PGA packages are still used for microprocessors. However, industry leaders Intel and AMD transitioned in the 2000s from PGA packages to land grid array packages. Ball grid array packages have existed since the 1970s, but evolved into flip-chip ball grid array packages in the 1990s. FCBGA packages allow for much higher pin count than any existing package types. In an FCBGA package, the die is mounted upside-down and connects to the package balls via a substrate, similar to a printed-circuit board rather than by wires. FCBGA packages allow an array of input-output signals to be distributed over the entire die rather than being confined to the die periphery. Traces out of the die, through the package, into the printed circuit board have different electrical properties, compared to on-chip signals.
An integrated circuit or monolithic integrated circuit is a set of electronic circuits on one small flat piece of semiconductor material, silicon. The integration of large numbers of tiny transistors into a small chip results in circuits that are orders of magnitude smaller and faster than those constructed of discrete electronic components; the IC's mass production capability and building-block approach to circuit design has ensured the rapid adoption of standardized ICs in place of designs using discrete transistors. ICs are now used in all electronic equipment and have revolutionized the world of electronics. Computers, mobile phones, other digital home appliances are now inextricable parts of the structure of modern societies, made possible by the small size and low cost of ICs. Integrated circuits were made practical by mid-20th-century technology advancements in semiconductor device fabrication. Since their origins in the 1960s, the size and capacity of chips have progressed enormously, driven by technical advances that fit more and more transistors on chips of the same size – a modern chip may have many billions of transistors in an area the size of a human fingernail.
These advances following Moore's law, make computer chips of today possess millions of times the capacity and thousands of times the speed of the computer chips of the early 1970s. ICs have two main advantages over discrete circuits: performance. Cost is low because the chips, with all their components, are printed as a unit by photolithography rather than being constructed one transistor at a time. Furthermore, packaged ICs use much less material than discrete circuits. Performance is high because the IC's components switch and consume comparatively little power because of their small size and close proximity; the main disadvantage of ICs is the high cost to fabricate the required photomasks. This high initial cost means. An integrated circuit is defined as: A circuit in which all or some of the circuit elements are inseparably associated and electrically interconnected so that it is considered to be indivisible for the purposes of construction and commerce. Circuits meeting this definition can be constructed using many different technologies, including thin-film transistors, thick-film technologies, or hybrid integrated circuits.
However, in general usage integrated circuit has come to refer to the single-piece circuit construction known as a monolithic integrated circuit. Arguably, the first examples of integrated circuits would include the Loewe 3NF. Although far from a monolithic construction, it meets the definition given above. Early developments of the integrated circuit go back to 1949, when German engineer Werner Jacobi filed a patent for an integrated-circuit-like semiconductor amplifying device showing five transistors on a common substrate in a 3-stage amplifier arrangement. Jacobi disclosed cheap hearing aids as typical industrial applications of his patent. An immediate commercial use of his patent has not been reported; the idea of the integrated circuit was conceived by Geoffrey Dummer, a radar scientist working for the Royal Radar Establishment of the British Ministry of Defence. Dummer presented the idea to the public at the Symposium on Progress in Quality Electronic Components in Washington, D. C. on 7 May 1952.
He gave many symposia publicly to propagate his ideas and unsuccessfully attempted to build such a circuit in 1956. A precursor idea to the IC was to create small ceramic squares, each containing a single miniaturized component. Components could be integrated and wired into a bidimensional or tridimensional compact grid; this idea, which seemed promising in 1957, was proposed to the US Army by Jack Kilby and led to the short-lived Micromodule Program. However, as the project was gaining momentum, Kilby came up with a new, revolutionary design: the IC. Newly employed by Texas Instruments, Kilby recorded his initial ideas concerning the integrated circuit in July 1958 demonstrating the first working integrated example on 12 September 1958. In his patent application of 6 February 1959, Kilby described his new device as "a body of semiconductor material … wherein all the components of the electronic circuit are integrated." The first customer for the new invention was the US Air Force. Kilby won the 2000 Nobel Prize in Physics for his part in the invention of the integrated circuit.
His work was named an IEEE Milestone in 2009. Half a year after Kilby, Robert Noyce at Fairchild Semiconductor developed a new variety of integrated circuit, more practical than Kilby's implementation. Noyce's design was made of silicon. Noyce credited Kurt Lehovec of Sprague Electric for the principle of p–n junction isolation, a key concept behind the IC; this isolation allows each transistor to operate independently despite being part of the same piece of silicon. Fairchild Semiconductor was home of the first silicon-gate IC technology with self-aligned gates, the basis of all modern CMOS integrated circuits; the technology was developed by Italian physicist Federico Faggin in 1968. In 1970, he joined Intel in order to develop the first single-chip central processing unit microprocessor, the Intel 4004, for which he received the National Medal of Technology and Innovation in 2010; the 4004 was designed by Busicom's Masatoshi Shima and Intel's Ted Hoff in 1969, but it was Faggin's improved design in 1970 that made it a reality.
Advances in IC technology smaller features and la
Chemical vapor deposition
Chemical vapor deposition is a deposition method used to produce high quality, high-performance, solid materials under vacuum. The process is used in the semiconductor industry to produce thin films. In typical CVD, the wafer is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the desired deposit. Volatile by-products are produced, which are removed by gas flow through the reaction chamber. Microfabrication processes use CVD to deposit materials in various forms, including: monocrystalline, polycrystalline and epitaxial; these materials include: silicon, fluorocarbons, tungsten, titanium nitride and various high-k dielectrics. CVD is practiced in a variety of formats; these processes differ in the means by which chemical reactions are initiated. Classified by operating conditions: Atmospheric pressure CVD – CVD at atmospheric pressure. Low-pressure CVD – CVD at sub-atmospheric pressures. Reduced pressures tend to reduce unwanted gas-phase reactions and improve film uniformity across the wafer.
Ultrahigh vacuum CVD – CVD at low pressure below 10−6 Pa. Note that in other fields, a lower division between high and ultra-high vacuum is common 10−7 Pa. Most modern CVD is either LPCVD or UHVCVD. Classified by physical characteristics of vapor: Aerosol assisted CVD – CVD in which the precursors are transported to the substrate by means of a liquid/gas aerosol, which can be generated ultrasonically; this technique is suitable for use with non-volatile precursors. Direct liquid injection CVD – CVD in which the precursors are in liquid form. Liquid solutions are injected in a vaporization chamber towards injectors; the precursor vapors are transported to the substrate as in classical CVD. This technique is suitable for use on solid precursors. High growth rates can be reached using this technique. Classified by type of substrate heating: Hot wall CVD – CVD in which the chamber is heated by an external power source and the substrate is heated by radiation from the heated chamber walls. Cold wall CVD – CVD in which only the substrate is directly heated either by induction or by passing current through the substrate itself or a heater in contact with the substrate.
The chamber walls are at room temperature. Plasma methods: Microwave plasma-assisted CVD Plasma-Enhanced CVD – CVD that utilizes plasma to enhance chemical reaction rates of the precursors. PECVD processing allows deposition at lower temperatures, critical in the manufacture of semiconductors; the lower temperatures allow for the deposition of organic coatings, such as plasma polymers, that have been used for nanoparticle surface functionalization. Remote plasma-enhanced CVD – Similar to PECVD except that the wafer substrate is not directly in the plasma discharge region. Removing the wafer from the plasma region allows processing temperatures down to room temperature. Atomic-layer CVD – Deposits successive layers of different substances to produce layered, crystalline films. See Atomic layer epitaxy. Combustion Chemical Vapor Deposition – Combustion Chemical Vapor Deposition or flame pyrolysis is an open-atmosphere, flame-based technique for depositing high-quality thin films and nanomaterials.
Hot filament CVD – known as catalytic CVD or more initiated CVD, this process uses a hot filament to chemically decompose the source gases. The filament temperature and substrate temperature thus are independently controlled, allowing colder temperatures for better absorption rates at the substrate and higher temperatures necessary for decomposition of precursors to free radicals at the filament. Hybrid Physical-Chemical Vapor Deposition – This process involves both chemical decomposition of precursor gas and vaporization of a solid source. Metalorganic chemical vapor deposition – This CVD process is based on metalorganic precursors. Rapid thermal CVD – This CVD process uses heating lamps or other methods to heat the wafer substrate. Heating only the substrate rather than the gas or chamber walls helps reduce unwanted gas-phase reactions that can lead to particle formation. Vapor-phase epitaxy Photo-initiated CVD – This process uses UV light to stimulate chemical reactions, it is similar to plasma processing, given.
Under certain conditions, PICVD can be operated near atmospheric pressure. Laser Chemical vapor deposition - This CVD process uses lasers to heat spots or lines on a substrate in semiconductor applications. In MEMS and in fiber production the lasers are used to break down the precursor gas-process temperature can exceed 2000 °C-to build up a solid structure in much the same way as laser sintering based 3-D printers build up solids from powders. CVD is used to deposit conformal films and augment substrate surfaces in ways that more traditional surface modification techniques are not capable of. CVD is useful in the process of atomic layer deposition at depositing thin layers of material. A variety of applications for such films exist. Gallium arsenide is used in photovoltaic devices. Amorphous polysilicon is used in photovoltaic devices. Certain carbides and nitrides confer wear-resistance. Polymerization by CVD the most versatile of all applications, allows for super-thin coatings which possess some de
Wafer testing is a step performed during semiconductor device fabrication. During this step, performed before a wafer is sent to die preparation, all individual integrated circuits that are present on the wafer are tested for functional defects by applying special test patterns to them; the wafer testing is performed by a piece of test equipment called a wafer prober. The process of wafer testing can be referred to in several ways: Wafer Final Test, Electronic Die Sort and Circuit Probe are the most common. A wafer prober is a machine used to test integrated circuits. For electrical testing a set of microscopic contacts or probes called a probe card are held in place whilst the wafer, vacuum-mounted on a wafer chuck, is moved into electrical contact; when a die have been electrically tested the prober moves the wafer to the next die and the next test can start. The wafer prober is responsible for loading and unloading the wafers from their carrier and is equipped with automatic pattern recognition optics capable of aligning the wafer with sufficient accuracy to ensure accurate registration between the contact pads on the wafer and the tips of the probes.
For today's multi-die packages such as stacked chip-scale package or system in package – the development of non-contact probes for identification of known tested die and known good die are critical to increasing overall system yield. The wafer prober exercises any test circuitry on the wafer scribe lines; some companies get most of their information about device performance from these scribe line test structures. When all test patterns pass for a specific die, its position is remembered for use during IC packaging. Sometimes a die has internal spare resources available for repairing. If redundancy of failed die is not possible the die is discarded. Non-passing circuits are marked with a small dot of ink in the middle of the die, or the information of passing/non-passing is stored in a file, named a wafermap; this map categorizes the non-passing dies by making use of bins. A bin is defined as a good or bad die; this wafermap is sent to the die attachment process which only picks up the passing circuits by selecting the bin number of good dies.
The process where no ink dot is used to mark the bad dies is named substrate mapping. When ink dots are used, vision systems on subsequent die handling equipment can disqualify the die by recognizing the ink dot. In some specific cases, a die that passes some but not all test patterns can still be used as a product with limited functionality; the most common example of this is a microprocessor for which only one part of the on-die cache memory is functional. In this case, the processor can sometimes still be sold as a lower cost part with a smaller amount of memory and thus lower performance. Additionally when bad dies have been identified, the die from the bad bin can be used by production personnel for assembly line setup; the contents of all test patterns and the sequence by which they are applied to an integrated circuit are called the test program. After IC packaging, a packaged chip will be tested again during the IC testing phase with the same or similar test patterns. For this reason, one might think that wafer testing is an redundant step.
In reality this is not the case, since the removal of defective dies saves the considerable cost of packaging faulty devices. However, when the production yield is so high that wafer testing is more expensive than the packaging cost of defect devices, the wafer testing step can be skipped altogether and dies will undergo blind assembly. Bond characterization Non-contact wafer testing Wafer bonding Fundamentals of Digital Semiconductor Testing by Guy A. Perry ISBN 978-0965879705 Principles of Semiconductor Network Testing by Amir Afshar, 1995 ISBN 978-0-7506-9472-8 Power-Constrained Testing of VLSI Circuits. A Guide to the IEEE 1149.4 Test Standard by Nicola Nicolici and Bashir M. Al-Hashimi ISBN 978-0-306-48731-6 Semiconductor Memories: Technology and Reliability by Ashok K. Sharma ISBN 978-0780310001
Polycrystalline silicon called polysilicon or poly-Si, is a high purity, polycrystalline form of silicon, used as a raw material by the solar photovoltaic and electronics industry. Polysilicon is produced from metallurgical grade silicon by a chemical purification process, called the Siemens process; this process involves distillation of volatile silicon compounds, their decomposition into silicon at high temperatures. An emerging, alternative process of refinement uses a fluidized bed reactor; the photovoltaic industry produces upgraded metallurgical-grade silicon, using metallurgical instead of chemical purification processes. When produced for the electronics industry, polysilicon contains impurity levels of less than one part per billion, while polycrystalline solar grade silicon is less pure. A few companies from China, Japan and the United States, such as GCL-Poly, Wacker Chemie, OCI, Hemlock Semiconductor, as well as the Norwegian headquartered REC, accounted for most of the worldwide production of about 230,000 tonnes in 2013.
The polysilicon feedstock – large rods broken into chunks of specific sizes and packaged in clean rooms before shipment – is directly cast into multicrystalline ingots or submitted to a recrystallization process to grow single crystal boules. The products are sliced into thin silicon wafers and used for the production of solar cells, integrated circuits and other semiconductor devices. Polysilicon consists of small crystals known as crystallites, giving the material its typical metal flake effect. While polysilicon and multisilicon are used as synonyms, multicrystalline refers to crystals larger than 1 mm. Multicrystalline solar cells are the most common type of solar cells in the fast-growing PV market and consume most of the worldwide produced polysilicon. About 5 tons of polysilicon is required to manufacture 1 megawatt of conventional solar modules. Polysilicon is distinct from monocrystalline silicon and amorphous silicon. In single crystal silicon known as monocrystalline silicon, the crystalline framework is homogenous, which can be recognized by an external colouring.
The entire sample is one single and unbroken crystal as its structure contains no grain boundaries. Large single crystals are rare in nature and can be difficult to produce in the laboratory. In contrast, in an amorphous structure the order in atomic positions is limited to short range. Polycrystalline and paracrystalline phases are composed of a number of smaller crystals or crystallites. Polycrystalline silicon is a material consisting of multiple small silicon crystals. Polycrystalline cells can be recognized by a visible grain, a "metal flake effect". Semiconductor grade polycrystalline silicon is converted to "single crystal" silicon – meaning that the randomly associated crystallites of silicon in "polycrystalline silicon" are converted to a large "single" crystal. Single crystal silicon is used to manufacture most Si-based microelectronic devices. Polycrystalline silicon can be as much as 99.9999% pure. Ultra-pure poly is used in the semiconductor industry, starting from poly rods that are two to three meters in length.
In microelectronic industry, poly is used both at the micro-scale level. Single crystals are grown using the Czochralski float-zone and Bridgman techniques. At the component level, polysilicon has long been used as the conducting gate material in MOSFET and CMOS processing technologies. For these technologies it is deposited using low-pressure chemical-vapour deposition reactors at high temperatures and is heavily doped n-type or p-type. More intrinsic and doped polysilicon is being used in large-area electronics as the active and/or doped layers in thin-film transistors. Although it can be deposited by LPCVD, plasma-enhanced chemical vapour deposition, or solid-phase crystallization of amorphous silicon in certain processing regimes, these processes still require high temperatures of at least 300 °C; these temperatures make deposition of polysilicon possible for glass substrates but not for plastic substrates. The deposition of polycrystalline silicon on plastic substrates is motivated by the desire to be able to manufacture digital displays on flexible screens.
Therefore, a new technique called laser crystallization has been devised to crystallize a precursor amorphous silicon material on a plastic substrate without melting or damaging the plastic. Short, high-intensity ultraviolet laser pulses are used to heat the deposited a-Si material to above the melting point of silicon, without melting the entire substrate; the molten silicon will crystallize as it cools. By controlling the temperature gradients, researchers have been able to grow large grains, of up to hundreds of micrometers in size in the extreme case, although grain sizes of 10 nanometers to 1 micrometer are common. In order to create devices on polysilicon over large-areas however, a crystal grain size smaller than the device feature size is needed for homogeneity of the devices. Another method to produce poly-Si at low temperatures is metal-induced crystallization where an amorphous-Si thin film can be crystallized at temperatures as low as 150 °C if annealed while in contact of another metal film such as aluminium, gold, or silver.
Polysilicon has many applications in VLSI manufacturing. One of its primary uses is as gate electrode material for MOS devices. A polysilicon gate's electrical conductivity may be increased by depositing a metal or a metal silicide (such as tungsten silici
Die preparation is a step of semiconductor device fabrication during which a wafer is prepared for IC packaging and IC testing. The process of die preparation consists of two steps: wafer mounting and wafer dicing. Wafer mounting is a step, performed during the die preparation of a wafer as part of the process of semiconductor fabrication. During this step, the wafer is mounted on a plastic tape, attached to a ring. Wafer mounting is performed right; the adhesive film upon which the wafer is mounted ensures that the individual dies remain in place during'dicing', as the process of cutting the wafer is called. The picture on the right shows a 300 mm wafer after it was diced; the blue plastic is the adhesive tape. The wafer is the round disc in the middle. In this case, a large number of dies were removed. In the manufacturing of micro-electronic devices, die cutting, dicing or singulation is a process of reducing a wafer containing multiple identical integrated circuits to individual dies each containing one of those circuits.
During this process, a wafer with up to thousands of circuits is cut into rectangular pieces, each called a die. In between those functional parts of the circuits, a thin non-functional spacing is foreseen where a saw can safely cut the wafer without damaging the circuits; this spacing is called the scribe saw street. The width of the scribe is small around 100 μm. A thin and accurate saw is therefore needed to cut the wafer into pieces; the dicing is performed with a water-cooled circular saw with diamond-tipped teeth. The most common make up of blade used is either a metal or resin bond containing abrasive grit of natural or more synthetic diamond, or borazon in various forms. Alternatively, the bond and grit may be applied as a coating to a metal former. See diamond tools. Kaeslin, Digital Integrated Circuit Design, from VLSI Architectures to CMOS Fabrication, Cambridge University Press, section 11.4