Photolithography called optical lithography or UV lithography, is a process used in microfabrication to pattern parts of a thin film or the bulk of a substrate. It uses light to transfer a geometric pattern from a photomask to a photosensitive chemical photoresist on the substrate. A series of chemical treatments either etches the exposure pattern into the material or enables deposition of a new material in the desired pattern upon the material underneath the photoresist. In complex integrated circuits, a CMOS wafer may go through the photolithographic cycle as many as 50 times. Photolithography shares some fundamental principles with photography in that the pattern in the photresist etching is created by exposing it to light, either directly or with a projected image using a photomask; this procedure is comparable to a high precision version of the method used to make printed circuit boards. Subsequent stages in the process have more in common with etching than with lithographic printing; this method can create small patterns, down to a few tens of nanometers in size.
It provides precise control of the shape and size of the objects it creates and can create patterns over an entire surface cost-effectively. Its main disadvantages are that it requires a flat substrate to start with, it is not effective at creating shapes that are not flat, it can require clean operating conditions. Photolithography is the standard method of printed circuit microprocessor fabrication; the root words photo and graphy all have Greek origins, with the meanings'light','stone' and'writing' respectively. As suggested by the name compounded from them, photolithography is a printing method in which light plays an essential role. In the 1820s, Nicephore Niepce invented a photographic process that used Bitumen of Judea, a natural asphalt, as the first photoresist. A thin coating of the bitumen on a sheet of metal, glass or stone became less soluble where it was exposed to light; the light-sensitivity of bitumen was poor and long exposures were required, but despite the introduction of more sensitive alternatives, its low cost and superb resistance to strong acids prolonged its commercial life into the early 20th century.
In 1940, Oskar Süß created a positive photoresist by using diazonaphthoquinone, which worked in the opposite manner: the coating was insoluble and was rendered soluble where it was exposed to light. In 1954, Louis Plambeck Jr. developed the Dycryl polymeric letterpress plate, which made the platemaking process faster. In 1952, the U. S. military assigned Jay W. Lathrop and James R. Nall at the National Bureau of Standards with the task of finding a way to reduce the size of electronic circuits in order to better fit the necessary circuitry in the limited space available inside a proximity fuze. Inspired by the application of photoresist, a photosensitive liquid used to mark the boundaries of rivet holes in metal aircraft wings, Nall determined that a similar process can be used to protect the germanium in the transistors and pattern the surface with light. During development and Nall were successful in creating a 2D miniaturized hybrid integrated circuit with transistors using this technique.
In 1958, during the IRE Professional Group on Electron Devices conference in Washington, D. C. they presented the first paper to describe the fabrication of transistors using photographic techniques and adopted the term “photolithography” to describe the process, marking the first published use of the term to describe semiconductor device patterning. Despite the fact that photolithography of electronic components concerns etching metal duplicates, rather than etching stone to produce a "master" as in conventional lithographic printing and Nall chose the term “photolithography” over “photoetching” because the former sounded “high tech.” A year after the conference and Nall’s patent on photolithography was formally approved on June 9, 1959. Photolithography would contribute to the development of the first semiconductor ICs as well as the first microchips. A single iteration of photolithography combines several steps in sequence. Modern cleanrooms use robotic wafer track systems to coordinate the process.
The procedure described here omits some advanced treatments, such as thinning agents or edge-bead removal. If organic or inorganic contaminations are present on the wafer surface, they are removed by wet chemical treatment, e.g. the RCA clean procedure based on solutions containing hydrogen peroxide. Other solutions made with trichloroethylene, acetone or methanol can be used to clean; the wafer is heated to a temperature sufficient to drive off any moisture that may be present on the wafer surface, 150 °C for ten minutes is sufficient. Wafers that have been in storage must be chemically cleaned to remove contamination. A liquid or gaseous "adhesion promoter", such as Bisamine, is applied to promote adhesion of the photoresist to the wafer; the surface layer of silicon dioxide on the wafer reacts with HMDS to form tri-methylated silicon-dioxide, a water repellent layer not unlike the layer of wax on a car's paint. This water repellent layer prevents the aqueous developer from penetrating between the photoresist layer and the wafer's
The Intel 8088 microprocessor is a variant of the Intel 8086. Introduced on July 1, 1979, the 8088 had an eight-bit external data bus instead of the 16-bit bus of the 8086; the 16-bit registers and the one megabyte address range were however. In fact, according to the Intel documentation, the 8086 and 8088 have the same execution unit —only the bus interface unit is different; the original IBM PC was based on the 8088. The 8088 was designed at Intel's laboratory in Haifa, Israel, as were a large number of Intel's processors; the 8088 was targeted at economical systems by allowing the use of an eight-bit data path and eight-bit support and peripheral chips. The prefetch queue of the 8088 was shortened to four bytes, from the 8086's six bytes, the prefetch algorithm was modified to adapt to the narrower bus; these modifications of the basic 8086 design were one of the first jobs assigned to Intel's then-new design office and laboratory in Haifa. Variants of the 8088 with more than 5 MHz maximal clock frequency include the 8088-2, fabricated using Intel's new enhanced nMOS process called HMOS and specified for a maximal frequency of 8 MHz.
Followed the 80C88, a static CHMOS design, which could operate with clock speeds from 0 to 8 MHz. There were several other, more or less similar, variants from other manufacturers. For instance, the NEC V20 was a pin-compatible and faster variant of the 8088, designed and manufactured by NEC. Successive NEC 8088 compatible processors would run at up to 16 MHz. In 1984, Commodore International signed a deal to manufacture the 8088 for use in a licensed Dynalogic Hyperion clone, in a move, regarded as signaling a major new direction for the company; when announced, the list price of the 8088 was US$124.80. The 8088 is architecturally similar to the 8086; the main difference is. All of the other pins of the device perform the same function as they do with the 8086 with two exceptions. First, pin 34 is no longer BHE. Instead it outputs a maximum mode status, SSO. Combined with the IO/M and DT/R signals, the bus cycles can be decoded; the second change is the pin that signals whether a memory access or input/output access is being made has had it sense reversed.
The pin on the 8088 is IO/M. On the 8086 part it is IO/M; the reason for the reversal is that it makes the 8088 compatible with the 8085. Depending on the clock frequency, the number of memory wait states, as well as on the characteristics of the particular application program, the average performance for the Intel 8088 ranged from 0.33 to 1 million instructions per second. Meanwhile, the mov reg,reg and ALU reg,reg instructions, taking two and three cycles yielded an absolute peak performance of between 1⁄3 and 1⁄2 MIPS per MHz, that is, somewhere in the range 3–5 MIPS at 10 MHz; the speed of the execution unit and the bus of the 8086 CPU was well balanced. Cutting down the bus to eight bits made it a serious bottleneck in the 8088. With the speed of instruction fetch reduced by 50% in the 8088 as compared to the 8086, a sequence of fast instructions can drain the four-byte prefetch queue; when the queue is empty, instructions take as long to complete. Both the 8086 and 8088 take four clock cycles to complete a bus cycle.
Therefore, for example, a two-byte shift or rotate instruction, which takes the EU only two clock cycles to execute takes eight clock cycles to complete if it is not in the prefetch queue. A sequence of such fast instructions prevents the queue from being filled as fast as it is drained, in general, because so many basic instructions execute in fewer than four clocks per instruction byte—including all the ALU and data-movement instructions on register operands and some of these on memory operands—it is impossible to avoid idling the EU in the 8088 at least ¼ of the time while executing useful real-world programs, it is not hard to idle it half the time. In short, an 8088 runs about half as fast as 8086 clocked at the same rate, because of the bus bottleneck. A side effect of the 8088 design, with the slow bus and the small prefetch queue, is that the speed of code execution can be dependent on instruction order; when programming the 8088, for CPU efficiency, it is vital to interleave long-running instructions with short ones whenever possible.
For example, a repeated string operation or a shift by three or more will take long enough to allow time for the 4-byte prefetch queue to fill. If short instructions are placed between slower instructions like these, the short ones can execute at full speed out of the queue. If, on the other hand, the slow instructions are executed sequentially, back to back after the first of them the bus unit will be forced to idle because the queue will be full, with the consequence that more of the faster instructions will suffer fetch delays that might have been avoidable; as some instructions, such as single-bit-position shifts and rotates, take 4 times as long to fetch as to execute, the overall effec
The Intel MCS-51 is a single chip microcontroller series developed by Intel in 1980 for use in embedded systems. The architect of the instruction set of the Intel MCS-51 was John H. Wharton. Intel's original versions were popular in the 1980s and early 1990s and enhanced binary compatible derivatives remain popular today, it is an example of a complex instruction set computer, has separate memory spaces for program instructions and data. Intel's original MCS-51 family was developed using N-type metal-oxide-semiconductor technology like its predecessor Intel MCS-48, but versions, identified by a letter C in their name used complementary metal–oxide–semiconductor technology and consume less power than their NMOS predecessors; this made them more suitable for battery-powered devices. The family was continued in 1996 with the enhanced 8-bit MCS-151 and the 8/16/32-bit MCS-251 family of binary compatible microcontrollers. While Intel no longer manufactures the MCS-51, MCS-151 and MCS-251 family, enhanced binary compatible derivatives made by numerous vendors remain popular today.
Some derivatives integrate a digital signal processor. Beyond these physical devices, several companies offer MCS-51 derivatives as IP cores for use in field-programmable gate array or application-specific integrated circuit designs; the 8051 architecture provides many functions in one package: 8-bit arithmetic logic unit and accumulator, 8-bit registers, 8-bit data bus and 2×16-bit address bus, program counter, data pointer, related 8/11/16-bit operations. This feature helped cement the 8051's popularity in industrial control applications because it reduced code size by as much as 30%. Another feature is the inclusion of four bank selectable working register sets which reduce the amount of time required to perform the context switches to enter and leave interrupt service routines. With one instruction, the 8051 can switch register banks, avoiding the time consuming task of transferring the critical registers to RAM. Once a UART, a timer if necessary, has been configured, the programmer needs only write a simple interrupt routine to refill the send shift register whenever the last bit is shifted out by the UART and/or empty the full receive shift register.
The main program performs serial reads and writes by reading and writing 8-bit data to stacks. As of 2013, new derivatives are still developed by many major chipmakers, major compiler suppliers such as IAR Systems and Altium Tasking continuously release updates. MCS-51 based microcontrollers include one or two UARTs, two or three timers, 128 or 256 bytes of internal data RAM, up to 128 bytes of I/O, 512 bytes to 64 KB of internal program memory, sometimes a quantity of extended data RAM located in the external data space. External RAM and ROM share the data and address buses; the original 8051 core ran at 12 clock cycles per machine cycle, with most instructions executing in one or two machine cycles. With a 12 MHz clock frequency, the 8051 could thus execute 1 million one-cycle instructions per second or 500,000 two-cycle instructions per second. Enhanced 8051 cores are now used which run at six, two, or one clock per machine cycle, have clock frequencies of up to 100 MHz, are thus capable of an greater number of instructions per second.
All Silicon Labs, some Dallas and a few Atmel devices have single cycle cores. 8051 variants may include built-in reset timers with brown-out detection, on-chip oscillators, self-programmable flash ROM program memory, built-in external RAM, extra internal program storage, bootloader code in ROM, EEPROM non-volatile data storage, I²C, SPI, USB host interfaces, CAN or LIN bus, ZigBee or Bluetooth radio modules, PWM generators, analog comparators, A/D and D/A converters, RTCs, extra counters and timers, in-circuit debugging facilities, more interrupt sources, extra power saving modes, more/less parallel ports etc. Intel manufactured a mask programmed version, 8052AH-BASIC, with a BASIC interpreter in ROM, capable of running user programs loaded into RAM. MCS-51 based. Examples for high-temperature variants are the Tekmos TK8H51 family for −40 °C to +250 °C or the Honeywell HT83C51 for −55 °C to +225 °C. Radiation-hardenend MCS-51 microcontrollers for use in spacecraft are available.
The Intel i860 was a RISC microprocessor design introduced by Intel in 1989. It was one of Intel's first attempts at an new, high-end instruction set architecture since the failed Intel iAPX 432 from the 1980s, it was released with considerable fanfare obscuring the earlier Intel i960, successful in some niches of embedded systems, which many considered to be a better design. The i860 never achieved the project was terminated in the mid-1990s; the first implementation of the i860 architecture was the i860 XR microprocessor, which ran at 25, 33, or 40 MHz. The second-generation i860 XP microprocessor added 4 Mbyte pages, larger on-chip caches, second level cache support, faster buses, hardware support for bus snooping, for cache consistency in multiprocessor systems. A process shrink for the XP bumped it to 50 MHz. Both microprocessors supported the same instruction set for application programs; the i860 combined a number of features that were unique at the time, most notably its long instruction word architecture and powerful support for high-speed floating point operations.
The design mounted a 32-bit ALU "Core" along with a 64-bit FPU, itself built in three parts: an adder, a multiplier, a graphics processor. The system had separate pipelines for the ALU, floating point adder and multiplier, could hand off up to three operations per clock. All of the buses were at least 64 bits wide; the internal memory bus to the cache, for instance, was 128 bits wide. Both units had thirty-two 32-bit registers. Instructions for the ALU were fetched two at a time to use the full external bus. Intel referred to the design as the "i860 64-Bit Microprocessor". Intel i860 instructions acted on data sizes from 8-bit through 128-bit; the graphics unit was unique for the era. It was a 64-bit integer unit using the FPU registers as eight 128-bit registers, it supported a number of commands for SIMD-like instructions in addition to basic 64-bit integer math. Experience with the i860 influenced the MMX functionality added to Intel's Pentium processors. One unusual feature of the i860 was that the pipelines into the functional units were program-accessible, requiring the compilers to order instructions in the object code to keep the pipelines filled.
In traditional architectures these duties were handled at runtime by a scheduler on the CPU itself, but the complexity of these systems limited their application in early RISC designs. The i860 was an attempt to avoid this by moving this duty off-chip into the compiler; this allowed the i860 to devote more room to functional units. As a result of its architecture, the i860 could run certain graphics and floating point algorithms with exceptionally high speed, but its performance in general-purpose applications suffered and it was difficult to program efficiently. On paper, performance was impressive for a single-chip solution. One problem unrecognized at the time, was that runtime code paths are difficult to predict, meaning that it becomes exceedingly difficult to order instructions properly at compile time. For instance, an instruction to add two numbers will take longer if the data are not in the cache, yet there is no way for the programmer to know if they are or not. If an incorrect guess is made, the entire pipeline will stall.
The entire i860 design was based on the compiler efficiently handling this task, which proved impossible in practice. While theoretically capable of peaking at about 60-80 MFLOPS for both single precision and double precision for the XP versions, hand-coded assemblers managed to get only about up to 40 MFLOPS, most compilers had difficulty getting 10 MFLOPs; the Itanium architecture a VLIW design, suffered again from the problem of compilers incapable of delivering sufficiently optimized code. Another serious problem was the lack of any solution to handle context switching quickly; the i860 had several pipelines and an interrupt could spill them and require them all to be re-loaded. This took 62 cycles in the best case, 2000 cycles in the worst; the latter is 1/20000th of a second at 40 MHz, an eternity for a CPU. This eliminated the i860 as a general purpose CPU; as the compilers improved, the general performance of the i860 did but by most other RISC designs had passed the i860 in performance.
In the late 1990s, Intel replaced their entire RISC line with ARM-based designs, known as the XScale. Confusingly, the 860 number has since been re-used for a motherboard control chipset for Intel Xeon systems and a model of the Core i7. Andy Grove suggested that the i860's failure in the marketplace was due to Intel being stretched too thin: We now had two powerful chips that we were introducing at just about the same time: the 486 based on CISC technology and compatible with all the PC software, the i860, based on RISC technology, fast but compatible with nothing. We didn't know. So we introduced both, figuring we'd let the marketplace decide.... Our equivocation caused our customers to wonder what Intel stood for, the 486 or i860? At first, the i860 was only used in a small number of supercomputers such as the Intel iPSC/860. Intel marketed the i860 as a workstation microprocessor for a time, where it competed with microprocessor
The Intel 80386 known as i386 or just 386, is a 32-bit microprocessor introduced in 1985. The first versions had 275,000 transistors and were the CPU of many workstations and high-end personal computers of the time; as the original implementation of the 32-bit extension of the 80286 architecture, the 80386 instruction set, programming model, binary encodings are still the common denominator for all 32-bit x86 processors, termed the i386-architecture, x86, or IA-32, depending on context. The 32-bit 80386 can execute most code intended for the earlier 16-bit processors such as 8086 and 80286 that were ubiquitous in early PCs. Over the years, successively newer implementations of the same architecture have become several hundreds of times faster than the original 80386. A 33 MHz 80386 was measured to operate at about 11.4 MIPS. The 80386 was introduced in October 1985, while manufacturing of the chips in significant quantities commenced in June 1986. Mainboards for 80386-based computer systems were cumbersome and expensive at first, but manufacturing was rationalized upon the 80386's mainstream adoption.
The first personal computer to make use of the 80386 was designed and manufactured by Compaq and marked the first time a fundamental component in the IBM PC compatible de facto standard was updated by a company other than IBM. In May 2006, Intel announced that 80386 production would stop at the end of September 2007. Although it had long been obsolete as a personal computer CPU, Intel and others had continued making the chip for embedded systems; such systems using an 80386 or one of many derivatives are common in aerospace technology and electronic musical instruments, among others. Some mobile phones used the 80386 processor, such as BlackBerry 950 and Nokia 9000 Communicator; the processor was a significant evolution in the x86 architecture, extended a long line of processors that stretched back to the Intel 8008. The predecessor of the 80386 was the Intel 80286, a 16-bit processor with a segment-based memory management and protection system; the 80386 added a 32-bit architecture and a paging translation unit, which made it much easier to implement operating systems that used virtual memory.
It offered support for register debugging. The 80386 featured three operating modes: protected mode and virtual mode; the protected mode, which debuted in the 286, was extended to allow the 386 to address up to 4 GB of memory. The all new virtual 8086 mode made it possible to run one or more real mode programs in a protected environment, although some programs were not compatible; the ability for a 386 to be set up to act like it had a flat memory model in protected mode despite the fact that it uses a segmented memory model in all modes would arguably be the most important feature change for the x86 processor family until AMD released x86-64 in 2003. Several new instructions have been added to 386: BSF, BSR, BT, BTS, BTR, BTC, CDQ, CWDE, LFS, LGS, LSS, MOVSX, MOVZX, SETcc, SHLD, SHRD. Two new segment registers have been added for general-purpose programs, single Machine Status Word of 286 grew into eight control registers CR0–CR7. Debug registers DR0–DR7 were added for hardware breakpoints. New forms of MOV instruction are used to access them.
Chief architect in the development of the 80386 was John H. Crawford, he was responsible for extending the 80286 architecture and instruction set to 32-bit, led the microprogram development for the 80386 chip. The 80486 and P5 Pentium line of processors were descendants of the 80386 design; the following data types are directly supported and thus implemented by one or more 80386 machine instructions. 8-bit integer, either signed or unsigned. 16-bit integer, either signed or unsigned. 32-bit integer, either signed or unsigned. 64-bit integer, either signed or unsigned. Offset, a 16- or 32-bit displacement referring to a memory location. Pointer, a 16-bit selector together with a 16- or 32-bit offset. Character. String, a sequence of 8-, 16- or 32-bit words. BCD, decimal digits represented by unpacked bytes. Packed BCD, two BCD digits in one byte; the following 80386 assembly source code is for a subroutine named _strtolower that copies a null-terminated ASCIIZ character string from one location to another, converting all alphabetic characters to lower case.
The string is copied one byte at a time. The example code uses the EBP register to establish a call frame, an area on the stack that contains all of the parameters and local variables for the execution of the subroutine; this kind of calling convention supports reentrant and recursive code and has been used by Algol-like languages since the late 1950s. A flat memory model is assumed that the DS and ES segments address the same region of memory. In 1988, Intel introduced the 80386SX, most referred to as the 386SX, a cut-down version of the 80386 with a 16-bit data bus intended for lower-cost PCs aimed at the home and small-business markets, while the 386DX would remain the high-end variant used in workstations and other demanding tasks; the CPU remained 32-bit internally, but the 16-bit
The 8086 is a 16-bit microprocessor chip designed by Intel between early 1976 and June 8, 1978, when it was released. The Intel 8088, released July 1, 1979, is a modified chip with an external 8-bit data bus, is notable as the processor used in the original IBM PC design, including the widespread version called IBM PC XT; the 8086 gave rise to the x86 architecture, which became Intel's most successful line of processors. On June 5, 2018, Intel released a limited edition CPU celebrating the anniversary of the Intel 8086, called the Intel Core i7-8086K. In 1972, Intel launched the first 8-bit microprocessor, it implemented an instruction set designed by Datapoint corporation with programmable CRT terminals in mind, which proved to be general-purpose. The device needed several additional ICs to produce a functional computer, in part due to it being packaged in a small 18-pin "memory package", which ruled out the use of a separate address bus. Two years Intel launched the 8080, employing the new 40-pin DIL packages developed for calculator ICs to enable a separate address bus.
It has an extended instruction set, source-compatible with the 8008 and includes some 16-bit instructions to make programming easier. The 8080 device, was replaced by the depletion-load-based 8085, which sufficed with a single +5 V power supply instead of the three different operating voltages of earlier chips. Other well known 8-bit microprocessors that emerged during these years are Motorola 6800, General Instrument PIC16X, MOS Technology 6502, Zilog Z80, Motorola 6809; the 8086 project started in May 1976 and was intended as a temporary substitute for the ambitious and delayed iAPX 432 project. It was an attempt to draw attention from the less-delayed 16- and 32-bit processors of other manufacturers and at the same time to counter the threat from the Zilog Z80, which became successful. Both the architecture and the physical chip were therefore developed rather by a small group of people, using the same basic microarchitecture elements and physical implementation techniques as employed for the older 8085.
Marketed as source compatible, the 8086 was designed to allow assembly language for the 8008, 8080, or 8085 to be automatically converted into equivalent 8086 source code, with little or no hand-editing. The programming model and instruction set is based on the 8080. However, the 8086 design was expanded to support full 16-bit processing, instead of the limited 16-bit capabilities of the 8080 and 8085. New kinds of instructions were added as well. Instructions directly supporting nested ALGOL-family languages such as Pascal and PL/M were added. According to principal architect Stephen P. Morse, this was a result of a more software-centric approach than in the design of earlier Intel processors. Other enhancements included microcoded multiply and divide instructions and a bus structure better adapted to future coprocessors and multiprocessor systems; the first revision of the instruction set and high level architecture was ready after about three months, as no CAD tools were used, four engineers and 12 layout people were working on the chip.
The 8086 took a little more than two years from idea to working product, considered rather fast for a complex design in 1976–1978. The 8086 was sequenced using a mixture of random logic and microcode and was implemented using depletion-load nMOS circuitry with 20,000 active transistors, it was soon moved to a new refined nMOS manufacturing process called HMOS that Intel developed for manufacturing of fast static RAM products. This was followed by HMOS-II, HMOS-III versions, a static CMOS version for battery powered devices, manufactured using Intel's CHMOS processes; the original chip measured minimum feature size was 3.2 μm. The architecture was defined by Stephen P. Morse with some help and assistance by Bruce Ravenel in refining the final revisions. Logic designer Jim McKevitt and John Bayliss were the lead engineers of the hardware-level development team and Bill Pohlman the manager for the project; the legacy of the 8086 is enduring in the basic instruction set of today's personal computers and servers.
All internal registers, as well as internal and external data buses, are 16 bits wide, which established the "16-bit microprocessor" identity of the 8086. A 20-bit external address bus provides a 1 MB physical address space; this address space is addressed by means of internal memory "segmentation". The data bus is multiplexed with the address bus in order to fit all of the control lines into a standard 40-pin dual in-line package, it provides a 16-bit I/O address bus. The maximum line
The Intel 80486 known as the i486 or 486, is a higher performance follow-up to the Intel 80386 microprocessor. The 80486 was introduced in 1989 and was the first pipelined x86 design as well as the first x86 chip to use more than a million transistors, due to a large on-chip cache and an integrated floating-point unit, it represents a fourth generation of binary compatible CPUs since the original 8086 of 1978. A 50 MHz 80486 executes around 40 million instructions per second on average and is able to reach 50 MIPS peak performance; the 80486 was announced at Spring Comdex in April 1989. At the announcement, Intel stated that samples would be available in the third quarter of 1989 and production quantities would ship in the fourth quarter of 1989; the first 80486-based PCs were announced in late 1989, but some advised that people wait until 1990 to purchase an 80486 PC because there were early reports of bugs and software incompatibilities. The instruction set of the i486 is similar to its predecessor, the Intel 80386, with the addition of only a few extra instructions, such as CMPXCHG which implements a compare-and-swap atomic operation and XADD, a fetch-and-add atomic operation returning the original value.
From a performance point of view, the architecture of the i486 is a vast improvement over the 80386. It has an on-chip unified instruction and data cache, an on-chip floating-point unit and an enhanced bus interface unit. Due to the tight pipelining, sequences of simple instructions could sustain a single clock cycle throughput; these improvements yielded a rough doubling in integer ALU performance over the 386 at the same clock rate. A 16-MHz 80486 therefore had a performance similar to a 33-MHz 386, the older design had to reach 50 MHz to be comparable with a 25-MHz 80486 part. An 8 KB on-chip SRAM cache stores the most used instructions and data; the 386 supported a slower off-chip cache. An enhanced external bus protocol to enable cache coherency and a new burst mode for memory accesses to fill a cacheline of 16 bytes within 5 bus cycles; the 386 needed 8 bus cycles to transfer the same amount of data. Coupled pipelining completes a simple instruction like ALU reg,reg or ALU reg,im every clock cycle.
The 386 needed two clock cycles to do this. Integrated FPU with a dedicated local bus. Improved MMU performance. New instructions: XADD, BSWAP, CMPXCHG, INVD, WBINVD, INVLPG. Just as in the 80386, a simple flat 4 GB memory model could be implemented by setting all "segment selector" registers to a neutral value in protected mode, or setting "segment registers" to zero in real mode, using only the 32-bit "offset registers" as a linear 32-bit virtual address bypassing the segmentation logic. Virtual addresses were normally mapped onto physical addresses by the paging system except when it was disabled. Just as with the 80386, circumventing memory segmentation could improve performance in some operating systems and applications. On a typical PC motherboard, either four matched 30-pin SIMMs or one 72-pin SIMM per bank were required to fit the 80486's 32-bit data bus; the address bus used 30-bits complemented by four byte-select pins to allow for any 8/16/32-bit selection. This meant. There are several suffixes and variants..
Other variants include: Intel RapidCAD: a specially packaged Intel 486DX and a dummy floating-point unit designed as pin-compatible replacements for an Intel 80386 processor and 80387 FPU. i486SL-NM: i486SL based on i486SX. I487SX: i486DX with one extra pin sold as an FPU upgrade to i486SX systems. I486 OverDrive: i486SX, i486SX2, i486DX2 or i486DX4. Marked as upgrade processors, some models had different pinouts or voltage-handling abilities from "standard" chips of the same speed stepping. Fitted to a coprocessor or "OverDrive" socket on the motherboard, worked the same as the i487SX; the specified maximal internal clock frequency ranged from 16 to 100 MHz. The 16 MHz i486SX model was used by Dell Computers. One of the few 80486 models specified for a 50 MHz bus had overheating problems and was moved to the 0.8-micrometre fabrication process. However, problems continued when the 486DX-50 was installed in local-bus systems due to the high bus speed, making it rather unpopular with mainstream consumers, as local-bus video was considered a requirement at the time, though it remained popular with users of EISA systems.
The 486DX-50 was soon eclipsed by the clock-doubled i486DX2, which although running the internal CPU logic at twice the external bus speed, was slower due to the external bus running at only 25 MHz. The 486DX2 at 66 MHz was faster than the 486DX-50, overall. More powerful 80486 iterations such as the OverDrive and DX4 were less popular, as they came out after Intel had re