Circuit underutilization

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Circuit underutilization also programmable circuit underutilization, gate underutilization, logic block underutilization refers to a physical incomplete utility of semiconductor grade silicon on a standardized mass-produced circuit programmable chip, such as a gate array type ASIC, an FPGA, or CPLD.

Gate array[edit]

In the example of a gate array, which may come in sizes of 5,000 or 10,000 gates, a design which utilizes even 5,001 gates would be required to use a 10,000 gate chip. This inefficiency results in underutilization of the silicon.[1]

FPGA[edit]

Due to the design components of FPGA into logic blocks, simple designs that underutilize a single block suffer from gate underutilization, as do designs that overflow onto multiple blocks, such as designs that use wide gates.[2] Additionally, the very generic architecture of FPGAs lends to high inefficiency; multiplexers occupy silicon real estate for programmable selection, and an abundance of flip-flops to reduce setup and hold times, even if the design does not require them,[1] resulting in 40 times less density than of standard cell ASICs.

References[edit]

  1. ^ a b http://chipdesignmag.com/display.php?articleId=386
  2. ^ Zilic, Zeljko; Lemieux, Guy; Loveless, Kelvin; Brown, Stephen; Vranesic, Zvonko (June 1995). "Designing for High Speed-Performance in CPLDs and FPGAs". Proceeding of the Third Canadian Workshop on FPGAs. CiteSeerX 10.1.1.52.3689Freely accessible.