Athlon is the brand name applied to a series of x86-compatible microprocessors designed and manufactured by Advanced Micro Devices. The original Athlon was the first seventh-generation x86 processor and was the first desktop processor to reach speeds of one gigahertz, it made its debut on June 23, 1999. AMD has continued using the Athlon name with the 64-bit Athlon 64 architecture, the Athlon II, Accelerated Processing Unit chips targeting the Socket AM1 desktop SoC architecture, Socket AM4 Zen microarchitecture. Athlon comes from the Ancient Greek ἆθλον meaning " contest", or "prize of a contest", or "place of a contest. AMD founder Jerry Sanders aggressively pursued strategic partnerships and engineering talent in the late 1990s, desiring to leverage the success AMD had gained in the PC market with the preceding AMD K6 line of processors. One major partnership announced in 1998 paired AMD with semiconductor giant Motorola to co-develop copper-based semiconductor technology, resulted with the K7 project being the first commercial processor to utilize copper fabrication technology.
In the announcement, Sanders referred to the partnership as creating a "virtual gorilla" that would enable AMD to compete with Intel on fabrication capacity while limiting AMD's financial outlay for new facilities. The K7 design team was led by Dirk Meyer, who had worked as a lead engineer at DEC on multiple Alpha microprocessors during his employment at DEC; when DEC was sold to Compaq in 1998, the company discontinued Alpha processor development. Sanders approached many of the Alpha engineering staff as Compaq/DEC wound down their semiconductor business, was able to bring in nearly all of the Alpha design team; the K7 engineering design team was thus now consisted of both the acquired NexGen K6 team and the nearly complete Alpha design team. In August 1999, AMD released the Athlon processor. By working with Motorola, AMD was able to refine copper interconnect manufacturing to the production stage about one year before Intel; the revised process permitted 180-nanometer processor production. The accompanying die-shrink resulted in lower power consumption, permitting AMD to increase Athlon clock speeds to the 1 GHz range.
Yields on the new process exceeded expectations, permitting AMD to deliver high speed chips in volume in March 2000. The Athlon architecture used the EV6 bus licensed from DEC as its main system bus. Intel required licensing to use the GTL+ bus used by its Slot 1 Pentium II and processors. By licensing the EV6 bus used by the Alpha line of processors from DEC, AMD was able to develop its own chipsets and motherboards, avoid being dependent on licensing from its direct competitor. Internally, the Athlon is a seventh generation x86 processor, the first of its kind. Like the AMD K5 and K6, the Athlon dynamically buffers internal micro-instructions at runtime resulting from parallel x86 instruction decoding; the CPU is an out-of-order design, again like previous post-5x86 AMD CPUs. The Athlon utilizes the Alpha 21264's EV6 bus architecture with double data rate technology; this means that at 100 MHz, the Athlon front side bus transfers at a rate similar to a 200 MHz single data rate bus, superior to the method used on Intel's Pentium III.
AMD designed the CPU with more robust x86 instruction decoding capabilities than that of K6, to enhance its ability to keep more data in-flight at once. The Athlon's three decoders could decode three x86 instructions to six microinstructions per clock, although this was somewhat unlikely in real-world use; the critical branch predictor unit, essential to keeping the pipeline busy, was enhanced compared to what was on board the K6. Deeper pipelining with more stages allowed higher clock speeds to be attained. Whereas the AMD K6-III+ topped out at 570 MHz due to its short pipeline when built on the 180 nm process, the Athlon was capable of clocking much higher. AMD ended its long-time handicap with floating point x87 performance by designing a super-pipelined, out-of-order, triple-issue floating point unit; each of its three units was tailored to be able to calculate an optimal type of instructions with some redundancy. By having separate units, it was possible to operate on more than one floating point instruction at once.
This FPU was a huge step forward for AMD. While the K6 FPU had looked anemic compared to the Intel P6 FPU, with Athlon this was no longer the case; the 3DNow! Floating point SIMD technology, again present, received some revisions and a name change to "Enhanced 3DNow!". Additions included DSP instructions and an implementation of the extended MMX subset of Intel SSE; the Athlon's CPU cache consisted of the typical two levels. Athlon was the first x86 processor with a 128 kB split level 1 cache; this cache was double the size of K6's large 2×32 kB cache, quadruple the size of Pentium II and III's 2×16 kB L1 cache. The initial Athlon used 512 kB of level 2 cache separate from the CPU, on the processor cartridge board, running at 50% to 33% of core speed; this was done because the 250 nm manufacturing process was too large to allow for on-die cache while maintaining cost-effective die size. Athlon CPUs, afforded greater transistor budgets by smaller 180 nm and 130 nm process nodes, moved to on-die L2 cache at full CPU clock speed.
The AMD Athlon processor launched on June 23, 1999, with general availability by August'99. It launched at 500 MHz and was, on average, 10% faster than the Pent
Marin Mersenne, Marin Mersennus or le Père Mersenne was a French polymath, whose works touched a wide variety of fields. He is best known today among mathematicians for Mersenne prime numbers, those which can be written in the form Mn = 2n − 1 for some integer n, he developed Mersenne's laws, which describe the harmonics of a vibrating string, his seminal work on music theory, Harmonie universelle, for which he is referred to as the "father of acoustics". Mersenne, an ordained priest, had many contacts in the scientific world and has been called "the center of the world of science and mathematics during the first half of the 1600s" and, because of his ability to make connections between people and ideas, "the post-box of Europe", he was a member of the Minim religious order and wrote and lectured on theology and philosophy. Mersenne was born of peasant parents near Maine, he was educated at the Jesuit College of La Flèche. On 17 July 1611, he joined the Minim Friars and, after studying theology and Hebrew in Paris, was ordained a priest in 1613.
Between 1614 and 1618, he taught theology and philosophy at Nevers, but he returned to Paris and settled at the convent of L'Annonciade in 1620. There he studied mathematics and music and met with other kindred spirits such as René Descartes, Étienne Pascal, Pierre Petit, Gilles de Roberval, Thomas Hobbes, Nicolas-Claude Fabri de Peiresc, he corresponded with Giovanni Doni, Jacques Alexandre Le Tenneur, Constantijn Huygens, Galileo Galilei, other scholars in Italy and the Dutch Republic. He was a staunch defender of Galileo, assisting him in translations of some of his mechanical works. For four years, Mersenne devoted himself to philosophic and theological writing, published Quaestiones celeberrimae in Genesim, it is sometimes incorrectly stated. He was educated by Jesuits, he taught philosophy at Nevers and Paris. In 1635 he set up the informal Académie Parisienne, which had nearly 140 correspondents, including astronomers and philosophers as well as mathematicians, was the precursor of the Académie des sciences established by Jean-Baptiste Colbert in 1666.
He was not afraid to cause disputes among his learned friends in order to compare their views, notable among which were disputes between Descartes and Pierre de Fermat and Jean de Beaugrand. Peter L. Bernstein, in his book Against the Gods: The Remarkable Story of Risk, wrote, "The Académie des Sciences in Paris and the Royal Society in London, which were founded about twenty years after Mersenne's death, were direct descendants of Mersenne's activities."In 1635 Mersenne met with Tommaso Campanella but concluded that he could "teach nothing in the sciences... but still he has a good memory and a fertile imagination." Mersenne asked if Descartes wanted Campanella to come to Holland to meet him, but Descartes declined. He visited Italy fifteen times, in 1640, 1641 and 1645. In 1643–1644 Mersenne corresponded with the German Socinian Marcin Ruar concerning the Copernican ideas of Pierre Gassendi, finding Ruar a supporter of Gassendi's position. Among his correspondents were Descartes, Roberval, Pascal and other scientists.
He died September 1 through complications arising from a lung abscess. Quaestiones celeberrimae in Genesim was written as a commentary on the Book of Genesis and comprises uneven sections headed by verses from the first three chapters of that book. At first sight the book appears to be a collection of treatises on various miscellaneous topics; however Robert Lenoble has shown that the principle of unity in the work is a polemic against magical and divinatory arts and animistic and pantheistic philosophies. He mentions Martin Del Rio's Investigations into Magic and criticises Marsilio Ficino for claiming power for images and characters, he condemns astral magic and astrology and the anima mundi, a concept popular amongst Renaissance neo-platonists. Whilst allowing for a mystical interpretation of the Cabala, he wholeheartedly condemned its magical application angelology, he criticises Pico della Mirandola, Cornelius Agrippa, Francesco Giorgio and Robert Fludd, his main target. Fludd responded with Sophia cum moria certamen, wherein he admits his involvement with the Rosicrucians.
The anonymous Summum bonum, another critique of Mersenne, is an Rosicrucian text. The cabalist Jacques Gaffarel joined Fludd's side. L'Harmonie universelle is Mersenne's most influential work, it is one of the earliest comprehensive works on music theory, touching on a wide range of musical concepts, the mathematical relationships involved in music. The work contains the earliest formulation of what has become known as Mersenne's laws, which describe the frequency of oscillation of a stretched string; this frequency is: Inversely proportional to the length of the string Proportional to the square root of the stretching force, Inversely proportional to the square root of the mass per unit length. The formula for the lowest frequency is f = 1 2 L F μ, where f is the frequency, L is the length, F is the force and μ is the mass per unit length
Pentium 4 is a brand by Intel for an entire series of single-core CPUs for desktops and entry-level servers. The processors were shipped from November 20, 2000, until August 8, 2008. All Pentium 4 CPUs are based on the NetBurst architecture; the Pentium 4 Willamette introduced SSE2, while the Prescott introduced SSE3. Versions introduced Hyper-Threading Technology; the first Pentium 4-branded processor to implement 64-bit was the Prescott, but this feature was not enabled. Intel subsequently began selling 64-bit Pentium 4s using the "E0" revision of the Prescotts, being sold on the OEM market as the Pentium 4, model F; the E0 revision adds eXecute Disable to Intel 64. Intel's official launch of Intel 64 in mainstream desktop processors was the N0 stepping Prescott-2M. Intel marketed a version of their low-end Celeron processors based on the NetBurst microarchitecture, a high-end derivative, intended for multi-socket servers and workstations. In 2005, the Pentium 4 was complemented by the dual-core-brands Pentium D and Pentium Extreme Edition.
In benchmark evaluations, the advantages of the NetBurst microarchitecture were unclear. With optimized application code, the first Pentium 4s outperformed Intel's fastest Pentium III, as expected, but in legacy applications with many branching or x87 floating-point instructions, the Pentium 4 would match or run slower than its predecessor. Its main downfall was a shared unidirectional bus; the NetBurst microarchitecture consumed more power and emitted more heat than any previous Intel or AMD microarchitectures. As a result, the Pentium 4's introduction was met with mixed reviews: Developers disliked the Pentium 4, as it posed a new set of code optimization rules. For example, in mathematical applications, AMD's lower-clocked Athlon outperformed the Pentium 4, which would only catch up if software was re-compiled with SSE2 support. Tom Yager of Infoworld magazine called it "the fastest CPU - for programs that fit in cache". Computer-savvy buyers avoided Pentium 4 PCs due to their price premium, questionable benefit, initial restriction to Rambus RAM.
In terms of product marketing, the Pentium 4's singular emphasis on clock frequency made it a marketer's dream. The result of this was that the NetBurst micro architecture was referred to as a marchitecture by various computing websites and publications during the life of the Pentium 4, it was called "NetBust," a term popular with reviewers who reflected negatively upon the processor's performance. The two classical metrics of CPU performance are clock speed. While IPC is difficult to quantify due to dependence on the benchmark application's instruction mix, clock speed is a simple measurement yielding a single absolute number. Unsophisticated buyers would consider the processor with the highest clock speed to be the best product, the Pentium 4 had the fastest clock speed; because AMD's processors had slower clock speeds, it countered Intel's marketing advantage with the "megahertz myth" campaign. AMD product marketing used a "PR-rating" system, which assigned a merit value based on relative performance to a baseline machine.
At the launch of the Pentium 4, Intel stated that NetBurst-based processors were expected to scale to 10 GHz after several fabrication process generations. However, the clock speed of processors using the NetBurst micro architecture reached a maximum of 3.8 GHz. Intel had not anticipated a rapid upward scaling of transistor power leakage that began to occur as the die reached the 90 nm lithography and smaller; this new power leakage phenomenon, along with the standard thermal output, created cooling and clock scaling problems as clock speeds increased. Reacting to these unexpected obstacles, Intel attempted several core redesigns and explored new manufacturing technologies, such as using multiple cores, increasing FSB speeds, increasing the cache size, using a longer instruction pipeline along with higher clock speeds; these solutions failed, from 2003 to 2005, Intel shifted development away from NetBurst to focus on the cooler-running Pentium M microarchitecture. On January 5, 2006, Intel launched the Core processors, which put greater emphasis on energy efficiency and performance per clock cycle.
The final NetBurst-derived products were released in 2007, with all subsequent product families switching to the Core microarchitecture. Pentium 4 processors have an integrated heat spreader that prevents the die from accidentally being damaged when mounting and unmounting cooling solutions. Prior to the IHS, a CPU shim was sometimes used by people worried about damaging the core. Overclockers sometimes removed the IHS from Socket 423 and Socket 478 chips to allow for more direct heat transfer. On processors using the Socket LGA 775 interface, the IHS is directly soldered to the die or dies, making it difficult to remove. Willamette, the project codename for the first NetBurst microarchitecture implementation, experienced long delays in the completion of its design process; the project was started in 1998. At that time, the Willamette core was expected to operate at frequencies up to about 1 GHz. However, the Pentium III was released. Due to the radical differences between the P6 and NetBurst microarchitectures, Intel could not market Willamette as a Pentium III, so it was marketed as the Pentium 4.
On November 20, 2000, Intel released the Willame
Pentium is a brand used for a series of x86 architecture-compatible microprocessors produced by Intel since 1993. In their form as of November 2011, Pentium processors are considered entry-level products that Intel rates as "two stars", meaning that they are above the low-end Atom and Celeron series, but below the faster Core i3, i5, i7, i9, workstation Xeon series; as of 2017, Pentium processors have little more than their name in common with earlier Pentiums, which were Intel's flagship processor for over a decade until the introduction of the Intel Core line in 2006. They are based on both the architecture used in that of Core processors. In the case of Atom architectures, Pentiums are the highest performance implementations of the architecture. Pentium processors with Core architectures prior to 2017 were distinguished from the faster, higher-end i-series processors by lower clock rates and disabling some features, such as hyper-threading and sometimes L3 cache; the name Pentium is derived from the Greek word penta, meaning "five", a reference to the prior numeric naming convention of Intel's 80x86 processors, with the Latin ending -ium.
In 2017, Intel split Pentium into two line-ups. Pentium Silver aiming for low-power devices and shares architecture with Atom and Celeron. Pentium Gold aiming for entry-level desktop and using existing architecture, such as Kaby Lake or Coffee Lake. During development, Intel identifies processors with codenames, such as Prescott, Coppermine, Klamath, or Deschutes; these become known after the processors are given official names on launch. The original Pentium-branded CPUs were expected to be named 586 or i586, to follow the naming convention of prior generations. However, as the firm wanted to prevent their competitors from branding their processors with similar names, Intel filed a trademark application on the name in the United States, but was denied because a series of numbers was considered to lack trademark distinctiveness. Following Intel's prior series of 8086, 80186, 80286, 80386, 80486 microprocessors, the firm's first P5-based microprocessor was released as the original Intel Pentium on March 22, 1993.
Marketing firm Lexicon Branding was hired to coin a name for the new processor. The suffix -ium was chosen as it could connote a fundamental ingredient of a computer, like a chemical element, while the prefix pent- could refer to the fifth generation of x86. Due to its success, the Pentium brand would continue through several generations of high-end processors. In 2006, the name disappeared from Intel's technology roadmaps, only to re-emerge in 2007. In 1998, Intel introduced the Celeron brand for low-priced microprocessors. With the 2006 introduction of the Intel Core brand as the company's new flagship line of processors, the Pentium series was to be discontinued. However, due to a demand for mid-range dual-core processors, the Pentium brand was repurposed to be Intel's mid-range processor series, between the Celeron and Core series, continuing with the Pentium Dual-Core line. In 2009, the "Dual-Core" suffix was dropped, new x86 microprocessors started carrying the plain Pentium name again.
In 2014, Intel released the Pentium 20th Anniversary Edition, to mark the 20th anniversary of the Pentium brand. The processors are unlocked and overclockable. In 2017, Intel splits Pentium into two line-ups, Pentium Silver aiming for low-power devices and shares architecture with Atom and Celeron and Pentium Gold aiming for entry-level desktop and using existing architecture, such as Kaby Lake or Coffee Lake The original Intel P5 or Pentium and Pentium MMX processors were the superscalar follow-on to the 80486 processor and were marketed from 1993 to 1999; some versions of these were available as Pentium OverDrive. In parallel with the P5 microarchitecture, Intel developed the P6 microarchitecture and started marketing it as the Pentium Pro for the high-end market in 1995, it introduced out-of-order execution and an integrated second-level cache on dual-chip processor package. The second P6 generation replaced the original P5 with the Pentium II and rebranded the high-end version as Pentium II Xeon.
It was followed by a third version named the Pentium Pentium III Xeon respectively. The Pentium II line added the MMX instructions that were present in the Pentium MMX. Versions of these processors for the laptop market were named Mobile Pentium II and Mobile Pentium III versions were named Pentium III-M. Starting with the Pentium II, the Celeron brand was used for low-end versions of most Pentium processors with a reduced feature set such as a smaller cache or missing power management features. In 2000, Intel introduced a new microarchitecture named NetBurst, with a much longer pipeline enabling higher clock frequencies than the P6-based processors; these were named Pentium 4, the high-end versions have since been named Xeon. As with Pentium III, there are both Mobile Pentium 4 and Pentium 4 M processors for the laptop market, with Pentium 4 M denoting the more power-efficient versions. Enthusiast versions of the Pentium 4 with the highest clock rates were named Pentium 4 Extreme Edition; the Pentium D was the first multi-core Pentium, integrating two Pentium 4 chips in one package and was available as the enthusiast Pentium Extreme Edition.
In 2003, Intel introduced a new processor based on the P6 microarchitecture named Pentium M, much more power-efficient than the Mobile Pentium 4, Pentium 4 M, Pentium III M. Dual-core versions of the Pentium M were developed under the code name Yonah and sold under the marketing names Core Duo and Pentium Dual-Core. Unlike Pentium D, it
Units of paper quantity
Various measures of paper quantity have been and are in use. Although there are no S. I. units such as quires and bales, there are DIN standards for the ream. Expressions used here include U. S. Customary units. Writing paper measurements 25 sheets = 1 quire 500 sheets = 20 quires = 1 ream 1,000 sheets = 40 quires = 2 reams = 1 bundle5,000 sheets = 200 quires = 10 reams = 5 bundles = 1 bale'Short' paper measurements 24 sheets = 1'short' quire 480 sheets = 20'short' quires = 1'short' ream 960 sheets = 40'short' quires = 2'short' reams = 1'short' bundle 4,800 sheets = 200'short' quires = 10'short' reams = 5'short' bundles = 1'short' balePosters and printing measurements 516 sheets = 1 printer's ream 1,032 sheets = 2 printer's reams = 1 printer's bundle 5,160 sheets = 5 printer's bundles = 1 printer's baleCover and Index paper 250 sheets = 1 ream A quire of paper is a measure of paper quantity; the usual meaning is 25 sheets of the quality: 1⁄20 of a ream of 500 sheets. Quires of 25 sheets are used for machine-made paper, while quires of 24 sheets are used for handmade or specialised paper of 480-sheet reams.
Quires of 15, 18 or 20 sheets have been used, depending on the type of paper. The current word "quire" derives from OE "quair" or "guaer", from OF "quayer", "cayer", from L. quaternum, "by fours", "fourfold". When bookmaking switched to using paper and it became possible to stitch 5 to 7 sheets at a time, the association of "quaire" with "four" was lost. In the Middle Ages, a quire was most formed of 4 folded sheets of vellum or parchment, i.e. 8 leaves, 16 sides. The term "quaternion" designates such a quire. A quire made of a single folded sheet is a "bifolium"; this last meaning is preserved in the modern Italian term for quinterno di carta. When paper was packed at the paper mill, the top and bottom quires were made up of damaged sheets to protect the good quires; these outside quires were known as "cassie quires", or "cording quires" and had only 20 sheets to the quire. The printer William Caslon in a book published in 1770 mentions both 24- and 25-sheet quires. An 1826 French manual on typography complained that cording quires from the Netherlands contained a single good sheet.
It became the name for any booklet small enough to be made from a single quire of paper. Simon Winchester, in The Surgeon of Crowthorne, cites a specific number, defining quire as "a booklet eight pages thick." Several European words for quire keep the meaning of "book of paper": Ger. Buch von Papier, Dan. Bog papir, Du. bock papier. In blankbook binding, quire is a term indicating 80 pages. A ream of paper is a quantity of sheets of the quality. International standards organizations define the ream as 500 identical sheets; this ream of 500 sheets is known as a'long' ream, is replacing the old value of 480 sheets, now known as a'short' ream. Reams of 472 and 516 sheets are still current, but in retail outlets paper is sold in reams of 500; as an old UK and US unit, a perfect ream was equal to 516 sheets. Certain types of specialist papers such as tissue paper, greaseproof paper, handmade paper, blotting paper are still sold in'short' reams of 480 sheets. However, the commercial use of the word'ream' for quantities of paper other than 500 is now deprecated by such standards as ISO 4046.
In Europe, the DIN 6730 standard for Paper and Board includes a definition of 1 ream of A4 80gsm paper equals 500 sheets. The word'ream' derives from Old French reyme, from Spanish resma, from Arabic rizmah "bundle", from rasama, "collect into a bundle". Early variant rym suggests a Dutch influence. During the time of Spanish Habsburg control of the Netherlands; the number of sheets in a ream has varied locally over the centuries according to the size and type of paper being sold. Reams of 500 sheets were known in England in c1594. In 18th- and 19th-century Europe, the size of the ream varied widely. In Lombardy a ream of music paper was 480 sheets; some paper manufacturers counted 546 sheets. J. S. Bach's manuscript paper at Weimar was ordered by the ream of 480 sheets. In 1840, a ream in Lisbon was 17 quires and 3 sheets = 428 sheets, a double ream was 18 quires and 2 sheets = 434 sheets. A mid-19th century Milanese-Italian dictionary has an example for a risma as being either 450 or 480 sheets. In the UK in 1914, paper was sold using the following reams: 472 sheets – Mill ream 480 sheets – – now called'short' ream 500 sheets – – now called'long' ream 504 sheets – Statio
The Intel 80386 known as i386 or just 386, is a 32-bit microprocessor introduced in 1985. The first versions had 275,000 transistors and were the CPU of many workstations and high-end personal computers of the time; as the original implementation of the 32-bit extension of the 80286 architecture, the 80386 instruction set, programming model, binary encodings are still the common denominator for all 32-bit x86 processors, termed the i386-architecture, x86, or IA-32, depending on context. The 32-bit 80386 can execute most code intended for the earlier 16-bit processors such as 8086 and 80286 that were ubiquitous in early PCs. Over the years, successively newer implementations of the same architecture have become several hundreds of times faster than the original 80386. A 33 MHz 80386 was measured to operate at about 11.4 MIPS. The 80386 was introduced in October 1985, while manufacturing of the chips in significant quantities commenced in June 1986. Mainboards for 80386-based computer systems were cumbersome and expensive at first, but manufacturing was rationalized upon the 80386's mainstream adoption.
The first personal computer to make use of the 80386 was designed and manufactured by Compaq and marked the first time a fundamental component in the IBM PC compatible de facto standard was updated by a company other than IBM. In May 2006, Intel announced that 80386 production would stop at the end of September 2007. Although it had long been obsolete as a personal computer CPU, Intel and others had continued making the chip for embedded systems; such systems using an 80386 or one of many derivatives are common in aerospace technology and electronic musical instruments, among others. Some mobile phones used the 80386 processor, such as BlackBerry 950 and Nokia 9000 Communicator; the processor was a significant evolution in the x86 architecture, extended a long line of processors that stretched back to the Intel 8008. The predecessor of the 80386 was the Intel 80286, a 16-bit processor with a segment-based memory management and protection system; the 80386 added a 32-bit architecture and a paging translation unit, which made it much easier to implement operating systems that used virtual memory.
It offered support for register debugging. The 80386 featured three operating modes: protected mode and virtual mode; the protected mode, which debuted in the 286, was extended to allow the 386 to address up to 4 GB of memory. The all new virtual 8086 mode made it possible to run one or more real mode programs in a protected environment, although some programs were not compatible; the ability for a 386 to be set up to act like it had a flat memory model in protected mode despite the fact that it uses a segmented memory model in all modes would arguably be the most important feature change for the x86 processor family until AMD released x86-64 in 2003. Several new instructions have been added to 386: BSF, BSR, BT, BTS, BTR, BTC, CDQ, CWDE, LFS, LGS, LSS, MOVSX, MOVZX, SETcc, SHLD, SHRD. Two new segment registers have been added for general-purpose programs, single Machine Status Word of 286 grew into eight control registers CR0–CR7. Debug registers DR0–DR7 were added for hardware breakpoints. New forms of MOV instruction are used to access them.
Chief architect in the development of the 80386 was John H. Crawford, he was responsible for extending the 80286 architecture and instruction set to 32-bit, led the microprogram development for the 80386 chip. The 80486 and P5 Pentium line of processors were descendants of the 80386 design; the following data types are directly supported and thus implemented by one or more 80386 machine instructions. 8-bit integer, either signed or unsigned. 16-bit integer, either signed or unsigned. 32-bit integer, either signed or unsigned. 64-bit integer, either signed or unsigned. Offset, a 16- or 32-bit displacement referring to a memory location. Pointer, a 16-bit selector together with a 16- or 32-bit offset. Character. String, a sequence of 8-, 16- or 32-bit words. BCD, decimal digits represented by unpacked bytes. Packed BCD, two BCD digits in one byte; the following 80386 assembly source code is for a subroutine named _strtolower that copies a null-terminated ASCIIZ character string from one location to another, converting all alphabetic characters to lower case.
The string is copied one byte at a time. The example code uses the EBP register to establish a call frame, an area on the stack that contains all of the parameters and local variables for the execution of the subroutine; this kind of calling convention supports reentrant and recursive code and has been used by Algol-like languages since the late 1950s. A flat memory model is assumed that the DS and ES segments address the same region of memory. In 1988, Intel introduced the 80386SX, most referred to as the 386SX, a cut-down version of the 80386 with a 16-bit data bus intended for lower-cost PCs aimed at the home and small-business markets, while the 386DX would remain the high-end variant used in workstations and other demanding tasks; the CPU remained 32-bit internally, but the 16-bit
Electronic Frontier Foundation
The Electronic Frontier Foundation is an international non-profit digital rights group based in San Francisco, California. The foundation was formed in July 1990 by John Gilmore, John Perry Barlow and Mitch Kapor to promote Internet civil liberties. EFF provides funds for legal defense in court, presents amicus curiae briefs, defends individuals and new technologies from what it considers abusive legal threats, works to expose government malfeasance, provides guidance to the government and courts, organizes political action and mass mailings, supports some new technologies which it believes preserve personal freedoms and online civil liberties, maintains a database and web sites of related news and information and challenges potential legislation that it believes would infringe on personal liberties and fair use and solicits a list of what it considers abusive patents with intentions to defeat those that it considers without merit. EFF provides tips, how-tos and software for safer online communications.
The Electronic Frontier Foundation was formed in July 1990 by John Gilmore, John Perry Barlow and Mitch Kapor in response to a series of actions by law enforcement agencies that led them to conclude that the authorities were gravely uninformed about emerging forms of online communication, that there was a need for increased protection for Internet civil liberties. In April 1990, Barlow had been visited by a U. S. Federal Bureau of Investigation agent in relation to the theft and distribution of the source code for a series of Macintosh ROMs. Barlow described the visit as "complicated by complete unfamiliarity with computer technology. I realized right away that before I could demonstrate my innocence, I would first have to explain to him what guilt might be." Barlow felt that his experience was symptomatic of a "great paroxysm of governmental confusion during which everyone's liberties would become at risk". Barlow posted an account of this experience to The WELL online community and was contacted by Mitch Kapor, who had had a similar experience.
The pair agreed. Kapor agreed to fund any legal fees associated with such a defense and the pair contacted New York lawyers Rabinowitz, Standard and Lieberman about defending several computer hackers from a Harper's magazine forum on computers and freedom, the target of Secret Service raids; this generated a large amount of publicity which led to offers of financial support from John Gilmore and Steve Wozniak. Barlow and Kapor continued to research conflicts between the government and technology and in June 1990, Barlow posted online the influential article entitled "Crime & Puzzlement" in which Barlow announced his and Kapor's plans to create an organization to "raise and disburse funds for education and litigation in the areas relating to digital speech and the extension of the Constitution into Cyberspace."This generated further reaction and support for the ideas of Barlow and Kapor. In late June, Barlow held a series of dinners in San Francisco with major figures in the computer industry to develop a coherent response to these perceived threats.
Barlow considered that: "The actions of the FBI and Secret Service were symptoms of a growing social crisis: Future Shock. America was entering the Information Age with neither laws nor metaphors for the appropriate protection and conveyance of information itself." Barlow felt. The Electronic Frontier Foundation was formally founded on July 10, 1990, by Kapor and Barlow, who soon after elected Gilmore and Stewart Brand to join them on the Board of Directors. Initial funding was provided by Kapor, an anonymous benefactor. In 1990, Mike Godwin joined the organization as its first staff counsel. In 1991, Esther Dyson and Jerry Berman joined the EFF board of directors. By 1992, Cliff Figallo became the director of the original office, in December 1992, Jerry Berman became the acting executive director of the organization as a whole, based in a new second office; the creation of the organization was motivated by the massive search and seizure on Steve Jackson Games executed by the United States Secret Service early in 1990.
Similar but unconnected law-enforcement raids were being conducted across the United States at about that time as part of a state–federal task force called Operation Sundevil. GURPS Cyberpunk, one of the game company's projects, was mistakenly labeled as a handbook for computer crime, the Secret Service raided the offices of Steve Jackson Games; the search warrant for the raid was deemed hastily issued, the games company soon after claimed unauthorized access as well as tampering of their emails. While phone calls were protected by legislation, digital emails were an early concept and had not been considered to fall under the right to personal privacy; the Steve Jackson Games case was EFF's first high-profile case, was the major rallying point around which EFF began promoting computer- and Internet-related civil liberties. EFF's second big case was Bernstein v. United States led by Cindy Cohn, in which programmer and professor Daniel J. Bernstein sued the government for permission to publish his encryption software, a paper describing it.
More the organization has been involved in defending Edward Felten, Jon Lech Johansen and Dmitry Sklyarov. The organization was located at Mitch Kapor's Kapor Enterprises offices. By the fall of 1993, the main EFF offices were consolidated into a single office, headed by Executive Director Jerry Berman. During this time, som