Microsoft Windows is a group of several graphical operating system families, all of which are developed and sold by Microsoft. Each family caters to a certain sector of the computing industry. Active Windows families include Windows Embedded. Defunct Windows families include Windows Mobile and Windows Phone. Microsoft introduced an operating environment named Windows on November 20, 1985, as a graphical operating system shell for MS-DOS in response to the growing interest in graphical user interfaces. Microsoft Windows came to dominate the world's personal computer market with over 90% market share, overtaking Mac OS, introduced in 1984. Apple came to see Windows as an unfair encroachment on their innovation in GUI development as implemented on products such as the Lisa and Macintosh. On PCs, Windows is still the most popular operating system. However, in 2014, Microsoft admitted losing the majority of the overall operating system market to Android, because of the massive growth in sales of Android smartphones.
In 2014, the number of Windows devices sold was less than 25 %. This comparison however may not be relevant, as the two operating systems traditionally target different platforms. Still, numbers for server use of Windows show one third market share, similar to that for end user use; as of October 2018, the most recent version of Windows for PCs, tablets and embedded devices is Windows 10. The most recent versions for server computers is Windows Server 2019. A specialized version of Windows runs on the Xbox One video game console. Microsoft, the developer of Windows, has registered several trademarks, each of which denote a family of Windows operating systems that target a specific sector of the computing industry; as of 2014, the following Windows families are being developed: Windows NT: Started as a family of operating systems with Windows NT 3.1, an operating system for server computers and workstations. It now consists of three operating system subfamilies that are released at the same time and share the same kernel: Windows: The operating system for mainstream personal computers and smartphones.
The latest version is Windows 10. The main competitor of this family is macOS by Apple for personal computers and Android for mobile devices. Windows Server: The operating system for server computers; the latest version is Windows Server 2019. Unlike its client sibling, it has adopted a strong naming scheme; the main competitor of this family is Linux. Windows PE: A lightweight version of its Windows sibling, meant to operate as a live operating system, used for installing Windows on bare-metal computers, recovery or troubleshooting purposes; the latest version is Windows PE 10. Windows IoT: Initially, Microsoft developed Windows CE as a general-purpose operating system for every device, too resource-limited to be called a full-fledged computer. However, Windows CE was renamed Windows Embedded Compact and was folded under Windows Compact trademark which consists of Windows Embedded Industry, Windows Embedded Professional, Windows Embedded Standard, Windows Embedded Handheld and Windows Embedded Automotive.
The following Windows families are no longer being developed: Windows 9x: An operating system that targeted consumers market. Discontinued because of suboptimal performance. Microsoft now caters to the consumer market with Windows NT. Windows Mobile: The predecessor to Windows Phone, it was a mobile phone operating system; the first version was called Pocket PC 2000. The last version is Windows Mobile 6.5. Windows Phone: An operating system sold only to manufacturers of smartphones; the first version was Windows Phone 7, followed by Windows Phone 8, the last version Windows Phone 8.1. It was succeeded by Windows 10 Mobile; the term Windows collectively describes any or all of several generations of Microsoft operating system products. These products are categorized as follows: The history of Windows dates back to 1981, when Microsoft started work on a program called "Interface Manager", it was announced in November 1983 under the name "Windows", but Windows 1.0 was not released until November 1985.
Windows 1.0 was to achieved little popularity. Windows 1.0 is not a complete operating system. The shell of Windows 1.0 is a program known as the MS-DOS Executive. Components included Calculator, Cardfile, Clipboard viewer, Control Panel, Paint, Reversi and Write. Windows 1.0 does not allow overlapping windows. Instead all windows are tiled. Only modal dialog boxes may appear over other windows. Microsoft sold as included Windows Development libraries with the C development environment, which included numerous windows samples. Windows 2.0 was released in December 1987, was more popular than its predecessor. It features several improvements to the user memory management. Windows 2.03 changed the OS from tiled windows to overlapping windows. The result of this change led to Apple Computer filing a suit against Microsoft alleging infringement on Apple's copyrights. Windows 2.0
MMX (instruction set)
MMX is a single instruction, multiple data instruction set designed by Intel, introduced in 1997 with its P5-based Pentium line of microprocessors, designated as "Pentium with MMX Technology". It developed out of a similar unit introduced on the Intel i860, earlier the Intel i750 video pixel processor. MMX is a processor supplementary capability, supported on recent IA-32 processors by Intel and other vendors; the New York Times described the initial push, including Super Bowl ads, as focused on "a new generation of glitzy multimedia products, including videophones and 3-D video games."MMX has subsequently been extended by several programs by Intel and others: 3DNow!, Streaming SIMD Extensions, ongoing revisions of Advanced Vector Extensions. MMX is a meaningless initialism trademarked by Intel. Newsweek described it as "57 new'instructions' etched microscopically onto the face of the chip."AMD, during one of its numerous court battles with Intel, produced marketing material from Intel indicating that MMX stood for "Matrix Math Extensions".
Since an initialism cannot be trademarked, this was an attempt to invalidate Intel's trademark. In 1995, Intel filed suit against AMD and Cyrix Corp. for misuse of its trademark MMX. AMD and Intel settled, with AMD acknowledging MMX as a trademark owned by Intel, with Intel granting AMD rights to use the MMX trademark as a technology name, but not a processor name. MMX defines eight registers, called MM0 through MM7, operations that operate on them; each register is 64 bits wide and can be used to hold either 64-bit integers, or multiple smaller integers in a "packed" format: a single instruction can be applied to two 32-bit integers, four 16-bit integers, or eight 8-bit integers at once. MMX provides only integer operations; when developed, for the Intel i860, the use of integer math made sense, but as graphics cards that did much of this became common, integer SIMD in the CPU became somewhat redundant for graphical applications. On the other hand, the saturation arithmetic operations in MMX could speed up some digital signal processing applications.
To avoid compatibility problems with the context switch mechanisms in existing operating systems, the MMX registers are aliases for the existing x87 FPU registers, which context switches would save and restore. Unlike the x87 registers, which behave like a stack, the MMX registers are each directly addressable. Any operation involving the floating point stack might affect the MMX registers and vice versa, so this aliasing makes it difficult to work with floating point and SIMD operations in the same application. To maximize performance, programmers used the processor in one mode or the other, deferring the slow switch between them as long as possible; each 64-bit MMX register corresponds to the mantissa part of an 80-bit x87 register. The upper 16 bits of the x87 registers thus go unused in MMX, these bits are all set to ones, making them NaNs or infinities in the floating point representation; this can be used by applications to decide whether a particular register's content is intended as floating point or SIMD data.
Software support for MMX was slow in coming. Intel's C Compiler and related development tools obtained intrinsics for invoking MMX instructions and Intel released libraries of common vectorized algorithms using MMX. Both Intel and Metrowerks attempted automatic vectorization in their compilers, but the operations in the C programming language mapped poorly onto the MMX instruction set and custom algorithms as of 2000 still had to be written in assembly. AMD, a competing x86 microprocessor vendor, enhanced Intel's MMX with their own 3DNow! Instruction set. 3DNow is best known for adding single-precision floating-point support to the SIMD instruction-set, among other integer and more general enhancements. Following MMX, Intel's next major x86 extension was the SSE, introduced with the Pentium-III family. SSE addressed the core shortcomings of MMX by creating a new 128-bit wide register file and new SIMD instructions for it. Like 3DNow!, SSE focused on single-precision floating-point operations. However, the new XMM register-file allowed SSE SIMD-operations to be mixed with either MMX or x87 FPU ops.
SSE2, introduced with the Pentium 4, further extended the x86 SIMD instruction set with integer and double-precision floating-point data support for the XMM register file. SSE2 allowed the MMX opcodes to use XMM register operands, extended to wider YMM and ZMM registers by SSE revisions. Intel's and Marvell's XScale microprocessor core starting with PXA270 include an SIMD instruction set extension to the ARM core called iwMMXt whose functions are similar to those of the IA-32 MMX extension. IwMMXt stands for "Intel Wireless MMX Technology", it provides logic operations on 64-bit integer numbers. The extension contains. All registers are accessed through standard ARM architecture coprocessor mapping mechanism. IwMMXt occupies coprocessors 0 and 1 space, some of its opcodes clash with the opcodes of the earlier floating-point extension, FPA. Versions of Marvell's ARM processo
The Intel 80386 known as i386 or just 386, is a 32-bit microprocessor introduced in 1985. The first versions had 275,000 transistors and were the CPU of many workstations and high-end personal computers of the time; as the original implementation of the 32-bit extension of the 80286 architecture, the 80386 instruction set, programming model, binary encodings are still the common denominator for all 32-bit x86 processors, termed the i386-architecture, x86, or IA-32, depending on context. The 32-bit 80386 can execute most code intended for the earlier 16-bit processors such as 8086 and 80286 that were ubiquitous in early PCs. Over the years, successively newer implementations of the same architecture have become several hundreds of times faster than the original 80386. A 33 MHz 80386 was measured to operate at about 11.4 MIPS. The 80386 was introduced in October 1985, while manufacturing of the chips in significant quantities commenced in June 1986. Mainboards for 80386-based computer systems were cumbersome and expensive at first, but manufacturing was rationalized upon the 80386's mainstream adoption.
The first personal computer to make use of the 80386 was designed and manufactured by Compaq and marked the first time a fundamental component in the IBM PC compatible de facto standard was updated by a company other than IBM. In May 2006, Intel announced that 80386 production would stop at the end of September 2007. Although it had long been obsolete as a personal computer CPU, Intel and others had continued making the chip for embedded systems; such systems using an 80386 or one of many derivatives are common in aerospace technology and electronic musical instruments, among others. Some mobile phones used the 80386 processor, such as BlackBerry 950 and Nokia 9000 Communicator; the processor was a significant evolution in the x86 architecture, extended a long line of processors that stretched back to the Intel 8008. The predecessor of the 80386 was the Intel 80286, a 16-bit processor with a segment-based memory management and protection system; the 80386 added a 32-bit architecture and a paging translation unit, which made it much easier to implement operating systems that used virtual memory.
It offered support for register debugging. The 80386 featured three operating modes: protected mode and virtual mode; the protected mode, which debuted in the 286, was extended to allow the 386 to address up to 4 GB of memory. The all new virtual 8086 mode made it possible to run one or more real mode programs in a protected environment, although some programs were not compatible; the ability for a 386 to be set up to act like it had a flat memory model in protected mode despite the fact that it uses a segmented memory model in all modes would arguably be the most important feature change for the x86 processor family until AMD released x86-64 in 2003. Several new instructions have been added to 386: BSF, BSR, BT, BTS, BTR, BTC, CDQ, CWDE, LFS, LGS, LSS, MOVSX, MOVZX, SETcc, SHLD, SHRD. Two new segment registers have been added for general-purpose programs, single Machine Status Word of 286 grew into eight control registers CR0–CR7. Debug registers DR0–DR7 were added for hardware breakpoints. New forms of MOV instruction are used to access them.
Chief architect in the development of the 80386 was John H. Crawford, he was responsible for extending the 80286 architecture and instruction set to 32-bit, led the microprogram development for the 80386 chip. The 80486 and P5 Pentium line of processors were descendants of the 80386 design; the following data types are directly supported and thus implemented by one or more 80386 machine instructions. 8-bit integer, either signed or unsigned. 16-bit integer, either signed or unsigned. 32-bit integer, either signed or unsigned. 64-bit integer, either signed or unsigned. Offset, a 16- or 32-bit displacement referring to a memory location. Pointer, a 16-bit selector together with a 16- or 32-bit offset. Character. String, a sequence of 8-, 16- or 32-bit words. BCD, decimal digits represented by unpacked bytes. Packed BCD, two BCD digits in one byte; the following 80386 assembly source code is for a subroutine named _strtolower that copies a null-terminated ASCIIZ character string from one location to another, converting all alphabetic characters to lower case.
The string is copied one byte at a time. The example code uses the EBP register to establish a call frame, an area on the stack that contains all of the parameters and local variables for the execution of the subroutine; this kind of calling convention supports reentrant and recursive code and has been used by Algol-like languages since the late 1950s. A flat memory model is assumed that the DS and ES segments address the same region of memory. In 1988, Intel introduced the 80386SX, most referred to as the 386SX, a cut-down version of the 80386 with a 16-bit data bus intended for lower-cost PCs aimed at the home and small-business markets, while the 386DX would remain the high-end variant used in workstations and other demanding tasks; the CPU remained 32-bit internally, but the 16-bit
Intel Quark is a line of 32-bit x86 SoCs and microcontrollers by Intel, designed for small size and low power consumption, targeted at new markets including wearable devices. The line was introduced at Intel Developer Forum in 2013. Quark processors, while slower than Atom processors, consume less power, they lack only support embedded operating systems. Quark powers the Intel Galileo developer microcontroller board. However, in 2016 Arduino released the Arduino 101 board that includes an Intel Quark SoCThe CPU instruction set is the same as a Pentium CPU; the first product in the Quark line is the single-core 32 nm X1000 SoC with a clock rate of up to 400 MHz. The system includes several interfaces, including PCI Express, serial UART, I²C, Fast Ethernet, USB 2.0, SDIO, power management controller, GPIO. There are 16 KB of an integrated DDR3 memory controller. A second Intel product that includes Quark core, the Intel Edison microcomputer, was presented in January 2014, it has a form factor close to the size of an SD card, is capable of wireless networking using Wi-Fi or Bluetooth.
In January 2015, Intel announced the sub-miniature Intel Curie module for wearable applications, based on a Quark SE core with 80 KB SRAM and 384 KB flash. At the size of a button, it features a 6-axis accelerometer, a DSP sensor hub, a Bluetooth LE unit and a battery charge controller; the name Lakemont has been used in reference to the processor core in multiple Quark-series processors. Intel Quark SoC X1000 contains a bug #71538 that "under specific circumstances" results in a type of crash known as a segfault; the workaround implemented by Intel is to omit in the compiled code LOCK prefixes not required on single threaded processors. While source-based embedded systems like those built using the Yocto Project can incorporate this workaround at compile time, general purpose Linux distributions such as Debian are affected by the bug; such a workaround is not easy to implement in binaries meant to support multithreading too as they require LOCK prefixes to function properly. Intel Management Engine Intel Quark SoC Documents Quark family // Intel ARK Intel's'Quark' lineup targets wearables.
Intel is making the tiniest of chips. // CNET, September 10, 2013 Intel Unveils Tiny Quark Chips for Wearable Devices. Processor Is One-Fifth the Size of Its Low-End Atom Chip // The WSJ, September 10, 2013 Intel introduces Quark, a tiny chip for the internet of things and wearable computing // The Verge, 2013-09-10 With Quark, Intel blesses the market of chips for wearable devices // Ventureboat, 2013-09-12
A microprocessor is a computer processor that incorporates the functions of a central processing unit on a single integrated circuit, or at most a few integrated circuits. The microprocessor is a multipurpose, clock driven, register based, digital integrated circuit that accepts binary data as input, processes it according to instructions stored in its memory, provides results as output. Microprocessors contain sequential digital logic. Microprocessors operate on symbols represented in the binary number system; the integration of a whole CPU onto a single or a few integrated circuits reduced the cost of processing power. Integrated circuit processors are produced in large numbers by automated processes, resulting in a low unit price. Single-chip processors increase reliability because there are many fewer electrical connections that could fail; as microprocessor designs improve, the cost of manufacturing a chip stays the same according to Rock's law. Before microprocessors, small computers had been built using racks of circuit boards with many medium- and small-scale integrated circuits.
Microprocessors combined this into a few large-scale ICs. Continued increases in microprocessor capacity have since rendered other forms of computers completely obsolete, with one or more microprocessors used in everything from the smallest embedded systems and handheld devices to the largest mainframes and supercomputers; the complexity of an integrated circuit is bounded by physical limitations on the number of transistors that can be put onto one chip, the number of package terminations that can connect the processor to other parts of the system, the number of interconnections it is possible to make on the chip, the heat that the chip can dissipate. Advancing technology makes more powerful chips feasible to manufacture. A minimal hypothetical microprocessor might include only an arithmetic logic unit, a control logic section; the ALU performs addition and operations such as AND or OR. Each operation of the ALU sets one or more flags in a status register, which indicate the results of the last operation.
The control logic retrieves instruction codes from memory and initiates the sequence of operations required for the ALU to carry out the instruction. A single operation code might affect many individual data paths and other elements of the processor; as integrated circuit technology advanced, it was feasible to manufacture more and more complex processors on a single chip. The size of data objects became larger. Additional features were added to the processor architecture. Floating-point arithmetic, for example, was not available on 8-bit microprocessors, but had to be carried out in software. Integration of the floating point unit first as a separate integrated circuit and as part of the same microprocessor chip sped up floating point calculations. Physical limitations of integrated circuits made such practices as a bit slice approach necessary. Instead of processing all of a long word on one integrated circuit, multiple circuits in parallel processed subsets of each data word. While this required extra logic to handle, for example and overflow within each slice, the result was a system that could handle, for example, 32-bit words using integrated circuits with a capacity for only four bits each.
The ability to put large numbers of transistors on one chip makes it feasible to integrate memory on the same die as the processor. This CPU cache has the advantage of faster access than off-chip memory and increases the processing speed of the system for many applications. Processor clock frequency has increased more than external memory speed, so cache memory is necessary if the processor is not delayed by slower external memory. A microprocessor is a general-purpose entity. Several specialized processing devices have followed: A digital signal processor is specialized for signal processing. Graphics processing units are processors designed for realtime rendering of images. Other specialized units exist for video machine vision. Microcontrollers integrate a microprocessor with peripheral devices in embedded systems. Systems on chip integrate one or more microprocessor or microcontroller cores. Microprocessors can be selected for differing applications based on their word size, a measure of their complexity.
Longer word sizes allow each clock cycle of a processor to carry out more computation, but correspond to physically larger integrated circuit dies with higher standby and operating power consumption. 4, 8 or 12 bit processors are integrated into microcontrollers operating embedded systems. Where a system is expected to handle larger volumes of data or require a more flexible user interface, 16, 32 or 64 bit processors are used. An 8- or 16-bit processor may be selected over a 32-bit processor for system on a chip or microcontroller applications that require low-power electronics, or are part of a mixed-signal integrated circuit with noise-sensitive on-chip analog electronics such as high-resolution analog to digital converters, or both. Running 32-bit arithmetic on an 8-bit chip could end up using more power, as the chip must execute software with multiple instructions. Thousands of items that were traditionally not computer-related inc
VIA Technologies Inc. is a Taiwanese manufacturer of integrated circuits motherboard chipsets, CPUs, memory. It is the world's largest independent manufacturer of motherboard chipsets; as a fabless semiconductor company, VIA conducts research and development of its chipsets in-house subcontracts the actual manufacturing to third-party merchant foundries, such as TSMC. The company was founded in Fremont, California, USA by Cher Wang. In 1992, it was decided to move the headquarters to Taipei, Taiwan in order to establish closer partnerships with the substantial and growing IT manufacturing base in Taiwan and neighbouring China. In 1999, VIA acquired most of Cyrix a division of National Semiconductor; that same year, VIA acquired Centaur Technology from Integrated Device Technology, marking its entry into the x86 microprocessor market. VIA is the maker of the VIA C3, VIA C7 & VIA Nano processors, the EPIA platform; the Cyrix MediaGX platform remained with National Semiconductor. In 2001, VIA established the S3 Graphics joint venture.
In January 2005, VIA began the VIA pc-1 Initiative, to develop information and communication technology systems to benefit those with no access to computers or Internet. In February 2005, VIA celebrated production of the 100 millionth VIA AMD chipset. On 29 August 2008, VIA announced that they would release official 2D accelerated Linux drivers for their chipsets, would release 3D accelerated drivers. In 2013, VIA entered into an agreement with the Shanghai Municipal Government to create a fabless semiconductor company called Zhaoxin; the joint venture is producing x86 compatible CPUs for the Chinese market. VIA's business focuses on integrated chipsets for the PC market. Among PC users, VIA is best known for its motherboard chipsets. However, VIA's products include audio controllers, network/connectivity controllers, low-power CPUs, CD/DVD-writer chipsets. PC and peripheral vendors such as ASUS buy the chipsets for inclusion into their own product brands. In the late 1990s, VIA began diversifying its core-logic business, the company has since made business acquisitions to form a CPU division, graphics division, a sound division.
As advances in silicon manufacturing continue to increase the level of integration and functionality in chipsets, VIA will need these divisions to remain competitive in the core-logic market. VIA has produced multiple x86 compatible CPUs, through its acquisitions of Cyrix and Centaur Technology. VIA still produces CPUs through the Zhaoxin joint venture; some of the VIA x86 processors contain an undocumented Alternate Instruction Set. VIA established itself as important supplier of PC components with its chipsets for Socket 7 platform. With the Apollo VP3 chipset VIA pioneered AGP support for Socket 7 processors. VIA's present market position derives from the success of its Pentium III chipsets. Intel discontinued the development of its SDRAM chipsets, stated as policy that only RAMBUS memory would be supported going forward. Since RAMBUS was more expensive and offered few, if any, obvious performance advantages, manufacturers found they could ship performance-equivalent PCs at a lower cost by using VIA chipsets.
In response to increasing market competition, VIA decided to buy out the ailing S3 Graphics business. While the Savage chipset was not fast enough to survive as a discrete solution, its low manufacturing cost made it an ideal integrated solution, as part of the VIA northbridge. Under VIA, the S3 brand has held onto a 10% share of the PC graphics market, behind Intel, AMD, Nvidia. VIA includes the VIA Envy soundcard on its motherboards, which offers 24-bit sound. While its Pentium 4 chipset designs have struggled to win market share, in the face of legal threats from Intel, the K8T800 chipset for the Athlon 64 has been popular. VIA has continued the development of its VIA C3 and VIA C7 processors, targeting small, low power applications, a market space in which VIA is successful. In January 2008, Via unveiled the VIA Nano, an 11 mm × 11 mm footprint VM-enabled x86-64 processor, which debuted in May 2008, for ultra-mobile PCs. On the basis of the IDT Centaur acquisition, VIA appears to have come into possession of at least three patents, which cover key aspects of processor technology used by Intel.
On the basis of the negotiating leverage these patents offered, in 2003, VIA arrived at an agreement with Intel that allowed for a ten-year patent cross license, enabling VIA to continue to design and manufacture x86 compatible CPUs. VIA was granted a three-year grace period in which it could continue to use Intel socket infrastructure. Mini-ITX Pico-ITX Nano-ITX NanoBook List of VIA chipsets List of VIA microprocessor cores VIA Technologies VIA Arena Homepage The 100 Millionth VIA AMD Chipset viagallery.com's photostream Palm-sized ZOTAC ZBOX Featuring VIA Nano X2 ZOTAC ZBOX Nano Performance: VIA vs. AMD Zhaoxin wikichip.org
The first Pentium microprocessor was introduced by Intel on March 22, 1993. Dubbed P5, its microarchitecture was the fifth generation for Intel, the first superscalar IA-32 microarchitecture; as a direct extension of the 80486 architecture, it included dual integer pipelines, a faster floating-point unit, wider data bus, separate code and data caches and features for further reduced address calculation latency. In 1996, the Pentium with MMX Technology was introduced with the same basic microarchitecture complemented with an MMX instruction set, larger caches, some other enhancements; the P5 Pentium competitors included the Motorola 68060 and the PowerPC 601 as well as the SPARC, MIPS, Alpha microprocessor families, most of which used a superscalar in-order dual instruction pipeline configuration at some time. Intel's Larrabee multicore architecture project uses a processor core derived from a P5 core, augmented by multithreading, 64-bit instructions, a 16-wide vector processing unit. Intel's low-powered Bonnell microarchitecture employed in early Atom processor cores uses an in-order dual pipeline similar to P5.
Intel discontinued the P5 Pentium processors in 1999 in favor of the Celeron processor which replaced the 80486 brand. The P5 microarchitecture was designed by the same Santa Clara team which designed the 386 and 486. Design work started in 1989; the preliminary design was first simulated in 1990, followed by the laying-out of the design. By this time, the team had several dozen engineers; the design was taped out, or transferred to silicon, in April 1992, at which point beta-testing began. By mid-1992, the P5 team had 200 engineers. Intel at first planned to demonstrate the P5 in June 1992 at the trade show PC Expo, to formally announce the processor in September 1992, but design problems forced the demo to be cancelled, the official introduction of the chip was delayed until the spring of 1993. John H. Crawford, chief architect of the original 386, co-managed the design of the P5, along with Donald Alpert, who managed the architectural team. Dror Avnon managed the design of the FPU. Vinod K. Dham was general manager of the P5 group.
The P5 microarchitecture brings several important advancements over the preceding i486 architecture. Performance: Superscalar architecture — The Pentium has two datapaths that allow it to complete two instructions per clock cycle in many cases; the main pipe can handle any instruction, while the other can handle the most common simple instructions. Some RISC proponents had argued that the "complicated" x86 instruction set would never be implemented by a pipelined microarchitecture, much less by a dual-pipeline design; the 486 and the Pentium demonstrated that this was indeed feasible. 64-bit external databus doubles the amount of information possible to read or write on each memory access and therefore allows the Pentium to load its code cache faster than the 80486. Separation of code and data caches lessens the fetch and operand read/write conflicts compared to the 486. To reduce access time and implementation cost, both of them are 2-way associative, instead of the single 4-way cache of the 486.
A related enhancement in the Pentium is the ability to read a contiguous block from the code cache when it is split between two cache lines. Much faster floating-point unit; some instructions showed an enormous improvement, most notably FMUL, with up to 15 times higher throughput than in the 80486 FPU. The Pentium is able to execute a FXCH ST instruction in parallel with an ordinary FPU instruction. Four-input address adders enables the Pentium to further reduce the address calculation latency compared to the 80486; the Pentium can calculate full addressing modes with segment-base + base-register + scaled register + immediate offset in a single cycle. The microcode can employ both pipelines to enable auto-repeating instructions such as REP MOVSW perform one iteration every clock cycle, while the 80486 needed three clocks per iteration. Optimization of the access to the first microcode words during the decode stages helps in making several frequent instructions execute more especially in their most common forms and in typical cases.
Some examples are: CALL, RET, shifts/rotates. A faster hardware-based multiplier makes instructions such as MUL and IMUL several times faster than in the 80486. Virtualized interrupt to speed up virtual 8086 mode. Other features: Enhanced debug features with the introduction of the Processor-based debug port. Enhanced self-test features like the L1 cache parity check. New instructions: CPUID, CMPXCHG8B, RDTSC, RDMSR, WRMSR, RSM. Test registers TR0–TR7 and MOV instructions for access to them were eliminated; the Pentium MMX added the MMX instruction set, a basic integer SIMD instruction set extension marketed for use in multimedia applications. MMX could not be used with the x87 FPU instructions because the registers were