X87 is a floating-point-related subset of the x86 architecture instruction set. It originated as an extension of the 8086 instruction set in the form of optional floating-point coprocessors that worked in tandem with corresponding x86 CPUs; these microchips had names ending in "87". This was known as the NPX. Like other extensions to the basic instruction set, x87 instructions are not needed to construct working programs, but provide hardware and microcode implementations of common numerical tasks, allowing these tasks to be performed much faster than corresponding machine code routines can; the x87 instruction set includes instructions for basic floating-point operations such as addition and comparison, but for more complex numerical operations, such as the computation of the tangent function and its inverse, for example. Most x86 processors since the Intel 80486 have had these x87 instructions implemented in the main CPU, but the term is sometimes still used to refer to that part of the instruction set.
Before x87 instructions were standard in PCs, compilers or programmers had to use rather slow library calls to perform floating-point operations, a method, still common in embedded systems. The x87 registers form an 8-level deep non-strict stack structure ranging from ST to ST with registers that can be directly accessed by either operand, using an offset relative to the top, as well as pushed and popped. There are instructions to push and pop values on top of this stack; the non-strict stack model allows binary operations to use ST together with a direct memory operand or with an explicitly specified stack register, ST, in a role similar to a traditional accumulator. This can be reversed on an instruction-by-instruction basis with ST as the unmodified operand and ST as the destination. Furthermore, the contents in ST can be exchanged with another stack register using an instruction called FXCH ST; these properties make the x87 stack usable as seven addressable registers plus a dedicated accumulator.
This is applicable on superscalar x86 processors, where these exchange instructions are optimized down to a zero clock penalty by using one of the integer paths for FXCH ST in parallel with the FPU instruction. Despite being natural and convenient for human assembly language programmers, some compiler writers have found it complicated to construct automatic code generators that schedule x87 code effectively; such a stack-based interface can minimize the need to save scratch variables in function calls compared with a register-based interface The x87 provides single-precision, double-precision and 80-bit double-extended precision binary floating-point arithmetic as per the IEEE 754-1985 standard. By default, the x87 processors all use 80-bit double-extended precision internally. A given sequence of arithmetic operations may thus behave differently compared to a strict single-precision or double-precision IEEE 754 FPU; as this may sometimes be problematic for some semi-numerical calculations written to assume double precision for correct operation, to avoid such problems, the x87 can be configured using a special configuration/status register to automatically round to single or double precision after each operation.
Since the introduction of SSE2, the x87 instructions are not as essential as they once were, but remain important as a high-precision scalar unit for numerical calculations sensitive to round-off error and requiring the 64-bit mantissa precision and extended range available in the 80-bit format. Clock cycle counts for examples of typical x87 FPU instructions; the A... B notation covers timing variations dependent on transient pipeline status and the arithmetic precision chosen; the L → H notation depicts values corresponding to the lowest and the highest maximal clock frequencies that were available. * An effective zero clock delay is possible, via superscalar execution. § The 5 MHz 8087 was the original x87 processor. Compared to typical software-implemented floating-point routines on an 8086, the factors would be larger by another factor of 10. Companies that have designed or manufactured floating-point units compatible with the Intel 8087 or models include AMD, Chips and Technologies, Fujitsu, Harris Semiconductor, IBM, IDT, IIT, LC Technology, National Semiconductor, NexGen, Rise Technology, ST Microelectronics, Texas Instruments, Transmeta, ULSI (the Math·Co copr
In computing, floating-point arithmetic is arithmetic using formulaic representation of real numbers as an approximation so as to support a trade-off between range and precision. For this reason, floating-point computation is found in systems which include small and large real numbers, which require fast processing times. A number is, in general, represented to a fixed number of significant digits and scaled using an exponent in some fixed base. A number that can be represented is of the following form: significand × base exponent, where significand is an integer, base is an integer greater than or equal to two, exponent is an integer. For example: 1.2345 = 12345 ⏟ significand × 10 ⏟ base − 4 ⏞ exponent. The term floating point refers to the fact that a number's radix point can "float"; this position is indicated as the exponent component, thus the floating-point representation can be thought of as a kind of scientific notation. A floating-point system can be used to represent, with a fixed number of digits, numbers of different orders of magnitude: e.g. the distance between galaxies or the diameter of an atomic nucleus can be expressed with the same unit of length.
The result of this dynamic range is that the numbers that can be represented are not uniformly spaced. Over the years, a variety of floating-point representations have been used in computers. In 1985, the IEEE 754 Standard for Floating-Point Arithmetic was established, since the 1990s, the most encountered representations are those defined by the IEEE; the speed of floating-point operations measured in terms of FLOPS, is an important characteristic of a computer system for applications that involve intensive mathematical calculations. A floating-point unit is a part of a computer system specially designed to carry out operations on floating-point numbers. A number representation specifies some way of encoding a number as a string of digits. There are several mechanisms. In common mathematical notation, the digit string can be of any length, the location of the radix point is indicated by placing an explicit "point" character there. If the radix point is not specified the string implicitly represents an integer and the unstated radix point would be off the right-hand end of the string, next to the least significant digit.
In fixed-point systems, a position in the string is specified for the radix point. So a fixed-point scheme might be to use a string of 8 decimal digits with the decimal point in the middle, whereby "00012345" would represent 0001.2345. In scientific notation, the given number is scaled by a power of 10, so that it lies within a certain range—typically between 1 and 10, with the radix point appearing after the first digit; the scaling factor, as a power of ten, is indicated separately at the end of the number. For example, the orbital period of Jupiter's moon Io is 152,853.5047 seconds, a value that would be represented in standard-form scientific notation as 1.528535047×105 seconds. Floating-point representation is similar in concept to scientific notation. Logically, a floating-point number consists of: A signed digit string of a given length in a given base; this digit string is referred to mantissa, or coefficient. The length of the significand determines the precision; the radix point position is assumed always to be somewhere within the significand—often just after or just before the most significant digit, or to the right of the rightmost digit.
This article follows the convention that the radix point is set just after the most significant digit. A signed integer exponent. To derive the value of the floating-point number, the significand is multiplied by the base raised to the power of the exponent, equivalent to shifting the radix point from its implied position by a number of places equal to the value of the exponent—to the right if the exponent is positive or to the left if the exponent is negative. Using base-10 as an example, the number 152,853.5047, which has ten decimal digits of precision, is represented as the significand 1,528,535,047 together with 5 as the exponent. To determine the actual value, a decimal point is placed after the first digit of the significand and the result is multiplied by 105 to give 1.528535047×105, or 152,853.5047. In storing such a number, the base need not be stored, since it will be the same for the entire range of supported numbers, can thus be inferred. Symbolically, this final value is: s b p − 1 × b e, where s is the
Intel Core is a line of mid- to high-end consumer and enthusiast central processing units marketed by Intel Corporation. These processors displaced the existing mid- to high-end Pentium processors of the time, moving the Pentium to the entry level, bumping the Celeron series of processors to the low end. Identical or more capable versions of Core processors are sold as Xeon processors for the server and workstation markets; as of June 2017, the lineup of Core processors includes the Intel Core i9, Intel Core i7, Intel Core i5, Intel Core i3, along with the X-series Intel Core CPUs. In early 2018, news reports indicated that security flaws, referred to as "Meltdown" and "Spectre", were found "in all Intel processors that will require fixes within Windows, macOS and Linux"; the flaw affected cloud servers. At the time, Intel was not commenting on this issue. According to a New York Times report, "There is no easy fix for Spectre... as for Meltdown, the software patch needed to fix the issue could slow down computers by as much as 30 percent".
In mid 2018, the majority of Intel Core processors were found to possess a defect, which undermines the Software Guard Extensions feature of the processor. Although Intel Core is a brand that promises no internal consistency or continuity, the processors within this family have been, for the most part, broadly similar; the first products receiving this designation were the Core Solo and Core Duo Yonah processors for mobile from the Pentium M design tree, fabricated at 65 nm and brought to market in January 2006. These are different in design than the rest of the Intel Core product group, having derived from the Pentium Pro lineage that predated Pentium 4; the first Intel Core desktop processor—and typical family member—came from the Conroe iteration, a 65 nm dual-core design fabricated brought to market in July 2006, based on the all-new Intel Core microarchitecture with substantial enhancements in micro-architectural efficiency and performance, outperforming Pentium 4 across the board, while operating at drastically lower clock rates.
Maintaining high instructions per cycle on a pipelined and resourced out-of-order execution engine has remained a constant fixture of the Intel Core product group since. The new substantial bump in microarchitecture came with the introduction of the 45 nm Bloomfield desktop processor in November 2008 on the Nehalem architecture, whose main advantage came from redesigned I/O and memory systems featuring the new Intel QuickPath Interconnect and an integrated memory controller supporting up to three channels of DDR3 memory. Subsequent performance improvements have tended toward making additions rather than profound changes, such as adding the Advanced Vector Extensions instruction set extensions to Sandy Bridge, first released on 32 nm in January 2011. Time has brought improved support for virtualization and a trend toward higher levels of system integration and management functionality through the ongoing evolution of facilities such as Intel Active Management Technology. Since 2019, the Core brand has been based on 4 products, consisting of the entry level i3, the mainstream i5, the high-end i7, the enthusiast i9.
Clock speed slowest 1.2 GHz to the fastest 4.2 GHz The original Core brand refers to Intel's 32-bit mobile dual-core x86 CPUs, which derived from the Pentium M branded processors. The processor family used an enhanced version of the Intel P6 microarchitecture, it emerged in parallel with the NetBurst microarchitecture of the Pentium 4 brand, was a precursor of the 64-bit Core microarchitecture of Core 2 branded CPUs. The Core brand comprised two branches: the Duo and Solo. Intel launched the Core brand on January 6, 2006 with the release of the 32-bit Yonah CPU – Intel's first dual-core mobile processor, its dual-core layout resembled two interconnected Pentium M branded CPUs packaged as a single die silicon chip. Hence, the 32-bit microarchitecture of Core branded CPUs – contrary to its name – had more in common with Pentium M branded CPUs than with the subsequent 64-bit Core microarchitecture of Core 2 branded CPUs. Despite a major rebranding effort by Intel starting January 2006, some companies continued to market computers with the Yonah core marked as Pentium M.
The Core series is the first Intel processor used as the main CPU in an Apple Macintosh computer. The Core Duo was the CPU for the first generation MacBook Pro, while the Core Solo appeared in Apple's Mac Mini line. Core Duo signified the beginning of Apple's shift to Intel processors across their entire line. In 2007, Intel began branding the Yonah core CPUs intended for mainstream mobile computers as Pentium Dual-Core, not to be confused with the desktop 64-bit Core microarchitecture CPUs branded as Pentium Dual-Core. September 2007 and January 4, 2008, marked the discontinuation of a number of Core branded CPUs including several Core Solo, Core Duo and one Core 2 Quad chip. Intel Core Solo features only one active core. Depending on demand, Intel may simply disable one of the cores to sell the chip at the Core Solo price—this requires less effort than launching and maintaining a separate line of CPUs that physically only have one core. Intel used the same strategy with the 486 CPU in which early 486SX CPUs were in fact manufactured as 486DX CPUs but with the FPU disabled.
Intel Core Duo consists of two co
Pentium is a brand used for a series of x86 architecture-compatible microprocessors produced by Intel since 1993. In their form as of November 2011, Pentium processors are considered entry-level products that Intel rates as "two stars", meaning that they are above the low-end Atom and Celeron series, but below the faster Core i3, i5, i7, i9, workstation Xeon series; as of 2017, Pentium processors have little more than their name in common with earlier Pentiums, which were Intel's flagship processor for over a decade until the introduction of the Intel Core line in 2006. They are based on both the architecture used in that of Core processors. In the case of Atom architectures, Pentiums are the highest performance implementations of the architecture. Pentium processors with Core architectures prior to 2017 were distinguished from the faster, higher-end i-series processors by lower clock rates and disabling some features, such as hyper-threading and sometimes L3 cache; the name Pentium is derived from the Greek word penta, meaning "five", a reference to the prior numeric naming convention of Intel's 80x86 processors, with the Latin ending -ium.
In 2017, Intel split Pentium into two line-ups. Pentium Silver aiming for low-power devices and shares architecture with Atom and Celeron. Pentium Gold aiming for entry-level desktop and using existing architecture, such as Kaby Lake or Coffee Lake. During development, Intel identifies processors with codenames, such as Prescott, Coppermine, Klamath, or Deschutes; these become known after the processors are given official names on launch. The original Pentium-branded CPUs were expected to be named 586 or i586, to follow the naming convention of prior generations. However, as the firm wanted to prevent their competitors from branding their processors with similar names, Intel filed a trademark application on the name in the United States, but was denied because a series of numbers was considered to lack trademark distinctiveness. Following Intel's prior series of 8086, 80186, 80286, 80386, 80486 microprocessors, the firm's first P5-based microprocessor was released as the original Intel Pentium on March 22, 1993.
Marketing firm Lexicon Branding was hired to coin a name for the new processor. The suffix -ium was chosen as it could connote a fundamental ingredient of a computer, like a chemical element, while the prefix pent- could refer to the fifth generation of x86. Due to its success, the Pentium brand would continue through several generations of high-end processors. In 2006, the name disappeared from Intel's technology roadmaps, only to re-emerge in 2007. In 1998, Intel introduced the Celeron brand for low-priced microprocessors. With the 2006 introduction of the Intel Core brand as the company's new flagship line of processors, the Pentium series was to be discontinued. However, due to a demand for mid-range dual-core processors, the Pentium brand was repurposed to be Intel's mid-range processor series, between the Celeron and Core series, continuing with the Pentium Dual-Core line. In 2009, the "Dual-Core" suffix was dropped, new x86 microprocessors started carrying the plain Pentium name again.
In 2014, Intel released the Pentium 20th Anniversary Edition, to mark the 20th anniversary of the Pentium brand. The processors are unlocked and overclockable. In 2017, Intel splits Pentium into two line-ups, Pentium Silver aiming for low-power devices and shares architecture with Atom and Celeron and Pentium Gold aiming for entry-level desktop and using existing architecture, such as Kaby Lake or Coffee Lake The original Intel P5 or Pentium and Pentium MMX processors were the superscalar follow-on to the 80486 processor and were marketed from 1993 to 1999; some versions of these were available as Pentium OverDrive. In parallel with the P5 microarchitecture, Intel developed the P6 microarchitecture and started marketing it as the Pentium Pro for the high-end market in 1995, it introduced out-of-order execution and an integrated second-level cache on dual-chip processor package. The second P6 generation replaced the original P5 with the Pentium II and rebranded the high-end version as Pentium II Xeon.
It was followed by a third version named the Pentium Pentium III Xeon respectively. The Pentium II line added the MMX instructions that were present in the Pentium MMX. Versions of these processors for the laptop market were named Mobile Pentium II and Mobile Pentium III versions were named Pentium III-M. Starting with the Pentium II, the Celeron brand was used for low-end versions of most Pentium processors with a reduced feature set such as a smaller cache or missing power management features. In 2000, Intel introduced a new microarchitecture named NetBurst, with a much longer pipeline enabling higher clock frequencies than the P6-based processors; these were named Pentium 4, the high-end versions have since been named Xeon. As with Pentium III, there are both Mobile Pentium 4 and Pentium 4 M processors for the laptop market, with Pentium 4 M denoting the more power-efficient versions. Enthusiast versions of the Pentium 4 with the highest clock rates were named Pentium 4 Extreme Edition; the Pentium D was the first multi-core Pentium, integrating two Pentium 4 chips in one package and was available as the enthusiast Pentium Extreme Edition.
In 2003, Intel introduced a new processor based on the P6 microarchitecture named Pentium M, much more power-efficient than the Mobile Pentium 4, Pentium 4 M, Pentium III M. Dual-core versions of the Pentium M were developed under the code name Yonah and sold under the marketing names Core Duo and Pentium Dual-Core. Unlike Pentium D, it
The Intel 8008 is an early byte-oriented microprocessor designed and manufactured by Intel and introduced in April 1972. It is an 8-bit CPU with an external 14-bit address bus. Known as the 1201, the chip was commissioned by Computer Terminal Corporation to implement an instruction set of their design for their Datapoint 2200 programmable terminal; as the chip was delayed and did not meet CTC's performance goals, the 2200 ended up using CTC's own TTL-based CPU instead. An agreement permitted Intel to market the chip to other customers after Seiko expressed an interest in using it for a calculator. CTC formed in San Antonio in 1968 under the direction of Austin O. "Gus" Roche and Phil Ray, both NASA engineers. Roche, in particular, was interested in producing a desktop computer. However, given the immaturity of the market, the company's business plan mentioned only a Teletype Model 33 ASR replacement, which shipped as the Datapoint 3300; the case was deliberately designed to fit in the same space as an IBM Selectric typewriter and used a video screen shaped to have the same aspect ratio as an IBM punched card.
Although commercially successful, the 3300 had ongoing heat problems due to the amount of circuitry packed into such a small space. In order to address the heating and other issues, a re-design started that featured the CPU part of the internal circuitry re-implemented on a single chip. Looking for a company able to produce their chip design, Roche turned to Intel primarily a vendor of memory chips. Roche met with Bob Noyce, he said that if you have a computer chip, you can only sell one chip per computer, while with memory, you can sell hundreds of chips per computer." Another major concern was that Intel's existing customer base purchased their memory chips for use with their own processor designs. Noyce agreed to a $50,000 development contract in early 1970. Texas Instruments was brought in as a second supplier. TI was able to make samples of the 1201 based on Intel drawings, but these proved to be buggy and were rejected. Intel's own versions were delayed. CTC decided to re-implement the new version of the terminal using discrete TTL instead of waiting for a single-chip CPU.
The new system was released as the Datapoint 2200 in the spring 1970, with their first sale to General Mills on May 25, 1970. CTC paused development of the 1201. Six months Seiko approached Intel, expressing an interest in using the 1201 in a scientific calculator after seeing the success of the simpler Intel 4004 used by Busicom in their business calculators. A small re-design followed, under the leadership of Federico Faggin, the designer of the 4004, now project leader of the 1201, expanding from a 16-pin to 18-pin design, the new 1201 was delivered to CTC in late 1971. By that point, CTC had once again moved on, this time to the Datapoint 2200 II, faster; the 1201 was no longer powerful enough for the new model. CTC voted to end their involvement with the 1201, leaving the design's intellectual property to Intel instead of paying the $50,000 contract. Intel renamed it the 8008 and put it in their catalog in April 1972 priced at $120. Intel's initial worries about their existing customer base leaving them proved unfounded, the 8008 went on to be a commercially successful design.
This was followed by the Intel 8080, the hugely successful Intel x86 family. One of the first teams to build a complete system around the 8008 was Bill Pentz' team at California State University, Sacramento; the Sac State 8008 was the first true microcomputer, with a disk operating system built with IBM Basic assembly language in PROM, all driving a color display, hard drive, modem, audio/paper tape reader and printer. The project started in the spring of 1972, with key help from Tektronix the system was functional a year later. Bill assisted Intel with the MCS-8 kit and provided key input to the Intel 8080 instruction set, which helped make it useful for the industry and hobbyists. In the UK, a team at S. E. Laboratories Engineering led by Tom Spink in 1972 built a microcomputer based on a pre-release sample of the 8008. Joe Hardman extended the chip with an external stack. This, among other things, gave it power-fail recovery. Joe developed a direct screen printer; the operating system was written using a meta-assembler developed by L. Crawford and J. Parnell for a Digital Equipment Corporation PDP-11.
The operating system was burnt into a PROM. It was interrupt-driven and based on a fixed page size for programs and data. An operational prototype was prepared for management; the 8008 was the CPU for the first commercial non-calculator personal computers: the US SCELBI kit and the pre-built French Micral N and Canadian MCM/70. The 8008 was implemented in 10 μm silicon-gate enhancement-mode PMOS logic. Initial versions could work at clock frequencies up to 0.5 MHz. This was increased in the 8008-1 to a specified maximum of 0.8 MHz. Instructions took between 11 T-states, where each T-state was 2 clock cycles. Register–register loads and ALU operations took 5T, register–memory 8T, while calls and jumps took 11 T-states; the 8008 was a little slower in terms of instructions per second (36,000 to 80,000 at 0.8 MH
X86 is a family of instruction set architectures based on the Intel 8086 microprocessor and its 8088 variant. The 8086 was introduced in 1978 as a 16-bit extension of Intel's 8-bit 8080 microprocessor, with memory segmentation as a solution for addressing more memory than can be covered by a plain 16-bit address; the term "x86" came into being because the names of several successors to Intel's 8086 processor end in "86", including the 80186, 80286, 80386 and 80486 processors. Many additions and extensions have been added to the x86 instruction set over the years consistently with full backward compatibility; the architecture has been implemented in processors from Intel, Cyrix, AMD, VIA and many other companies. Of those, only Intel, AMD, VIA hold x86 architectural licenses, are producing modern 64-bit designs; the term is not synonymous with IBM PC compatibility, as this implies a multitude of other computer hardware. As of 2018, the majority of personal computers and laptops sold are based on the x86 architecture, while other categories—especially high-volume mobile categories such as smartphones or tablets—are dominated by ARM.
In the 1980s and early 1990s, when the 8088 and 80286 were still in common use, the term x86 represented any 8086 compatible CPU. Today, however, x86 implies a binary compatibility with the 32-bit instruction set of the 80386; this is due to the fact that this instruction set has become something of a lowest common denominator for many modern operating systems and also because the term became common after the introduction of the 80386 in 1985. A few years after the introduction of the 8086 and 8088, Intel added some complexity to its naming scheme and terminology as the "iAPX" of the ambitious but ill-fated Intel iAPX 432 processor was tried on the more successful 8086 family of chips, applied as a kind of system-level prefix. An 8086 system, including coprocessors such as 8087 and 8089, as well as simpler Intel-specific system chips, was thereby described as an iAPX 86 system. There were terms iRMX, iSBC, iSBX – all together under the heading Microsystem 80. However, this naming scheme was quite temporary.
Although the 8086 was developed for embedded systems and small multi-user or single-user computers as a response to the successful 8080-compatible Zilog Z80, the x86 line soon grew in features and processing power. Today, x86 is ubiquitous in both stationary and portable personal computers, is used in midrange computers, workstations and most new supercomputer clusters of the TOP500 list. A large amount of software, including a large list of x86 operating systems are using x86-based hardware. Modern x86 is uncommon in embedded systems and small low power applications as well as low-cost microprocessor markets, such as home appliances and toys, lack any significant x86 presence. Simple 8-bit and 16-bit based architectures are common here, although the x86-compatible VIA C7, VIA Nano, AMD's Geode, Athlon Neo and Intel Atom are examples of 32- and 64-bit designs used in some low power and low cost segments. There have been several attempts, including by Intel itself, to end the market dominance of the "inelegant" x86 architecture designed directly from the first simple 8-bit microprocessors.
Examples of this are the iAPX 432, the Intel 960, Intel 860 and the Intel/Hewlett-Packard Itanium architecture. However, the continuous refinement of x86 microarchitectures and semiconductor manufacturing would make it hard to replace x86 in many segments. AMD's 64-bit extension of x86 and the scalability of x86 chips such as the eight-core Intel Xeon and 12-core AMD Opteron is underlining x86 as an example of how continuous refinement of established industry standards can resist the competition from new architectures; the table below lists processor models and model series implementing variations of the x86 instruction set, in chronological order. Each line item is characterized by improved or commercially successful processor microarchitecture designs. At various times, companies such as IBM, NEC, AMD, TI, STM, Fujitsu, OKI, Cyrix, Intersil, C&T, NexGen, UMC, DM&P started to design or manufacture x86 processors intended for personal computers as well as embedded systems; such x86 implementations are simple copies but employ different internal microarchitectures as well as different solutions at the electronic and physical levels.
Quite early compatible microprocessors were 16-bit, while 32-bit designs were developed much later. For the personal computer market, real quantities started to appear around 1990 with i386 and i486 compatible processors named to Intel's original chips. Other companies, which designed or manufactured x86 or x87 processors, include ITT Corporation, National Semiconductor, ULSI System Technology, Weitek. Following the pipelined i486, Intel introduced the Pentium brand name for their new set of superscalar x86 designs.
The first Pentium microprocessor was introduced by Intel on March 22, 1993. Dubbed P5, its microarchitecture was the fifth generation for Intel, the first superscalar IA-32 microarchitecture; as a direct extension of the 80486 architecture, it included dual integer pipelines, a faster floating-point unit, wider data bus, separate code and data caches and features for further reduced address calculation latency. In 1996, the Pentium with MMX Technology was introduced with the same basic microarchitecture complemented with an MMX instruction set, larger caches, some other enhancements; the P5 Pentium competitors included the Motorola 68060 and the PowerPC 601 as well as the SPARC, MIPS, Alpha microprocessor families, most of which used a superscalar in-order dual instruction pipeline configuration at some time. Intel's Larrabee multicore architecture project uses a processor core derived from a P5 core, augmented by multithreading, 64-bit instructions, a 16-wide vector processing unit. Intel's low-powered Bonnell microarchitecture employed in early Atom processor cores uses an in-order dual pipeline similar to P5.
Intel discontinued the P5 Pentium processors in 1999 in favor of the Celeron processor which replaced the 80486 brand. The P5 microarchitecture was designed by the same Santa Clara team which designed the 386 and 486. Design work started in 1989; the preliminary design was first simulated in 1990, followed by the laying-out of the design. By this time, the team had several dozen engineers; the design was taped out, or transferred to silicon, in April 1992, at which point beta-testing began. By mid-1992, the P5 team had 200 engineers. Intel at first planned to demonstrate the P5 in June 1992 at the trade show PC Expo, to formally announce the processor in September 1992, but design problems forced the demo to be cancelled, the official introduction of the chip was delayed until the spring of 1993. John H. Crawford, chief architect of the original 386, co-managed the design of the P5, along with Donald Alpert, who managed the architectural team. Dror Avnon managed the design of the FPU. Vinod K. Dham was general manager of the P5 group.
The P5 microarchitecture brings several important advancements over the preceding i486 architecture. Performance: Superscalar architecture — The Pentium has two datapaths that allow it to complete two instructions per clock cycle in many cases; the main pipe can handle any instruction, while the other can handle the most common simple instructions. Some RISC proponents had argued that the "complicated" x86 instruction set would never be implemented by a pipelined microarchitecture, much less by a dual-pipeline design; the 486 and the Pentium demonstrated that this was indeed feasible. 64-bit external databus doubles the amount of information possible to read or write on each memory access and therefore allows the Pentium to load its code cache faster than the 80486. Separation of code and data caches lessens the fetch and operand read/write conflicts compared to the 486. To reduce access time and implementation cost, both of them are 2-way associative, instead of the single 4-way cache of the 486.
A related enhancement in the Pentium is the ability to read a contiguous block from the code cache when it is split between two cache lines. Much faster floating-point unit; some instructions showed an enormous improvement, most notably FMUL, with up to 15 times higher throughput than in the 80486 FPU. The Pentium is able to execute a FXCH ST instruction in parallel with an ordinary FPU instruction. Four-input address adders enables the Pentium to further reduce the address calculation latency compared to the 80486; the Pentium can calculate full addressing modes with segment-base + base-register + scaled register + immediate offset in a single cycle. The microcode can employ both pipelines to enable auto-repeating instructions such as REP MOVSW perform one iteration every clock cycle, while the 80486 needed three clocks per iteration. Optimization of the access to the first microcode words during the decode stages helps in making several frequent instructions execute more especially in their most common forms and in typical cases.
Some examples are: CALL, RET, shifts/rotates. A faster hardware-based multiplier makes instructions such as MUL and IMUL several times faster than in the 80486. Virtualized interrupt to speed up virtual 8086 mode. Other features: Enhanced debug features with the introduction of the Processor-based debug port. Enhanced self-test features like the L1 cache parity check. New instructions: CPUID, CMPXCHG8B, RDTSC, RDMSR, WRMSR, RSM. Test registers TR0–TR7 and MOV instructions for access to them were eliminated; the Pentium MMX added the MMX instruction set, a basic integer SIMD instruction set extension marketed for use in multimedia applications. MMX could not be used with the x87 FPU instructions because the registers were