Ivy Bridge (microarchitecture)
Ivy Bridge is the codename for the "third generation" of the Intel Core processors. Ivy Bridge is a die shrink to 22 nanometer manufacturing process based on the 32 nanometer Sandy Bridge - see tick–tock model; the name is applied more broadly to the 22 nm die shrink of the Sandy Bridge microarchitecture based on FinFET Tri-Gate transistors, used in the Xeon and Core i7 Ivy Bridge-EX, Ivy Bridge-EP and Ivy Bridge-E microprocessors released in 2013. Ivy Bridge processors are backwards compatible with the Sandy Bridge platform, but such systems might require a firmware update. In 2011, Intel released the 7-series Panther Point chipsets with integrated USB 3.0 to complement Ivy Bridge. Volume production of Ivy Bridge chips began in the third quarter of 2011. Quad-core and dual-core-mobile models launched on May 31, 2012 respectively. Core i3 desktop processors, as well as the first 22 nm Pentium, were announced and available the first week of September 2012, it is the last Intel microarchitecture for which Windows XP driver support exists, while it is the first Intel microarchitecture to support Windows 10.
The Ivy Bridge CPU microarchitecture is a shrink from Sandy Bridge and remains unchanged. Like its predecessor, Sandy Bridge, Ivy Bridge was primarily developed by Intel's Israel branch, located in Haifa, Israel. Notable improvements include: 22 nm Tri-gate transistor technology. A new random number generator and the RdRand instruction, codenamed Bull Mountain; the mobile and desktop Ivy Bridge chips include significant changes over Sandy Bridge: F16C. RdRand instruction. PCI Express 3.0 support. Max CPU multiplier of 63. RAM support up to 2800 MT/s in 200 MHz increments; the built-in GPU has 6 or 16 execution units, compared to Sandy Bridge's 6 or 12. Intel HD Graphics with DirectX 11, OpenGL 3.1, OpenCL 1.1 support. OpenGL 4.0 is supported with 10.18.10.5059 WHQL drivers and drivers. On Linux OpenGL 4.2 is supported as of Mesa 17.1. DDR3L and configurable TDP for mobile processors. Multiple 4K video playback. Intel Quick Sync Video version 2. Up to three displays are supported. A 14- to 19-stage instruction pipeline, depending on the micro-operation cache hit or miss.
Compared to its predecessor, Sandy Bridge: 3% to 6% increase in CPU performance when compared clock for clock 25% to 68% increase in integrated GPU performance. Ivy Bridge's temperatures are 10 °C higher compared to Sandy Bridge when a CPU is overclocked at default voltage setting. Impress PC Watch, a Japanese website, performed experiments that confirmed earlier speculations that this is because Intel used a poor quality thermal interface material between the chip and the heat spreader, instead of the fluxless solder of previous generations; the mobile Ivy Bridge processors are not affected by this issue because they do not use a heat spreader between the chip and cooling system. Enthusiast reports describe the TIM used by Intel as low-quality, not up to par for a "premium" CPU, with some speculation that this is by design to encourage sales of prior processors. Further analyses caution that the processor can be damaged or void its warranty if home users attempt to remedy the matter; the TIM has much lower thermal conductivity.
Experiments with replacing this TIM with a higher-quality one or other heat removal methods showed a substantial temperature drop, improvements to the increased voltages and overclocking sustainable by Ivy Bridge chips. Intel claims that the smaller die of Ivy Bridge and the related increase in thermal density is expected to result in higher temperatures when the CPU is overclocked. All Ivy Bridge processors with one, two, or four cores report the same CPUID model 0x000306A9, are built in four different configurations differing in the number of cores, L3 cache and GPU execution units. Ivy Bridge-E family is the follow-up to Sandy Bridge-E, using the same CPU core as the Ivy Bridge processor, but in LGA 2011, LGA 1356 and LGA 2011-1 packages for workstations and servers. Dual memory controllers for Ivy Bridge-EP and Ivy Bridge-EX Up to 12 CPU cores and 30 MB of L3 cache for Ivy Bridge-EP Up to 15 CPU cores and 37.5 MB L3 cache for Ivy Bridge-EX Thermal design power between 50 W and 155 W Support for up to eight DIMMs of DDR3-1866 memory per socket, with reductions in memory speed depending on the number of DIMMs per channel No integrated GPU Ivy Bridge-EP introduced new hardware support for interrupt virtualization, branded as APICv.
The Ivy Bridge-E family is made in three different versions, by number of cores, for three market segments: the basic Ivy Bridge-E is a single-socket processor sold as Core i7-49xx and is only available in the six-core S1 stepping, with some versions limited to four active cores. Ivy Bridge-EN is the model for single- and dual-socket servers using LGA 1356 with up to 10 cores, while Ivy Bridge-EP scales up to four LGA 2011 sockets and up to 12 cores per chip. There are in fact three die "flavors" for the Ivy Bridge-EP, meaning that they are manufactured and organized differently, according to the number of cores an Ivy Bridge-EP CPU includ
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, in the Silicon Valley. It is the world's second largest and second highest valued semiconductor chip manufacturer based on revenue after being overtaken by Samsung, is the inventor of the x86 series of microprocessors, the processors found in most personal computers. Intel ranked No. 46 in the 2018 Fortune 500 list of the largest United States corporations by total revenue. Intel supplies processors for computer system manufacturers such as Apple, Lenovo, HP, Dell. Intel manufactures motherboard chipsets, network interface controllers and integrated circuits, flash memory, graphics chips, embedded processors and other devices related to communications and computing. Intel Corporation was founded on July 18, 1968, by semiconductor pioneers Robert Noyce and Gordon Moore, associated with the executive leadership and vision of Andrew Grove; the company's name was conceived as portmanteau of the words integrated and electronics, with co-founder Noyce having been a key inventor of the integrated circuit.
The fact that "intel" is the term for intelligence information made the name appropriate. Intel was an early developer of SRAM and DRAM memory chips, which represented the majority of its business until 1981. Although Intel created the world's first commercial microprocessor chip in 1971, it was not until the success of the personal computer that this became its primary business. During the 1990s, Intel invested in new microprocessor designs fostering the rapid growth of the computer industry. During this period Intel became the dominant supplier of microprocessors for PCs and was known for aggressive and anti-competitive tactics in defense of its market position against Advanced Micro Devices, as well as a struggle with Microsoft for control over the direction of the PC industry; the Open Source Technology Center at Intel hosts PowerTOP and LatencyTOP, supports other open-source projects such as Wayland, Mesa3D, Intel Array Building Blocks, Threading Building Blocks, Xen. Client Computing Group – 55% of 2016 revenues – produces hardware components used in desktop and notebook computers.
Data Center Group – 29% of 2016 revenues – produces hardware components used in server and storage platforms. Internet of Things Group – 5% of 2016 revenues – offers platforms designed for retail, industrial and home use. Non-Volatile Memory Solutions Group – 4% of 2016 revenues – manufactures NAND flash memory and 3D XPoint, branded as Optane, products used in solid-state drives. Intel Security Group – 4% of 2016 revenues – produces software security, antivirus software. Programmable Solutions Group – 3% of 2016 revenues – manufactures programmable semiconductors. In 2017, Dell accounted for about 16% of Intel's total revenues, Lenovo accounted for 13% of total revenues, HP Inc. accounted for 11% of total revenues. According to IDC, while Intel enjoyed the biggest market share in both the overall worldwide PC microprocessor market and the mobile PC microprocessor in the second quarter of 2011, the numbers decreased by 1.5% and 1.9% compared to the first quarter of 2011. In the 1980s, Intel was among the top ten sellers of semiconductors in the world.
In 1992, Intel became the biggest chip maker by revenue and has held the position since. Other top semiconductor companies include TSMC, Advanced Micro Devices, Texas Instruments, Toshiba and STMicroelectronics. Competitors in PC chipsets include Advanced Micro Devices, VIA Technologies, Silicon Integrated Systems, Nvidia. Intel's competitors in networking include NXP Semiconductors, Broadcom Limited, Marvell Technology Group and Applied Micro Circuits Corporation, competitors in flash memory include Spansion, Qimonda, Toshiba, STMicroelectronics, SK Hynix; the only major competitor in the x86 processor market is Advanced Micro Devices, with which Intel has had full cross-licensing agreements since 1976: each partner can use the other's patented technological innovations without charge after a certain time. However, the cross-licensing agreement is canceled in the event of takeover; some smaller competitors such as VIA Technologies produce low-power x86 processors for small factor computers and portable equipment.
However, the advent of such mobile computing devices, in particular, has in recent years led to a decline in PC sales. Since over 95% of the world's smartphones use processors designed by ARM Holdings, ARM has become a major competitor for Intel's processor market. ARM is planning to make inroads into the PC and server market. Intel has been involved in several disputes regarding violation of antitrust laws, which are noted below. Intel was founded in Mountain View, California, in 1968 by Gordon E. Moore, a chemist, Robert Noyce, a physicist and co-inventor of the integrated circuit. Arthur Rock helped. Moore and Noyce had left Fairchild Semiconductor to found Intel. Rock was not an employee; the total initial investment in Intel was $10,000 from Rock. Just 2 years Intel became a public company via an initial public offering, raising $6.8 million. Intel's third employee was Andy Grove, a chemical engineer, who ran the company through much of the 1980s and the high-growth 1990s. In dec
National Semiconductor was an American semiconductor manufacturer which specialized in analog devices and subsystems with headquarters in Santa Clara, United States. The company produced power management integrated circuits, display drivers and operational amplifiers, communication interface products and data conversion solutions. National's key markets included wireless handsets, displays and a variety of broad electronics markets, including medical, automotive and test and measurement applications. On September 23, 2011, the company formally became part of Texas Instruments as the "Silicon Valley" division. National Semiconductor was founded in Danbury, Connecticut, by Dr. Bernard J. Rothlein on May 27, 1959, when he and seven colleagues, Edward N. Clarke, Joseph J. Gruber, Milton Schneider, Robert L. Hopkins, Robert L. Koch, Richard R. Rau and Arthur V. Siefert, left their employment at the semiconductor division of Sperry Rand Corporation; the founding of the new company was followed by Sperry Rand filing a lawsuit against National Semiconductor for patent infringement.
By 1965, as it was reaching the courts, the preliminaries of the lawsuit had caused the stock value of National to be depressed. The depressed stock values allowed Peter J Sprague to invest in the company with Sprague's family funds. Sprague relied on further financial backing from a pair of West Coast investment firms and a New York underwriter to take control as the chairman of National Semiconductor. At that time Sprague was 27 years old. Jeffrey S. Young characterized the era as the beginning of venture capitalism; that same year National Semiconductor acquired Molectro. Molectro was founded in 1962 in Santa Clara, California, by J. Nall and D. Spittlehouse, who were employed at Fairchild Camera and Instrument Corporation; the acquisition brought to National Semiconductor two experts in linear semiconductor technologies, Robert Widlar and Dave Talbert, who were formerly employed at Fairchild. The acquisition of Molectro provided National with the technology to launch itself in the fabrication and manufacture of monolithic integrated circuits.
In 1967, Sprague hired five top executives away from Fairchild, among whom were Charles E. Sporck and Pierre Lamond. At the time of Sporck's hiring, Robert Noyce was de facto head of semiconductor operations at Fairchild and Sporck was his operations manager. Sporck was appointed CEO of National. To make the deal better for Sporck's hiring and appointment at half his former salary at Fairchild, Sporck was allotted a substantial share of National's stock. In essence, Sporck took four of his personnel from Fairchild with him as well as three others from TI, Perkin-Elmer, Hewlett-Packard to form a new eight-man team at National Semiconductor. Incidentally, Sporck had been Widlar's superior at Fairchild before Widlar left Fairchild to join Molectro after a compensation dispute with Sporck. In 1968, National shifted its headquarters from Connecticut, to Santa Clara, California. However, like many companies, National retained its registration as a Delaware corporation, for legal and financial expediency.
Over the years National Semiconductor acquired several companies like Fairchild Semiconductor, Cyrix. However, over time National Semiconductor spun off these acquisitions. Fairchild Semiconductor became a separate company again in 1997, the Cyrix microprocessors division was sold to VIA Technologies of Taiwan in 1999. From 1997 to 2002, National enjoyed a large amount of publicity and awards with the development of the Cyrix Media Center, Cyrix WebPad, WebPad Metro and National Origami PDA concept devices created by National's Conceptual Products Group. Based on the success of the WebPad, National formed the Information Appliance Division in 1998; the Information Appliance Division was sold to AMD in 2003. Other businesses dealing in such products as digital wireless chipsets, image sensors, PC I/O chipsets have been closed down or sold off as National has reincarnated itself as a high-performance analog semiconductor company. Peter Sprague, Pierre Lamond and the affectionately called Charlie Sporck worked hand-in-hand, with support of the board of directors to transform the company into a multinational and world-class semiconductor concern.
After becoming CEO, Sporck started a historic price war among semiconductor companies, which trimmed the number of competitors in the field. Among the casualties to exit the semiconductor business were General Electric and Westinghouse. Cost control, overhead reduction and a focus on profits implemented by Sporck was the key element to National surviving the price war and subsequently in 1981 becoming the first semiconductor company to reach the US$1 billion annual sales mark. However, the foundation that made National successful was its expertise in analog electronics, TTL and MOSFET integrated circuit technologies; as they had while employed in Fairchild and Lamond directed National Semiconductor towards the growing industrial and commercial markets and began to rely less on military and aerospace contracts. Those decisions coupled with inflationary growth in use of computers provided the market for the expansion of National. Meanwhile, sources of funds associated with Sprague coupled with creative structuring of cash flow buffering due to Sporck and Lamond provided the financing required for that expansion.
Lamond and Sporck had managed to attract and extract substantial funds to finance the expansion. Among Sporck's cost control efforts was his offshore outsourcing of labour. National Semiconductor was among the pioneers in the semicon
In computer engineering, microarchitecture called computer organization and sometimes abbreviated as µarch or uarch, is the way a given instruction set architecture is implemented in a particular processor. A given ISA may be implemented with different microarchitectures. Computer architecture is the combination of instruction set architecture; the ISA is the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers and data formats among other things; the microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is represented as diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be anything from single gates and registers, to complete arithmetic logic units and larger elements; these diagrams separate the datapath and the control path.
The person designing a system draws the specific microarchitecture as a kind of data flow diagram. Like a block diagram, the microarchitecture diagram shows microarchitectural elements such as the arithmetic and logic unit and the register file as a single schematic symbol; the diagram connects those elements with arrows, thick lines and thin lines to distinguish between three-state buses, unidirectional buses, individual control lines. Simple computers have a single data bus organization – they have a single three-state bus; the diagram of more complex computers shows multiple three-state buses, which help the machine do more operations simultaneously. Each microarchitectural element is in turn represented by a schematic describing the interconnections of logic gates used to implement it; each logic gate is in turn represented by a circuit diagram describing the connections of the transistors used to implement it in some particular logic family. Machines with different microarchitectures may have the same instruction set architecture, thus be capable of executing the same programs.
New microarchitectures and/or circuitry solutions, along with advances in semiconductor manufacturing, are what allows newer generations of processors to achieve higher performance while using the same ISA. In principle, a single microarchitecture could execute several different ISAs with only minor changes to the microcode; the pipelined datapath is the most used datapath design in microarchitecture today. This technique is used in most modern microprocessors, DSPs; the pipelined architecture allows multiple instructions to overlap in execution, much like an assembly line. The pipeline includes several different stages; some of these stages include instruction fetch, instruction decode and write back. Some architectures include other stages such as memory access; the design of pipelines is one of the central microarchitectural tasks. Execution units are essential to microarchitecture. Execution units include arithmetic logic units, floating point units, load/store units, branch prediction, SIMD.
These units perform the calculations of the processor. The choice of the number of execution units, their latency and throughput is a central microarchitectural design task; the size, latency and connectivity of memories within the system are microarchitectural decisions. System-level design decisions such as whether or not to include peripherals, such as memory controllers, can be considered part of the microarchitectural design process; this includes decisions on the connectivity of these peripherals. Unlike architectural design, where achieving a specific performance level is the main goal, microarchitectural design pays closer attention to other constraints. Since microarchitecture design decisions directly affect what goes into a system, attention must be paid to issues such as chip area/cost, power consumption, logic complexity, ease of connectivity, manufacturability, ease of debugging, testability. In general, all CPUs, single-chip microprocessors or multi-chip implementations run programs by performing the following steps: Read an instruction and decode it Find any associated data, needed to process the instruction Process the instruction Write the results outThe instruction cycle is repeated continuously until the power is turned off.
Complicating this simple-looking series of steps is the fact that the memory hierarchy, which includes caching, main memory and non-volatile storage like hard disks, has always been slower than the processor itself. Step introduces a lengthy delay while the data arrives over the computer bus. A considerable amount of research has been put into designs that avoid these delays as much as possible. Over the years, a central goal was to execute more instructions in parallel, thus increasing the effective execution speed of a program; these efforts introduced complicated circuit structures. These techniques could only be implemented on expensive mainframes or supercomputers due to the amount of circuitry needed for these techniques; as semiconductor manufacturing progressed and more of these techniq
The Pentium II brand refers to Intel's sixth-generation microarchitecture and x86-compatible microprocessors introduced on May 7, 1997. Containing 7.5 million transistors, the Pentium II featured an improved version of the first P6-generation core of the Pentium Pro, which contained 5.5 million transistors. However, its L2 cache subsystem was a downgrade. In 1998, Intel stratified the Pentium II family by releasing the Pentium II-based Celeron line of processors for low-end workstations and the Pentium II Xeon line for servers and high-end workstations; the Celeron was characterized by a reduced or omitted on-die full-speed L2 cache and a 66 MT/s FSB. The Xeon was characterized by a range of full-speed L2 cache, a 100 MT/s FSB, a different physical interface, support for symmetric multiprocessing. In February 1999, the Pentium II was replaced by the nearly identical Pentium III, which only added the new SSE instruction set; the Pentium II microprocessor was based upon the microarchitecture of its predecessor, the Pentium Pro, but with some significant improvements.
Unlike previous Pentium and Pentium Pro processors, the Pentium II CPU was packaged in a slot-based module rather than a CPU socket. The processor and associated components were carried on a daughterboard similar to a typical expansion board within a plastic cartridge. A fixed or removable heatsink was carried on one side; this larger package was a compromise allowing Intel to separate the secondary cache from the processor while still keeping it on a coupled back-side bus. The L2 cache ran at half the processor's clock frequency, unlike the Pentium Pro, whose off die L2 cache ran at the same frequency as the processor. However, its associativity was increased to 16-way and its size was always 512 KB, twice of the smallest option of 256 KB on the Pentium Pro. Off-package cache solved the Pentium Pro's low yield issues, allowing Intel to introduce the Pentium II at a mainstream price level. Intel improved 16-bit code execution performance on the Pentium II, an area in which the Pentium Pro was at a notable handicap, by adding segment register caches.
Most consumer software of the day was still using at least some 16-bit code, because of a variety of factors. The issues with partial registers was addressed by adding an internal flag to skip pipeline flushes whenever possible. To compensate for the slower L2 cache, the Pentium II featured 32 KB of L1 cache, double that of the Pentium Pro, as well as 4 write buffers; the Pentium II was the first P6-based CPU to implement the Intel MMX integer SIMD instruction set, introduced on the Pentium MMX. The Pentium II was a more consumer-oriented version of the Pentium Pro, it was cheaper to manufacture because of the separate, slower L2 cache memory. The improved 16-bit performance and MMX support made it a better choice for consumer-level operating systems, such as Windows 9x, multimedia applications; the slower and cheaper L2 cache's performance penalty was mitigated by the doubled L1 cache and architectural improvements for legacy code. General processor performance was increased. All Klamath and some early Deschutes Pentium IIs use a combined L2 cache controller / tag RAM chip that only allows for 512 MB to be cached.
While this limit was irrelevant for the average home user at the time, it was a concern for some workstation or server users. Intel put this limitation deliberately in place to distinguish the Pentium II from the more upmarket Pentium Pro line, which has a full 4 GB cacheable area. The'82459AD' revision of the chip on some 333 MHz and all 350 MHz and faster Pentium IIs lifted this restriction and offered a full 4 GB cacheable area; the original Klamath Pentium II microprocessor ran at 233, 266, 300 MHz and were produced in a 0.35 µm process. The 300 MHz version, only became available in quantities in 1997; these CPUs had a 66 MHz front side bus and were used on motherboards equipped with the aging Intel 440FX Natoma chipset designed for the Pentium Pro. Pentium II-based systems using the Intel 440LX Balboa chipset popularized SDRAM, the AGP graphics bus. On July 14, 1997, Intel announced a version of the Pentium II Klamath with 2× 72-bit ECC L2 cache for entry-level servers, as opposed to the 2× 64-bit non-ECC L2 cache on regular models.
The extra bits give it error-correction capability built into hardware, without impacting performance. The variant can be determined through the CPU part number. In Intel's "Family/Model/Stepping" scheme, Klamath CPUs are family 6, model 3; the Deschutes core Pentium II, which debuted at 333 MHz in January 1998, was produced with a 0.25 µm process and has a lower power draw. The die size is 113 mm2; the 333 MHz variant was the final Pentium CPU. In 1998, Pentium IIs running at 266, 300, 350, 400, 450 MHz were released; the Deschutes core introduced FXRSTOR instructions for fast FPU context save and restore. Towards the end of its design life, Deschutes chips capable of 500 MHz within Intel cooling and design specifications were produced. However, these were not marketed. Rather than destroy alre
Haswell is the codename for a processor microarchitecture developed by Intel as the "fourth-generation core" successor to the Ivy Bridge microarchitecture. Intel announced CPUs based on this microarchitecture on June 4, 2013, at Computex Taipei 2013, while a working Haswell chip was demonstrated at the 2011 Intel Developer Forum. With Haswell, which uses a 22 nm process, Intel introduced low-power processors designed for convertible or "hybrid" ultrabooks, designated by the "Y" suffix. Haswell CPUs are used in conjunction with the Intel 8 Series chipsets, Intel 9 Series chipsets, Intel C220 series chipsets; the Haswell architecture is designed to optimize the power savings and performance benefits from the move to FinFET transistors on the improved 22 nm process node. Haswell has been launched in three major forms: Desktop version: Haswell-DT Mobile/Laptop version: Haswell-MB BGA version: 47 W and 57 W TDP classes: Haswell-H 13.5 W and 15 W TDP classes: Haswell-ULT 10 W TDP class: Haswell-ULX ULT = Ultra Low TDP.
All other models have GT1 integrated graphics. See Intel HD and Iris Graphics for more details. Due to the low power requirements of tablet and UltraBook platforms, Haswell-ULT and Haswell-ULX are only available in dual-core configurations. All other versions come as dual- or quad-core variants. Compared to Ivy Bridge: Approximately 8% faster vector processing Up to 5% faster single-threaded performance 6% faster multi-threaded performance Desktop variants of Haswell draw between 8% and 23% more power under load than Ivy Bridge. A 6% increase in sequential CPU performance Up to 20% performance increase over the integrated HD4000 GPU Total performance improvement on average is about 3% Around 15 °C hotter than Ivy Bridge, while clock frequencies of over 4.6 GHz are achievable 22 nm manufacturing process 3D Tri-Gate FinFET transistors Micro-operation cache capable of storing 1.5 K micro-operations 14- to 19-stage instruction pipeline, depending on the micro-operation cache hit or miss Mainstream variants are up to quad-core.
Native support for dual-channel DDR3/DDR3L memory, with up to 32 GB of RAM on LGA 1150 variants 64 KB L1 cache and 256 KB L2 cache per core A total of 16 PCI Express 3.0 lanes on LGA 1150 variants Wider core: fourth arithmetic logic unit, third address generation unit, second branch execution unit, deeper buffers, higher cache bandwidth, improved front-end and memory controller, higher load/store bandwidth. New instructions; the instruction decode queue, which holds instructions after they have been decoded, is no longer statically partitioned between the two threads that each core can service. New sockets and chipsets: LGA 1150 for desktops, rPGA947 and BGA1364 for the mobile market. Z97 and H97 chipsets for the Haswell Refresh and Broadwell, in Q2 2014. LGA 2011-v3 with X99 chipset for the enthusiast-class desktop platform Haswell-E. Intel Transactional Synchronization Extensions for the Haswell-EX variant. In August 2014 Intel announced that a bug exists in the TSX implementation on the current steppings of Haswell, Haswell-E, Haswell-EP and early Broadwell CPUs, which resulted in disabling the TSX feature on affected CPUs via a microcode update.
Hardware graphics support for Direct3D 11.1 and OpenGL 4.3. Intel 10.18.14.5057 driver is the last planned driver release on Windows 7/8.1. DDR4 for the enthusiast and enterprise/server segments and for the Enthusiast-Class Desktop Platform Haswell-E Variable Base clock like LGA 2011. Four versions of the integrated GPU: GT1, GT2, GT3 and GT3e, where GT3 version has 40 execution units. Haswell's predecessor, Ivy Bridge, has a maximum of 16 EUs. GT3e version with 40 EUs and on-package 128 MB of embedded DRAM, called Crystalwell, is available only in mobile H-SKUs and desktop R-SKUs; this eDRAM is a Level 4 cache. Optional support for Thunderbolt technology and Thunderbolt 2.0 Fully integrated voltage regulator, thereby moving some of the components from motherboard onto the CPU. New advanced power-saving system. 37, 47, 57 W thermal design power mobile processors. 35, 45, 65, 84, 88, 95 and 130–140 W TDP desktop processors. 15 W or 11.5W TDP processors for the Ultrabook platform leading to reduced heat, which results in thinner as well as lighter Ultrabooks, but the performance level is lower than the 17 W version.
Shrink of the Platform Controller Hub, from 65 nm to 32 nm. Haswell-EP variant, released in September 2014, with up to 18 cores and marketed as the Xeon E5-1600 v3 and Xeon E5-2600 v3 series. Haswell-EX variant, released in May 2015, with 18 cores and functioning T
Bonnell is a CPU microarchitecture used by Intel Atom processors which can execute up to two instructions per cycle. Like many other x86 microprocessors, it translates x86 instructions into simpler internal operations prior to execution; the majority of instructions produce one micro-op when translated, with around 4% of instructions used in typical programs producing multiple micro-ops. The number of instructions that produce more than one micro-op is fewer than the P6 and NetBurst microarchitectures. In the Bonnell microarchitecture, internal micro-ops can contain both a memory load and a memory store in connection with an ALU operation, thus being more similar to the x86 level and more powerful than the micro-ops used in previous designs; this enables good performance with only two integer ALUs, without any instruction reordering, speculative execution or register renaming. A side effect of having no speculative execution is invulnerability against Spectre; the Bonnell microarchitecture therefore represents a partial revival of the principles used in earlier Intel designs such as P5 and the i486, with the sole purpose of enhancing the performance per watt ratio.
However, Hyper-Threading is implemented in an easy way to employ the whole pipeline efficiently by avoiding the typical single thread dependencies. On 2 March 2008, Intel announced a new single-core Atom Z5xx series processor, to be used in ultra-mobile PCs and mobile Internet devices, which will supersede Stealey; the processor has 47 million transistors on a 25 mm2 die, allowing for economical production. An Atom Z500 processor's dual-thread performance is equivalent to its predecessor Stealey, but should outperform it on applications that can use simultaneous multithreading and SSE3, they run from 0.8 to 2.0 GHz and have a TDP rating between 0.65 and 2.4 W that can dip down to 0.01 W when idle. They feature 32 KB instruction L1 and 24 KB data L1 caches, 512 KB L2 cache and a 533 MT/s front-side bus; the processors are manufactured in 45 nm process. On 2 March 2008, Intel announced lower-power variants of the Diamondville CPU named Atom N2xx, it was intended for use in nettops and the Classmate PC.
Like their predecessors, these are single-core CPUs with Hyper-Threading. The N270 has a TDP rating of 2.5 W, runs at 1.6 GHz and has a 533 MHz FSB. The N280 has a clock speed of 1.66 GHz and a 667 MHz FSB. On 22 September 2008, Intel announced a new 64-bit dual-core processor branded Atom 330, to be used in desktop computers, it runs at 1.6 GHz and has a FSB speed of 533 MHz and a TDP rating of 8 W. Its dual core consists of two Diamondville dies on a single substrate. During 2009, Nvidia used the Atom 300 and their GeForce 9400M chipset on a mini-ITX form factor motherboard for their Ion platform. Although the Atom processor itself is low-power for an x86 microprocessor, many chipsets used with it dissipate more power. For example, while the Atom N270 used in netbooks through mid-2010 has a TDP rating of 2.5 W, an Intel Atom platform that uses the 945GSE Express chipset has a specified maximum TDP of 11.8 W, with the processor responsible for a small portion of the total power dissipated. Individual figures are 2.5 W for the N270 processor, 6 W for the 945GSE chipset and 3.3 W for the 82801GBM I/O controller.
Intel provides a US15W System Controller Hub-based chipset with a combined TDP of less than 5 W together with the Atom Z5xx series processors, to be used in ultra-mobile PCs and MIDs, though some manufacturers have released ultra-thin systems running these processors. All Atom motherboards on the consumer market featured the Intel 945GC chipset, which uses 22 watts by itself; as of early 2009, only a few manufacturers are offering lower-power motherboards with a 945GSE or US15W chipset and an Atom N270, N280 or Z5xx series CPU. On 21 December 2009, Intel announced the D510 and D410 CPUs with integrated graphics; the new manufacturing process resulted in a 20% reduction in power consumption and a 60% smaller die size. The Intel GMA 3150, a 45 nm shrink of the GMA 3100 with no HD capabilities, is included as the on-die GPU. Netbooks using this new processor were released on 11 January 2010; the major new feature is longer battery life. This generation of the Atom was codenamed Pineview, used in the Pine Trail platform.
Intel's Pine Trail-M platform utilizes Platform Controller Hub. The graphics and memory controller have moved into the processor, paired with the Tiger Point PCH; this creates a more power-efficient 2-chip platform rather than the 3-chip one used with previous-generation Atom chipsets. On 1 March 2010 Intel introduced the N470 processor, running at 1.83 GHz with a 667 MHz FSB and a TDP rating of 6.5 W. The new Atom N4xx chips became available on 11 January 2010, it is used in netbook and nettop systems and includes an integrated single-channel DDR2 memory controller and an integrated graphics core. It features Hyper-Threading and is manufactured on a 45 nm process; the new design uses half the power of the older Menlow platform. This reduced overall power consumption and size makes the platform more desirable for use in smartphones and other mobile internet devices; the D4xx and D5xx series support DDR2-800 memory. They are rated for embedded use; the series has an integrated graphics processor built directly into the CPU to help improve performanc