ESi-RISC is a configurable CPU architecture from Ensilica. It is available in five implementations: the eSi-1600, eSi-1650, eSi-3200, eSi-3250 and eSi-3260; the eSi-1600 and eSi-1650 feature a 16-bit data-path. Each of these processors is licensed as soft IP cores, suitable for integrating into both ASICs and FPGAs; the main features of the eSi-RISC architecture are: RISC-like load/store architecture. Configurable 16 or 32-bit data-path. Instructions are encoded in either 32-bits. 8, 16 or 32 general purpose registers, that are either 16 or 32-bits wide. 0, 8, 16 or 32 vector registers, that are either 32 or 64-bits wide. Up to 32 external interrupts. Configurable instruction set including support for integer, floating-point and fixed-point arithmetic. SIMD operations. Optional support for user-defined instructions, such as cryptographic acceleration. Optional caches. Optional MMU supporting both memory protection and dynamic address translation. AMBA AXI, AHB and APB bus interfaces. Memory mapped I/O.
5-stage pipeline. Hardware JTAG debug. While there are many different 16 or 32-bit Soft microprocessor IP cores available, eSi-RISC is the only architecture licensed as an IP core that has both 16 and 32-bit implementations. Unlike in other RISC architectures supporting both 16 and 32-bit instructions, such as ARM/Thumb or MIPS/MIPS-16, 16 and 32-bit instructions in the eSi-RISC architecture can be intermixed, rather than having different modes where either all 16-bit instructions or all 32-bit instructions are executed; this improves code density without compromising performance. The 16-bit instructions support two register operands in the lower 16 registers, whereas the 32-bit instructions support three register operands and access to all 32 registers. ESi-RISC includes support for Multiprocessing. Implementations have included up to seven eSi-3250's on a single chip; the eSi-RISC toolchain is based on combination of a port of the GNU toolchain and the Eclipse IDE. This includes: GCC – C/C++ compiler.
Binutils – Assembler and binary utilities. GDB – Debugger. Eclipse – Integrated Development Environment; the C library is Newlib and the C++ library is Libstdc++. Ported RTOSes include MicroC/OS-II, FreeRTOS, ERIKA Enterprise and Phoenix-RTOS EnSilica's eSi-RISC homepage
Renesas Electronics Corporation TYO: 6723 is a Japanese semiconductor manufacturer headquartered in Tokyo. It has manufacturing and sales operations in around 20 countries, it was the world's largest auto semiconductor maker in 2014, the world's largest maker of microcontrollers. It makes mixed-signal integrated circuits and system on a chip. "Renesas" is a contraction of RENaissance SEmiconductor for Advanced Solutions. Renesas Electronics started operation in April 2010, through the integration of NEC Electronics Corporation and Renesas Technology Corporation. NEC Electronics was established in November 2002 by a spin-off of the semiconductor operations of NEC. Renesas Technology was established on April 1, 2003, as a joint venture of Hitachi, Ltd. and Mitsubishi Electric. In April 2009, Renesas Technology and NEC Electronics reached a basic agreement to merge by around April 2010. On April 1, 2010 NEC Electronics and Renesas Technology merged, forming Renesas Electronics which became the fourth largest semiconductor company according to iSuppli published data.
In December 2010 Renesas Mobile Corporation was created by integrating the Mobile Multimedia Business Unit of Renesas with the acquired Nokia Wireless Modem Business Unit. In 2011, Renesas Electronics was adversely affected by the 2011 Tōhoku earthquake and tsunami and flooding in Thailand. In 2012, the company decided to restructure its business, including the sale and consolidation of its Japanese domestic plants, to get profitable. In December 2012, INCJ, Japan’s government-backed fund, several key clients decided to invest in the company. Through the investment, Renesas aimed to secure 150 billion yen as fresh capital by September 2013 and use it for realizing the Smart Society through investment in the microcontroller and Analog & Power semiconductor development, plant improvements and industrial semiconductor solutions and corporate acquisitions. In September 2013, Broadcom Corporation acquired most of Renesas Mobile Communication. With the allotment of third-party shares to Innovation Network Corporation of Japan and 8 other companies in September 2013, Innovation Network Corporation of Japan became the largest shareholder.
In the fiscal year ending March 2014, Renesas records its first net profit since it operated as Renesas Electronics Corporation in 2010. To achieve a profit-generating corporate structure, Renesas announced its new business direction and issued its corporate presentation titled "Reforming Renesas” in October 2013. In September 2016, Renesas announced. Renesas presented its Mid-Term Growth Strategy in November, 2016. In February 2017, Renesas completed the acquisition of Intersil Corporation. In April 2017, Renesas unveiled in a self-driving demo car at a global developer conference that it will start delivering a new line of products for self-driving cars in December 2017 as it takes on global giants such as Intel Corp; the new technology acts as an onboard nerve center and controlling vehicle functions. In September 2018, Renesas announced; the deal is expected to close in the first half of 2019. In March 2019, Renesas completed the acquisition of IDT. Renesas Electronics' products include: Microcontrollers/microprocessors System LSIs ASICs Logic ICs Analog ICs ASSP Discrete devices Memory ICs The largest stockholders and their ownership ratio of Renesas are as follows as of December 31, 2018.
At the end of September 2013, Renesas issued new shares through third-party allotment resulting in Innovation Network Corporation of Japan becoming the new largest shareholder and non-parental controlling shareholder. In early May 2012, NEC transferred part of its stake in Renesas to its employee pension trust; as a result, the NEC pension fund held 32.4 percent of Renesas. Official website
The Power ISA is an instruction set architecture developed by the OpenPOWER Foundation, led by IBM. It was developed by the defunct Power.org industry group. Power ISA is an evolution of the PowerPC ISA, created by the mergers of the core PowerPC ISA and the optional Book E for embedded applications; the merger of these two components in 2006 was led by Power.org founders IBM and Freescale Semiconductor. The ISA is divided into several categories and every component is defined as a part of a category. Processors implement a set of these categories. Different classes of processors are required to implement certain categories, for example a server class processor includes the categories Base, Floating-Point, 64-Bit, etc. All processors implement the Base category; the Power ISA is a RISC load/store architecture. It has multiple sets of registers: thirty-two 32-bit or 64-bit general purpose registers for integer operations. Sixty-four 128-bit vector scalar registers for floating point operations. Thirty-two 64-bit floating-point registers as part of the VSRs for floating point operations.
Thirty-two 128-bit vector registers as part of the VSRs for vector operations. Eight 4-bit condition register fields for control flow. Special registers: counter register, link register, time base, alternate time base, status registers. Instructions have a length of 32 bits, with the exception of the VLE subset that provides for higher code density for low-end embedded applications. Most instructions are triadic, i.e. have one destination. Single and double precision IEEE-754 compliant floating point operations are supported, including additional fused multiply–add and decimal floating-point instructions. There are provisions for SIMD operations on integer and floating point data on up to 16 elements in a single instruction. Support for Harvard cache, i.e. split data and instruction caches, as well as support for unified caches. Memory operations are load/store, but allow for out-of-order execution. Support for both big and little-endian addressing with separate categories for moded and per-page endianness.
Support for both 32-bit and 64-bit addressing. Different modes of operation include user and hypervisor. Base – Most of Book I and Book II Server – Book III-S Embedded – Book III-E Misc – floating point, signal processing, cache locking, decimal floating point, etc; the Power ISA specification is divided into five parts, called "books": Book I – User Instruction Set Architecture covers the base instruction set available to the application programmer. Memory reference, flow control, floating point, numeric acceleration, application-level programming, it includes chapters regarding auxiliary processing units like the AltiVec extension. Book II – Virtual Environment Architecture defines the storage model available to the application programmer, including timing, cache management, storage features, byte ordering. Book III – Operating Environment Architecture includes exceptions, memory management, debug facilities and special control functions. It's divided into two parts. Book III-S – Defines the supervisor instructions used for general purpose/server implementations.
It is the contents of the Book III of the former PowerPC ISA. Book III-E – Defines the supervisor instructions used for embedded applications, it is derived from the former PowerPC Book E. Book VLE – Variable Length Encoded Instruction Architecture defines alternative instructions and definitions from Book I-III, intended for higher instruction density and very-low-end applications, they use big endian byte ordering. The specification for Power ISA v.2.03 is based on the former PowerPC ISA v.2.02 in POWER5+ and the Book E extension of the PowerPC specification. The Book I included five new chapters regarding auxiliary processing units like DSPs and the AltiVec extension. Compliant cores Freescale PowerPC e200, e500 IBM PowerPC 405, 440, 460, 970, POWER5 and POWER6 IBM Cell PPE The specification for Power ISA v.2.04 was finalized in June 2007. It is based on Power ISA v.2.03 and includes changes to the Book III-S part regarding virtualization, hypervisor functionality, logical partitioning and virtual page handling.
Compliant cores All cores that comply with previous versions of the Power ISA The PA6T core from P. A. Semi Titan from AMCC The specification for Power ISA v.2.05 was released in December 2007. It is based on Power ISA v.2.04 and includes changes to Book I and Book III-S, including significant enhancements such as decimal arithmetic and server hypervisor improvements. Compliant cores All cores that comply with previous versions of the Power ISA POWER6 PowerPC 476 The specification for Power ISA v.2.06 was released in February 2009, revised in July 2010. It includes extensions for the POWER7 processor and e500-mc core. One significant new feature is vector-scalar floating-point instructions. Book III-E includes significant enhancement for the embedded specification regarding hypervisor and virtualisation on single and multi core implementations; the spec was revised in November 2010 to the Power ISA v.2.06 revision B spec, enhancing virtualization features."Power ISA 2.06 Rev. B enables full hardware virtualization for embedded space".
EETimes. 2010-11-03. Retrieved 2011-06-08.</ref> Compliant cores All cores that comply with previous versions of the Power ISA POWER7 A2 e500-mc e5500 The specification for Power ISA v.2.07 was released in May 20
An embedded system is a controller programmed and controlled by a real-time operating system with a dedicated function within a larger mechanical or electrical system with real-time computing constraints. It is embedded as part of a complete device including hardware and mechanical parts. Embedded systems control many devices in common use today. Ninety-eight percent of all microprocessors manufactured are used in embedded systems. Examples of properties of typical embedded computers when compared with general-purpose counterparts are low power consumption, small size, rugged operating ranges, low per-unit cost; this comes at the price of limited processing resources, which make them more difficult to program and to interact with. However, by building intelligence mechanisms on top of the hardware, taking advantage of possible existing sensors and the existence of a network of embedded units, one can both optimally manage available resources at the unit and network levels as well as provide augmented functions, well beyond those available.
For example, intelligent techniques can be designed to manage power consumption of embedded systems. Modern embedded systems are based on microcontrollers, but ordinary microprocessors are common in more complex systems. In either case, the processor used may be types ranging from general purpose to those specialized in certain class of computations, or custom designed for the application at hand. A common standard class of dedicated processors is the digital signal processor. Since the embedded system is dedicated to specific tasks, design engineers can optimize it to reduce the size and cost of the product and increase the reliability and performance; some embedded systems are mass-produced. Embedded systems range from portable devices such as digital watches and MP3 players, to large stationary installations like traffic lights, factory controllers, complex systems like hybrid vehicles, MRI, avionics. Complexity varies from low, with a single microcontroller chip, to high with multiple units and networks mounted inside a large chassis or enclosure.
One of the first recognizably modern embedded systems was the Apollo Guidance Computer, developed ca. 1965 by Charles Stark Draper at the MIT Instrumentation Laboratory. At the project's inception, the Apollo guidance computer was considered the riskiest item in the Apollo project as it employed the newly developed monolithic integrated circuits to reduce the size and weight. An early mass-produced embedded system was the Autonetics D-17 guidance computer for the Minuteman missile, released in 1961; when the Minuteman II went into production in 1966, the D-17 was replaced with a new computer, the first high-volume use of integrated circuits. Since these early applications in the 1960s, embedded systems have come down in price and there has been a dramatic rise in processing power and functionality. An early microprocessor for example, the Intel 4004, was designed for calculators and other small systems but still required external memory and support chips. In 1978 National Engineering Manufacturers Association released a "standard" for programmable microcontrollers, including any computer-based controllers, such as single board computers and event-based controllers.
As the cost of microprocessors and microcontrollers fell it became feasible to replace expensive knob-based analog components such as potentiometers and variable capacitors with up/down buttons or knobs read out by a microprocessor in consumer products. By the early 1980s, memory and output system components had been integrated into the same chip as the processor forming a microcontroller. Microcontrollers find applications. A comparatively low-cost microcontroller may be programmed to fulfill the same role as a large number of separate components. Although in this context an embedded system is more complex than a traditional solution, most of the complexity is contained within the microcontroller itself. Few additional components may be needed and most of the design effort is in the software. Software prototype and test can be quicker compared with the design and construction of a new circuit not using an embedded processor. Embedded systems are found in consumer, automotive, medical and military applications.
Telecommunications systems employ numerous embedded systems from telephone switches for the network to cell phones at the end user. Computer networking uses dedicated routers and network bridges to route data. Consumer electronics include MP3 players, mobile phones, video game consoles, digital cameras, GPS receivers, printers. Household appliances, such as microwave ovens, washing machines and dishwashers, include embedded systems to provide flexibility and features. Advanced HVAC systems use networked thermostats to more and efficiently control temperature that can change by time of day and season. Home automation uses wired- and wireless-networking that can be used to control lights, security, audio/visual, etc. all of which use embedded devices for sensing and controlling. Transportation systems from flight to automobiles use embedded systems. New airplanes contain advanced avionics such as inertial guidance systems and GPS receivers that have considerable safety requirements. Various electric motors — brushless DC motors, induction motors and DC motors — use electric/electronic motor controllers.
Automobiles, electric vehicles, hy
A microcontroller is a small computer on a single integrated circuit. In modern terminology, it is less sophisticated than, a system on a chip. A microcontroller contains one or more CPUs along with memory and programmable input/output peripherals. Program memory in the form of ferroelectric RAM, NOR flash or OTP ROM is often included on chip, as well as a small amount of RAM. Microcontrollers are designed for embedded applications, in contrast to the microprocessors used in personal computers or other general purpose applications consisting of various discrete chips. Microcontrollers are used in automatically controlled products and devices, such as automobile engine control systems, implantable medical devices, remote controls, office machines, power tools and other embedded systems. By reducing the size and cost compared to a design that uses a separate microprocessor and input/output devices, microcontrollers make it economical to digitally control more devices and processes. Mixed signal microcontrollers are common, integrating analog components needed to control non-digital electronic systems.
In the context of the internet of things, microcontrollers are an economical and popular means of data collection and actuating the physical world as edge devices. Some microcontrollers may use four-bit words and operate at frequencies as low as 4 kHz, for low power consumption, they have the ability to retain functionality while waiting for an event such as a button press or other interrupt. Other microcontrollers may serve performance-critical roles, where they may need to act more like a digital signal processor, with higher clock speeds and power consumption; the first microprocessor is claimed to be the 4-bit Intel 4004 released in 1972. It was followed by the 4-bit 4040, the 8-bit Intel 8008, the 8-bit Intel 8080. All of these processors required several external chips to implement a working system, including memory and peripheral interface chips; as a result, the total system cost was several hundred dollars, making it impossible to economically computerize small appliances. MOS Technology introduced sub-$100 microprocessors, the 6501 and 6502, with the chief aim of addressing this economic obstacle, but these microprocessors still required external support and peripheral chips which kept the total system cost in the $100s of dollars.
One book credits TI engineers Gary Boone and Michael Cochran with the successful creation of the first microcontroller in 1971. The result of their work was the TMS 1000, which became commercially available in 1974, it combined read-only memory, read/write memory and clock on one chip and was targeted at embedded systems. In response to the existence of the single-chip TMS 1000, Intel developed a computer system on a chip optimized for control applications, the Intel 8048, with commercial parts first shipping in 1977, it combined ROM with on the same chip with a microprocessor. Among numerous applications, this chip would find its way into over one billion PC keyboards. At that time Intel's President, Luke J. Valenter, stated that the microcontroller was one of the most successful products in the company's history, he expanded the microcontroller division's budget by over 25%. Most microcontrollers at this time had concurrent variants. One had EPROM program memory, with a transparent quartz window in the lid of the package to allow it to be erased by exposure to ultraviolet light.
These erasable chips were used for prototyping. The other variant was either a mask programmed ROM or a PROM variant, only programmable once. For the latter, sometimes the designation OTP was used, standing for "one-time programmable". In an OTP microcontroller, the PROM was of identical type as the EPROM, but the chip package had no quartz window; because the erasable versions required ceramic packages with quartz windows, they were more expensive than the OTP versions, which could be made in lower-cost opaque plastic packages. For the erasable variants, quartz was required, instead of less expensive glass, for its transparency to ultraviolet light—to which glass is opaque—but the main cost differentiator was the ceramic package itself. In 1993, the introduction of EEPROM memory allowed microcontrollers to be electrically erased without an expensive package as required for EPROM, allowing both rapid prototyping, in-system programming; the same year, Atmel introduced the first microcontroller using Flash memory, a special type of EEPROM.
Other companies followed suit, with both memory types. Nowadays microcontrollers are cheap and available for hobbyists, with large online communities around certain processors. On 21 June the "world's smallest computer" was announced by the University of Michigan; the device is a "0.04mm3 16nW wireless and batteryless sensor system with integrated Cortex-M0+ processor and optical communication for cellular temperature measurement." It "measures just 0.3 mm to a side—dwarfed by a grain of rice. In addition to the RAM and photovoltaics, the new computing de
SuperH is a 32-bit reduced instruction set computing instruction set architecture developed by Hitachi and produced by Renesas. It is implemented by microprocessors for embedded systems; as of 2015, many of the original patents for the SuperH architecture are expiring and the SH2 CPU has been reimplemented as open source hardware under the name J2. The SuperH processor core family was first developed by Hitachi in the early 1990s. Hitachi has developed a complete group of upward compatible instruction set CPU cores; the SH-1 and the SH-2 were used in the Sega Saturn and Sega 32X. These cores have 16-bit instructions for better code density than 32-bit instructions, a great benefit at the time, due to the high cost of main memory. A few years the SH-3 core was added to the SH CPU family; the SH-3 core got a DSP extension called SH-3-DSP. With extended data paths for efficient DSP processing, special accumulators and a dedicated MAC-type DSP engine, this core was unifying the DSP and the RISC processor world.
A derivative was used with the original SH-2 core. Between 1994 and 1996, 35.1 million SuperH devices were shipped worldwide. For the Dreamcast, Hitachi developed the SH-4 architecture. Superscalar instruction execution and a vector floating point unit were the highlights of this architecture. SH-4 based standard chips were introduced around 1998; the SH-3 and SH-4 architectures support both big-endian and little-endian byte ordering. Hitachi and STMicroelectronics started collaborating as early as 1997 on the design of the SH-4. In early 2001, they formed the IP company SuperH, Inc., going to license the SH-4 core to other companies and was developing the SH-5 architecture, the first move of SuperH into the 64-bit area. In 2003, Hitachi and Mitsubishi Electric formed a joint-venture called Renesas Technology, with Hitachi controlling 55% of it. In 2004, Renesas Technology bought STMicroelectronics's share of ownership in the SuperH Inc. and with it the licence to the SH cores. Renesas Technology became Renesas Electronics, following their merger with NEC Electronics.
The SH-5 design supported two modes of operation. SHcompact mode is equivalent to the user-mode instructions of the SH-4 instruction set. SHmedia mode is different, using 32-bit instructions with sixty-four 64-bit integer registers and SIMD instructions. In SHmedia mode the destination of a branch is loaded into a branch register separately from the actual branch instruction; this allows the processor to prefetch instructions for a branch without having to snoop the instruction stream. The combination of a compact 16-bit instruction encoding with a more powerful 32-bit instruction encoding is not unique to SH-5. However, SH-5 differs because its backward compatibility mode is the 16-bit encoding rather than the 32-bit encoding; the evolution of the SuperH architecture still continues. The latest evolutionary step happened around 2003 where the cores from SH-2 up to SH-4 were getting unified into a superscalar SH-X core which forms a kind of instruction set superset of the previous architectures.
Today, the SuperH CPU cores and products are with Renesas Electronics, a merger of the Hitachi and Mitsubishi semiconductor groups and the architecture is consolidated around the SH-2, SH-2A, SH-3, SH-4 and SH-4A platforms giving a scalable family. The last of the SH-2 patents expired in 2014. At LinuxCon Japan 2015, j-core developers presented a cleanroom reimplemention of the SH-2 ISA with extensions. Subsequently, a design walkthrough was presented at ELC 2016; the open source BSD licensed VHDL code for the J2 core has been proven on Xilinx FPGAs and on ASICs manufactured on TSMC's 180 nm process, is capable of booting µClinux. J2 is backwards ISA compatible with SH-2, implemented as a 5-stage pipeline with separate Instruction and Data memory interfaces, a machine generated Instruction Decoder supporting the densely packed and complex ISA. Additional instructions are easy to add. J2 implements instructions for dynamic shift, extended atomic operations and locking/interfaces for symmetric multiprocessor support.
Plans to implement the SH-2A and SH-4 instruction sets as the relevant patents expire in 2016-2017. Several features of SuperH have been cited as motivations for designing new cores based on this architecture: High code density compared to other 32-bit RISC ISAs such as ARM or MIPS important for cache and memory bandwidth performance Existing compiler and operating system support Extremely low ASIC fabrication costs now that the patents are expiring. Patent and royalty free implementation Full and vibrant community support Availability of low cost hardware development platform for zero cost FPGA tools CPU and SoC RTL generation and integration tools, producing FPGA and ASIC portable RTL and documentation Clean, modern design with open source design, generation and verification environment The family of SuperH CPU cores includes: SH-1 - used in microcontrollers for embedded applications SH-2 - used in microcontrollers with higher performance requirements used in automotive such as engine control units or in networking app
ARM Advanced RISC Machine Acorn RISC Machine, is a family of reduced instruction set computing architectures for computer processors, configured for various environments. Arm Holdings develops the architecture and licenses it to other companies, who design their own products that implement one of those architectures—including systems-on-chips and systems-on-modules that incorporate memory, radios, etc, it designs cores that implement this instruction set and licenses these designs to a number of companies that incorporate those core designs into their own products. Processors that have a RISC architecture require fewer transistors than those with a complex instruction set computing architecture, which improves cost, power consumption, heat dissipation; these characteristics are desirable for light, battery-powered devices—including smartphones and tablet computers, other embedded systems. For supercomputers, which consume large amounts of electricity, ARM could be a power-efficient solution.
ARM Holdings periodically releases updates to the architecture. Architecture versions ARMv3 to ARMv7 support 32-bit arithmetic; the Thumb version supports a variable-length instruction set that provides both 32- and 16-bit instructions for improved code density. Some older cores can provide hardware execution of Java bytecodes. Released in 2011, the ARMv8-A architecture added support for a 64-bit address space and 64-bit arithmetic with its new 32-bit fixed-length instruction set. With over 100 billion ARM processors produced as of 2017, ARM is the most used instruction set architecture and the instruction set architecture produced in the largest quantity; the used Cortex cores, older "classic" cores, specialized SecurCore cores variants are available for each of these to include or exclude optional capabilities. The British computer manufacturer Acorn Computers first developed the Acorn RISC Machine architecture in the 1980s to use in its personal computers, its first ARM-based products were coprocessor modules for the BBC Micro series of computers.
After the successful BBC Micro computer, Acorn Computers considered how to move on from the simple MOS Technology 6502 processor to address business markets like the one, soon dominated by the IBM PC, launched in 1981. The Acorn Business Computer plan required that a number of second processors be made to work with the BBC Micro platform, but processors such as the Motorola 68000 and National Semiconductor 32016 were considered unsuitable, the 6502 was not powerful enough for a graphics-based user interface. According to Sophie Wilson, all the processors tested at that time performed about the same, with about a 4 Mbit/second bandwidth. After testing all available processors and finding them lacking, Acorn decided it needed a new architecture. Inspired by papers from the Berkeley RISC project, Acorn considered designing its own processor. A visit to the Western Design Center in Phoenix, where the 6502 was being updated by what was a single-person company, showed Acorn engineers Steve Furber and Sophie Wilson they did not need massive resources and state-of-the-art research and development facilities.
Wilson developed the instruction set, writing a simulation of the processor in BBC BASIC that ran on a BBC Micro with a 6502 second processor. This convinced Acorn engineers. Wilson approached Acorn's CEO, Hermann Hauser, requested more resources. Hauser assembled a small team to implement Wilson's model in hardware; the official Acorn RISC Machine project started in October 1983. They chose VLSI Technology as the silicon partner, as they were a source of ROMs and custom chips for Acorn. Wilson and Furber led the design, they implemented it with a similar efficiency ethos as the 6502. A key design goal was achieving low-latency input/output handling like the 6502; the 6502's memory access architecture had let developers produce fast machines without costly direct memory access hardware. The first samples of ARM silicon worked properly when first received and tested on 26 April 1985; the first ARM application was as a second processor for the BBC Micro, where it helped in developing simulation software to finish development of the support chips, sped up the CAD software used in ARM2 development.
Wilson subsequently rewrote BBC BASIC in ARM assembly language. The in-depth knowledge gained from designing the instruction set enabled the code to be dense, making ARM BBC BASIC an good test for any ARM emulator; the original aim of a principally ARM-based computer was achieved in 1987 with the release of the Acorn Archimedes. In 1992, Acorn once more won the Queen's Award for Technology for the ARM; the ARM2 featured 26-bit address space and 27 32-bit registers. Eight bits from the program counter register were available for other purposes; the address bus was extended to 32 bits in the ARM6, but program code still had to lie within the first 64 MB of memory in 26-bit compatibility mode, due to the reserved bits for the status flags. The ARM2 had a transistor count of just 30,000, compared to Motorola's six-year-older 68000 model with around 40,000. Much of this simplicity came from the lack of mic