International Business Machines Corporation is an American multinational information technology company headquartered in Armonk, New York, with operations in over 170 countries. The company began in 1911, founded in Endicott, New York, as the Computing-Tabulating-Recording Company and was renamed "International Business Machines" in 1924. IBM produces and sells computer hardware and software, provides hosting and consulting services in areas ranging from mainframe computers to nanotechnology. IBM is a major research organization, holding the record for most U. S. patents generated by a business for 26 consecutive years. Inventions by IBM include the automated teller machine, the floppy disk, the hard disk drive, the magnetic stripe card, the relational database, the SQL programming language, the UPC barcode, dynamic random-access memory; the IBM mainframe, exemplified by the System/360, was the dominant computing platform during the 1960s and 1970s. IBM has continually shifted business operations by focusing on higher-value, more profitable markets.
This includes spinning off printer manufacturer Lexmark in 1991 and the sale of personal computer and x86-based server businesses to Lenovo, acquiring companies such as PwC Consulting, SPSS, The Weather Company, Red Hat. In 2014, IBM announced that it would go "fabless", continuing to design semiconductors, but offloading manufacturing to GlobalFoundries. Nicknamed Big Blue, IBM is one of 30 companies included in the Dow Jones Industrial Average and one of the world's largest employers, with over 380,000 employees, known as "IBMers". At least 70% of IBMers are based outside the United States, the country with the largest number of IBMers is India. IBM employees have been awarded five Nobel Prizes, six Turing Awards, ten National Medals of Technology and five National Medals of Science. In the 1880s, technologies emerged that would form the core of International Business Machines. Julius E. Pitrap patented the computing scale in 1885. On June 16, 1911, their four companies were amalgamated in New York State by Charles Ranlett Flint forming a fifth company, the Computing-Tabulating-Recording Company based in Endicott, New York.
The five companies had offices and plants in Endicott and Binghamton, New York. C.. They manufactured machinery for sale and lease, ranging from commercial scales and industrial time recorders and cheese slicers, to tabulators and punched cards. Thomas J. Watson, Sr. fired from the National Cash Register Company by John Henry Patterson, called on Flint and, in 1914, was offered a position at CTR. Watson joined CTR as General Manager 11 months was made President when court cases relating to his time at NCR were resolved. Having learned Patterson's pioneering business practices, Watson proceeded to put the stamp of NCR onto CTR's companies, he implemented sales conventions, "generous sales incentives, a focus on customer service, an insistence on well-groomed, dark-suited salesmen and had an evangelical fervor for instilling company pride and loyalty in every worker". His favorite slogan, "THINK", became a mantra for each company's employees. During Watson's first four years, revenues reached $9 million and the company's operations expanded to Europe, South America and Australia.
Watson never liked the clumsy hyphenated name "Computing-Tabulating-Recording Company" and on February 14, 1924 chose to replace it with the more expansive title "International Business Machines". By 1933 most of the subsidiaries had been merged into one company, IBM. In 1937, IBM's tabulating equipment enabled organizations to process unprecedented amounts of data, its clients including the U. S. Government, during its first effort to maintain the employment records for 26 million people pursuant to the Social Security Act, the tracking of persecuted groups by Hitler's Third Reich through the German subsidiary Dehomag. In 1949, Thomas Watson, Sr. created IBM World Trade Corporation, a subsidiary of IBM focused on foreign operations. In 1952, he stepped down after 40 years at the company helm, his son Thomas Watson, Jr. was named president. In 1956, the company demonstrated the first practical example of artificial intelligence when Arthur L. Samuel of IBM's Poughkeepsie, New York, laboratory programmed an IBM 704 not to play checkers but "learn" from its own experience.
In 1957, the FORTRAN scientific programming language was developed. In 1961, IBM developed the SABRE reservation system for American Airlines and introduced the successful Selectric typewriter. In 1963, IBM employees and computers helped. A year it moved its corporate headquarters from New York City to Armonk, New York; the latter half of the 1960s saw IBM continue its support of space exploration, participating in the 1965 Gemini flights, 1966 Saturn flights and 1969 lunar mission. On April 7, 1964, IBM announced the first computer system family, the IBM System/360, it spanned the complete range of commercial and scientific applications from large to small, allowing companies for the first time to upgrade to models with greater computing capability without having to rewrite their applications. It was followed by the IBM System/370 in 1970. Together the
The POWER6 is a microprocessor developed by IBM that implemented the Power ISA v.2.03. When it became available in systems in 2007, it succeeded the POWER5+ as IBM's flagship Power microprocessor, it is claimed to be part of the eCLipz project, said to have a goal of converging IBM's server hardware where practical. POWER6 was described at the International Solid-State Circuits Conference in February 2006, additional details were added at the Microprocessor Forum in October 2006 and at the next ISSCC in February 2007, it was formally announced on May 21, 2007. It was released on June 8, 2007 at speeds of 3.5, 4.2 and 4.7 GHz, but the company has noted prototypes have reached 6 GHz. POWER6 reached first silicon in the middle of 2005, was bumped to 5.0 GHz in May 2008 with the introduction of the P595. The POWER6 is a dual-core processor; each core is capable of two-way simultaneous multithreading. The POWER6 has 790 million transistors and is 341 mm2 large fabricated on a 65 nm process. A notable difference from POWER5 is that the POWER6 executes instructions in-order instead of out-of-order.
This change requires software to be recompiled for optimal performance, but the POWER6 still achieves significant performance improvements over the POWER5+ with unmodified software, according to the lead engineer on the POWER6 project. POWER6 takes advantage of ViVA-2, Virtual Vector Architecture, which enables the combination of several POWER6 nodes to act as a single vector processor; each core has two integer units, two binary floating-point units, an AltiVec unit, a novel decimal floating-point unit. The binary floating-point unit incorporates "many microarchitectures, circuit and integration techniques to achieve 6-cycle, 13-FO4 pipeline", according to a company paper. Unlike the servers from IBM's competitors, the POWER6 has hardware support for IEEE 754 decimal arithmetic and includes the first decimal floating-point unit integrated in silicon. More than 50 new floating point instructions handle the decimal math and conversions between binary and decimal; this feature was added to the z10 microprocessor featured in the System z10.
Each core has a 64 KB, four-way set-associative instruction cache and a 64 KB data cache of an eight-way set-associative design with a two-stage pipeline supporting two independent 32-bit reads or one 64-bit write per cycle. Each core has semi-private 4 MiB unified L2 cache, where the cache is assigned a specific core, but the other has a fast access to it; the two cores share a 32 MiB L3 cache, off die, using an 80 GB/s bus. POWER6 can connect to up to 31 other processors using two inter node links, supports up to 10 logical partitions per core. There is an interface to a service processor that monitors and adjusts performance and power according to set parameters. IBM makes use of a 5 GHz duty-cycle correction clock distribution network for the processor. In the network, the company implements a copper distribution wire, 3 µm wide and 1.2 µm thick. The POWER6 design uses dual power supplies, a logic supply in the 0.8-to-1.2 Volt range and an SRAM power supply at about 150-mV higher. The thermal characteristics of POWER6 are similar to that of the POWER5.
Dr Frank Soltis, an IBM chief scientist, said IBM had solved power leakage problems associated with high frequency by using a combination of 90 nm and 65 nm parts in the POWER6 design. The enhanced POWER6+ was introduced in April 2009, but had been shipping in Power 560 and 570 systems since October 2008, it added more memory keys for secure memory partition, a feature taken from IBM's mainframe processors. As of 2008, the range of POWER6 systems includes Enterprise models; the various system models are designed to serve any sized business. For example, the 520 Express is marketed to small businesses while the Power 595 is marketed for large, multi-environment data centers; the main difference between the Express and Enterprise models is that the latter include Capacity Upgrade on Demand capabilities and hot-pluggable processor and memory "books". IBM offers four POWER6 based blade servers. Specifications are shown in the table below. All blades support AIX, i, Linux; the BladeCenter S and H chassis is supported for blades running AIX, i, Linux.
The BladeCenter E, HT, T chassis support blades running AIX and Linux but not i. At the SuperComputing 2007 conference in Reno a new water-cooled Power 575 was revealed; the 575 is composed of 2U "nodes" each with 32 POWER6 cores at 4.7 GHz with up to 256 GB of RAM. Up to 448 cores can be installed in a single frame. IBM POWER microprocessors POWER7 z10, a mainframe processor sharing much technology with the POWER6. IBM POWER6 Press Kit IBM's Power6 doubles speed "IBM Unleashes World's Fastest Chip in Powerful New Computer". IBM. May 21, 2007. InformationWeek report on the Power6 announcement Real World Tech, Dec 19, 2005 InformationWeek, Feb 6, 2006 C|Net, Oct 10, 2006 Heise Online, Oct 12, 2006 Fall Processor Forum 2006: IBM’s POWER6, Real World Tech, Oct 16, 2006 Arstechnica, Oct 19, 2006 Arstechnica, Feb 12, 2007 Arstechnica, May 21, 2007 POWER Roadmap, IBM, Oct 2006 M. J. Mack. Swaney. "IBM POWER6 Reliability". IBM Journal of Research and Development. 51: 763–774. Doi:10.1147/rd.516.0763. R. Berridge.
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The POWER5 is a microprocessor developed and fabricated by IBM. It is an improved version of the POWER4; the principal improvements are support for simultaneous multithreading and an on-die memory controller. The POWER5 is a dual-core microprocessor, with each core supporting one physical thread and two logical threads, for a total of two physical threads and four logical threads. Technical details of the microprocessor were first presented at the 2003 Hot Chips conference. A more complete description was given at Microprocessor Forum 2003 on 14 October 2003; the POWER5 was not sold and was used by IBM and their partners. Systems using the microprocessor were introduced in 2004; the POWER5 competed in the high-end enterprise server market against the Intel Itanium 2 and to a lesser extent, the Sun Microsystems UltraSPARC IV and the Fujitsu SPARC64 V. It was superseded in 2005 by an improved iteration, the POWER5+; the POWER5 is a further development of the POWER4. The addition of two-way multithreading required the duplication of the return stack, program counter, instruction buffer, group completion unit and store queue so that each thread may have its own.
Most resources, such as the register files and execution units, are shared, although each thread sees its own set of registers. The POWER5 implements simultaneous multithreading; the POWER5 can disable SMT to optimize for the current workload. As many resources such as the register files are shared by two threads, they are increased in capacity in many cases to compensate for the loss of performance; the number of integer and floating-point registers is increased to 120 each, from 80 integer and 72 floating-point registers in the POWER4. The floating-point instruction cache is increased in capacity to 24 entries from 20; the capacity of the L2 unified cache was increased to the set-associativity to 10-way. The unified L3 cache was brought on-package instead of located externally in separate chips, its capacity was increased to 36 MB. Like the POWER4, the cache is shared by the two cores; the cache is accessed via two unidirectional 128-bit buses operating at half the core frequency. The on-die memory controller supports up to 64 GB of DDR2 memory.
It uses high-frequency serial buses to communicate with external buffers that interface the dual inline memory modules to the microprocessor. The POWER5 contains 276 million transistors and has an area of 389 mm2, it is fabricated by IBM in a 0.13 µm silicon on insulator complementary metal–oxide–semiconductor process with eight layers of copper interconnect. The POWER5 die is packaged in either a multi-chip module; the DCM contains one POWER5 die and its associated L3 cache die. The MCM contains four POWER5 dies and four L3 cache dies, one for each POWER5 die, measures 95 mm by 95 mm. Several POWER5 processors in high-end systems can be coupled together to act as a single vector processor by a technology called ViVA; the POWER5+ is an improved iteration of the POWER5 introduced on 4 October 2005. Improvements were lower power consumption, due to the newer process it was fabricated in; the POWER5+ chip uses a 90 nm fabrication process. This resulted in the die size decrease from 389 mm2 to 243 mm2.
Clock frequency remained between at 1.5 to 1.9 GHz. On 14 February 2006, new versions raised the clock frequency to 2.2 GHz and to 2.3 GHz on 25 July 2006. The POWER5+ was packaged in the same packages as previous POWER5 microprocessors, but was available in a quad-chip module containing two POWER5+ dies and two L3 cache dies, one for each POWER5+ die; these QCM chips ran at a clock frequency of between 1.8 GHz. IBM uses the DCM and MCM POWER5 microprocessors in its System p and System i server families, in its DS8000 storage server, as embedded microprocessors in its high-end Infoprint printers. DCM POWER5 microprocessors are used by IBM in its high-end IntelliStation POWER 285 workstation. Third-party users of POWER5 microprocessors are Groupe Bull, in its Escala servers, Hitachi, in its SR11000 computers with up to 128 POWER5+ microprocessors, which have several installations featured in the 2007 TOP500 list of supercomputers. IBM uses the POWER5 + in its System p5 520Q, 550Q and 560Q servers.
IBM System p IBM POWER microprocessors PowerPC POWER6 "IBM Previews Power5".. Microprocessor Report. Clabes, Joachim et al.. "Design and Implementation of the POWER5 Microprocessor". Proceedings of 2004 IEEE International Solid-State Circuits Conference. Glaskowsky, Peter N.. "IBM Raises Curtain on Power5". Microprocessor Report. Kalla, Ron. "IBM Power5 Chip: A Dual-Core Multithreaded Processor". IEEE Micro. Krewell, Kevin. "Power5 Tops On Bandwidth". Microprocessor Report. Sinharoy, Balaram et al.. "POWER5 System Microarchitecture". IBM Journal of Research and Development. Vance, Ashlee. "IBM pumps Unix line full of Power5+". The Register. Sizing up the Super Heavyweights, a comparison and analysis of the POWER5 and Montecito, that explains the major changes between the POWER4 to the POWER5, along with performance estimates A High-Performance IBM Power5+ p5-575 Cluster 1600 and DDN S2A9550 Storage, Texas A&M University