Sandy Bridge is the codename for the microarchitecture used in the "second generation" of the Intel Core processors - the Sandy Bridge microarchitecture is the successor to Nehalem microarchitecture. Intel demonstrated a Sandy Bridge processor in 2009, released first products based on the architecture in January 2011 under the Core brand. Sandy Bridge is manufactured in the 32 nanometer process, while Intel's subsequent generation Ivy Bridge uses a 22 nanometer die shrink; this was known as the tick–tock model. A Core i7 2600 Sandy Bridge CPU at 3.4 GHz with 1333 MHz DDR3 memory reaches 83 GFLOPS performance in the Whetstone benchmark and 118,000 MIPS in the Dhrystone benchmark. It is the last Intel microarchitecture for which Windows Vista driver support exists. Intel demonstrated a Sandy Bridge processor with A1 stepping at 2 GHz during the Intel Developer Forum in September 2009. Upgraded features from Nehalem include: Intel Turbo Boost 2.0 32 KB data + 32 KB instruction L1 cache and 256 KB L2 cache per core Shared L3 cache includes the processor graphics.
64-byte cache line size Improved 2 vector ALU and 2 AGU per core. Two load/store operations per CPU cycle for each memory channel Decoded micro-operation cache and enlarged, optimized branch predictor Sandy Bridge retains the four branch predictors found in Nehalem: the branch target buffer, indirect branch target array, loop detector and renamed return stack buffer. Sandy Bridge has a single BTB that holds twice as many branch targets as the L1 and L2 BTBs in Nehalem. Improved performance for transcendental mathematics, AES encryption, SHA-1 hashing 256-bit/cycle ring bus interconnect between cores, graphics and System Agent Domain Advanced Vector Extensions 256-bit instruction set with wider vectors, new extensible syntax and rich functionality. Intel Quick Sync Video, hardware support for video encoding and decoding Up to eight physical cores or 16 logical cores through Hyper-threading Integration of the GMCH and processor into a single die inside the processor package. In contrast, Sandy Bridge's predecessor, has two separate dies within the processor package.
This tighter integration reduces memory latency more. A 14- to 19-stage instruction pipeline, depending on the micro-operation cache hit or missAll translation lookaside buffers are 4-way associative. All Sandy Bridge processors with one, two, or four cores report the same CPUID model 0206A7h and are related; the stepping number can not be seen from the CPUID but only from the PCI configuration space. The Sandy Bridge-E processors with up to eight cores and no graphics are using CPUIDs 0206D6h and 0206D7h. Ivy Bridge CPUs all have CPUID 0306A9h to date, are built in four different configurations differing in the number of cores, L3 cache and GPU execution units; the average performance increase, according to IXBT Labs and Semi Accurate as well as many other benchmarking sites, at clock to clock is 11.3% compared to the Nehalem generation, which includes Bloomfield and Lynnfield processors. Around twice the integrated graphics performance compared to Clarkdale's. 1Processors featuring Intel's HD 3000 graphics are set in bold.
Other processors feature HD graphics or no graphics core. This list may not contain all the Sandy Bridge processors released by Intel. A more complete listing can be found on Intel's website. Suffixes to denote: K – Unlocked P – Versions clocked higher than similar models, but with onboard-graphics deactivated. S – Performance-optimized lifestyle T – Power-optimized lifestyle X – Extreme performance NOTE: 3970X, 3960X, 3930K, 3820 are of Sandy Bridge-E edition. Core i5-2515E and Core i7-2715QE processors have support for ECC memory and PCI express port bifurcation. All mobile processors, except Celeron and Pentium, use Intel's Graphics subsystem HD 3000. Suffixes to denote: M – Mobile processors XM – Unlocked QM – Quad-core E – Embedded mobile processors QE – Quad-core LE – Performance-optimized UE – Power-optimized On 31 January 2011, Intel issued a recall on all 67-series motherboards due to a flaw in the Cougar Point Chipset. A hardware problem, in which the chipset's SATA II ports may fail over time, cause failure of connection to SATA devices, though data is not at risk.
Intel claims that this problem will affect only 5% of users over 3 years, heavier I/O workloads can exacerbate the problem. Intel stopped production of flawed B2 stepping chipsets and began producing B3 stepping chipsets with the silicon fix. Shipping of these new chipsets started on 14 February 2011 and Intel estimated full recovery volume in April 2011. Motherboard manufacturers and computer manufacturers stopped selling products that involved the flawed chipset and offered support for affected customers. Options ranged from swapping for B3 motherboards to product refunds. Sandy Bridge processor sales were temporarily on hold, as one cannot use the CPU without a motherboard. However, processor release dates were not affected. After two weeks, Intel continued shipping some chipsets, but manufacturers had to agree to a set of terms that will prevent customers from encountering the bug. Motherboard manufacturer websites should have instruction about how to identify chipset stepping version using bios. lshw produces this partial output: above output
Trace Cache is a specialized cache which stores the dynamic stream of instructions known as trace. It helps in increasing the instruction fetch bandwidth and decreasing power consumption by storing traces of instructions that have been fetched and decoded. Trace Processor is an architecture designed around the Trace Cache and processes the instructions at trace level granularity; the earliest academic publication of trace cache was "Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching". This acknowledged paper was presented by Eric Rotenberg, Steve Bennett, Jim Smith at 1996 MICRO conference. An earlier publication is, by Uri Weiser of Intel Corp.. "Dynamic flow instruction cache memory organized around trace segments independent of virtual address line", a continuation of an application filed in 1992 abandoned. Wider superscalar processors demand multiple instructions to be fetched in a single cycle for higher performance. Instructions to be fetched are not always in contiguous memory locations because of branch and jump instructions.
So processors need additional logic and hardware support to fetch and align such instructions from non-contiguous basic blocks. If multiple branches are predicted as not-taken processors can fetch instructions from multiple contiguous basic blocks in a single cycle. However, if any of the branches is predicted as taken processor should fetch instructions from the taken path in that same cycle; this limits the fetch capability of a processor. Consider these four basic blocks as shown in the figure that correspond to a simple if-else loop; these blocks will be stored contiguously as ABCD in the memory. If the branch D is predicted not-taken, the fetch unit can fetch the basic blocks A,B,C which are placed contiguously. However, if D is predicted taken, the fetch unit has to fetch A,B,D which are non-contiguously placed. Hence, fetching these blocks which are non contiguously placed, in a single cycle will be difficult. So, in situations like these trace cache comes in aid to the processor. Once fetched, trace cache stores the instructions in their dynamic sequence.
When these instructions are encountered again, trace cache allows the instruction fetch unit of a processor to fetch several basic blocks from it without having to worry about branches in the execution flow. Instructions will be stored in trace cache either after they have been decoded, or as they are retired. However, instruction sequence is speculative. A trace called a dynamic instruction sequence, is an entry in the trace cache, it can be characterized by maximum number of maximum basic blocks. Traces can start at any dynamic instruction. Multiple traces can have same starting instruction i.e. same starting PC and instructions from different basic blocks as per the branch outcomes. For the figure above, ABC and ABD are valid traces, they both have different basic blocks as per D's prediction. Traces terminate when one of the following occurs: Trace got filled with allowable maximum number of instructions Trace has allowable maximum basic blocks Return Instructions Indirect branches System calls A single trace will have following information.
Starting PC - PC of the first instruction in trace Branch Flag - branch predictions Branch Mask - number of branches in the trace and whether trace ends in a branch or not Trace Fall through - Next PC if last instruction is not-taken branch or not a branch Trace Target - Address of last branch's taken target Following are the factors that need to be considered while designing a trace cache. Trace Selection Policies - maximum number of instructions and maximum basic blocks in a trace Associativity - number of ways a cache can have Cache Indexing Method - Concatenation or XOR with PC bits Path Associativity - traces with same starting PC but with different basic blocks can be mapped to different sets Trace Cache Fill choices - After decode stage After retire stageA trace cache is not on the critical path of instruction fetch Trace lines are stored in the trace cache based on the program counter of the first instruction in the trace and a set of branch predictions; this allows for storing different trace paths that start on the same address, each representing different branch outcomes.
This method of tagging helps to provide path associativity to the trace cache. Other method can include having only starting PC as tag in trace cache. In the instruction fetch stage of a pipeline, the current program counter along with a set of branch predictions is checked in the trace cache for a hit. If there is a hit, a trace line is supplied to fetch unit which does not have to go to a regular cache or to memory for these instructions; the trace cache continues to feed the fetch unit until the trace line ends or until there is a misprediction in the pipeline. If there is a miss, a new trace starts to be built; the Pentium 4's Execution Trace Cache stores micro-operations resulting from decoding x86 instructions, providing the functionality of a micro-operation cache. Having this, the next time an instruction is needed, it does not have to be decoded into micro-ops again; the disadvantages of trace cache are: Redundant instruction storage between trace cache and instruction cache and within trace cache itself.
Power inefficiency and hardware complexity Within the L1 cache of the NetBurst CPUs, Intel incorporated its Execution Trace Cache. It stores decoded micro-operations, so that when executing a new instruction, instead of fetching and decoding the instruction again, the CPU directly
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, in the Silicon Valley. It is the world's second largest and second highest valued semiconductor chip manufacturer based on revenue after being overtaken by Samsung, is the inventor of the x86 series of microprocessors, the processors found in most personal computers. Intel ranked No. 46 in the 2018 Fortune 500 list of the largest United States corporations by total revenue. Intel supplies processors for computer system manufacturers such as Apple, Lenovo, HP, Dell. Intel manufactures motherboard chipsets, network interface controllers and integrated circuits, flash memory, graphics chips, embedded processors and other devices related to communications and computing. Intel Corporation was founded on July 18, 1968, by semiconductor pioneers Robert Noyce and Gordon Moore, associated with the executive leadership and vision of Andrew Grove; the company's name was conceived as portmanteau of the words integrated and electronics, with co-founder Noyce having been a key inventor of the integrated circuit.
The fact that "intel" is the term for intelligence information made the name appropriate. Intel was an early developer of SRAM and DRAM memory chips, which represented the majority of its business until 1981. Although Intel created the world's first commercial microprocessor chip in 1971, it was not until the success of the personal computer that this became its primary business. During the 1990s, Intel invested in new microprocessor designs fostering the rapid growth of the computer industry. During this period Intel became the dominant supplier of microprocessors for PCs and was known for aggressive and anti-competitive tactics in defense of its market position against Advanced Micro Devices, as well as a struggle with Microsoft for control over the direction of the PC industry; the Open Source Technology Center at Intel hosts PowerTOP and LatencyTOP, supports other open-source projects such as Wayland, Mesa3D, Intel Array Building Blocks, Threading Building Blocks, Xen. Client Computing Group – 55% of 2016 revenues – produces hardware components used in desktop and notebook computers.
Data Center Group – 29% of 2016 revenues – produces hardware components used in server and storage platforms. Internet of Things Group – 5% of 2016 revenues – offers platforms designed for retail, industrial and home use. Non-Volatile Memory Solutions Group – 4% of 2016 revenues – manufactures NAND flash memory and 3D XPoint, branded as Optane, products used in solid-state drives. Intel Security Group – 4% of 2016 revenues – produces software security, antivirus software. Programmable Solutions Group – 3% of 2016 revenues – manufactures programmable semiconductors. In 2017, Dell accounted for about 16% of Intel's total revenues, Lenovo accounted for 13% of total revenues, HP Inc. accounted for 11% of total revenues. According to IDC, while Intel enjoyed the biggest market share in both the overall worldwide PC microprocessor market and the mobile PC microprocessor in the second quarter of 2011, the numbers decreased by 1.5% and 1.9% compared to the first quarter of 2011. In the 1980s, Intel was among the top ten sellers of semiconductors in the world.
In 1992, Intel became the biggest chip maker by revenue and has held the position since. Other top semiconductor companies include TSMC, Advanced Micro Devices, Texas Instruments, Toshiba and STMicroelectronics. Competitors in PC chipsets include Advanced Micro Devices, VIA Technologies, Silicon Integrated Systems, Nvidia. Intel's competitors in networking include NXP Semiconductors, Broadcom Limited, Marvell Technology Group and Applied Micro Circuits Corporation, competitors in flash memory include Spansion, Qimonda, Toshiba, STMicroelectronics, SK Hynix; the only major competitor in the x86 processor market is Advanced Micro Devices, with which Intel has had full cross-licensing agreements since 1976: each partner can use the other's patented technological innovations without charge after a certain time. However, the cross-licensing agreement is canceled in the event of takeover; some smaller competitors such as VIA Technologies produce low-power x86 processors for small factor computers and portable equipment.
However, the advent of such mobile computing devices, in particular, has in recent years led to a decline in PC sales. Since over 95% of the world's smartphones use processors designed by ARM Holdings, ARM has become a major competitor for Intel's processor market. ARM is planning to make inroads into the PC and server market. Intel has been involved in several disputes regarding violation of antitrust laws, which are noted below. Intel was founded in Mountain View, California, in 1968 by Gordon E. Moore, a chemist, Robert Noyce, a physicist and co-inventor of the integrated circuit. Arthur Rock helped. Moore and Noyce had left Fairchild Semiconductor to found Intel. Rock was not an employee; the total initial investment in Intel was $10,000 from Rock. Just 2 years Intel became a public company via an initial public offering, raising $6.8 million. Intel's third employee was Andy Grove, a chemical engineer, who ran the company through much of the 1980s and the high-growth 1990s. In dec
A CPU cache is a hardware cache used by the central processing unit of a computer to reduce the average cost to access data from the main memory. A cache is a smaller, faster memory, closer to a processor core, which stores copies of the data from used main memory locations. Most CPUs have different independent caches, including instruction and data caches, where the data cache is organized as a hierarchy of more cache levels. All modern CPUs have multiple levels of CPU caches; the first CPUs that used a cache had only one level of cache. All current CPUs with caches have a split L1 cache, they have L2 caches and, for larger processors, L3 caches as well. The L2 cache is not split and acts as a common repository for the split L1 cache; every core of a multi-core processor has a dedicated L2 cache and is not shared between the cores. The L3 cache, higher-level caches, are shared between the cores and are not split. An L4 cache is uncommon, is on dynamic random-access memory, rather than on static random-access memory, on a separate die or chip.
That was the case with L1, while bigger chips have allowed integration of it and all cache levels, with the possible exception of the last level. Each extra level of cache tends to be optimized differently. Other types of caches exist, such as the translation lookaside buffer, part of the memory management unit that most CPUs have. Caches are sized in powers of two: 4, 8, 16 etc. KiB or MiB sizes; when trying to read from or write to a location in main memory, the processor checks whether the data from that location is in the cache. If so, the processor will read from or write to the cache instead of main memory, much slower. Most modern desktop and server CPUs have at least three independent caches: an instruction cache to speed up executable instruction fetch, a data cache to speed up data fetch and store, a translation lookaside buffer used to speed up virtual-to-physical address translation for both executable instructions and data. A single TLB can be provided for access to both instructions and data, or a separate Instruction TLB and data TLB can be provided.
The data cache is organized as a hierarchy of more cache levels. However, the TLB cache is part of the memory management unit and not directly related to the CPU caches. Data is transferred between memory and cache in blocks of fixed size, called cache lines or cache blocks; when a cache line is copied from memory into the cache, a cache entry is created. The cache entry will include the copied data as well as the requested memory location; when the processor needs to read or write a location in memory, it first checks for a corresponding entry in the cache. The cache checks for the contents of the requested memory location in any cache lines that might contain that address. If the processor finds that the memory location is in the cache, a cache hit has occurred. However, if the processor does not find the memory location in the cache, a cache miss. In the case of a cache hit, the processor reads or writes the data in the cache line. For a cache miss, the cache allocates a new entry and copies data from main memory the request is fulfilled from the contents of the cache.
To make room for the new entry on a cache miss, the cache may have to evict one of the existing entries. The heuristic it uses to choose the entry to evict is called the replacement policy; the fundamental problem with any replacement policy is that it must predict which existing cache entry is least to be used in the future. Predicting the future is difficult, so there is no perfect method to choose among the variety of replacement policies available. One popular replacement policy, least-recently used, replaces the least accessed entry. Marking some memory ranges as non-cacheable can improve performance, by avoiding caching of memory regions that are re-accessed; this avoids the overhead of loading something into the cache without having any reuse. Cache entries may be disabled or locked depending on the context. If data is written to the cache, at some point it must be written to main memory. In a write-through cache, every write to the cache causes a write to main memory. Alternatively, in a write-back or copy-back cache, writes are not mirrored to the main memory, the cache instead tracks which locations have been written over, marking them as dirty.
The data in these locations is written back to the main memory only when that data is evicted from the cache. For this reason, a read miss in a write-back cache may sometimes require two memory accesses to service: one to first write the dirty location to main memory, another to read the new location from memory. A write to a main memory location, not yet mapped in a write-back cache may evict an dirty location, thereby freeing that cache space for the new memory location. There are intermediate policies as well; the cache may be write-through, but the writes may be held in a store data queue temporarily so multiple stores can be processed together. Cached data from the main memory may be changed b
Hyper-threading is Intel's proprietary simultaneous multithreading implementation used to improve parallelization of computations performed on x86 microprocessors. It first appeared in February 2002 on Xeon server processors and in November 2002 on Pentium 4 desktop CPUs. Intel included this technology in Itanium and Core'i' Series CPUs, among others. For each processor core, physically present, the operating system addresses two virtual cores and shares the workload between them when possible; the main function of hyper-threading is to increase the number of independent instructions in the pipeline. With HTT, one physical core appears as two processors to the operating system, allowing concurrent scheduling of two processes per core. In addition, two or more processes can use the same resources: if resources for one process are not available another process can continue if its resources are available. In addition to requiring simultaneous multithreading support in the operating system, hyper-threading can be properly utilized only with an operating system optimized for it.
Furthermore, Intel recommends HTT to be disabled when using operating systems unaware of this hardware feature. Hyper-Threading Technology is a form of simultaneous multithreading technology introduced by Intel, while the concept behind the technology has been patented by Sun Microsystems. Architecturally, a processor with Hyper-Threading Technology consists of two logical processors per core, each of which has its own processor architectural state; each logical processor can be individually halted, interrupted or directed to execute a specified thread, independently from the other logical processor sharing the same physical core. Unlike a traditional dual-processor configuration that uses two separate physical processors, the logical processors in a hyper-threaded core share the execution resources; these resources include the execution engine and system bus interface. A processor stalls when it is waiting for data it has sent for so it can finish processing the present thread; the degree of benefit seen when using a hyper-threaded or multi core processor depends on the needs of the software, how well it and the operating system are written to manage the processor efficiently.
Hyper-threading works by duplicating certain sections of the processor—those that store the architectural state—but not duplicating the main execution resources. This allows a hyper-threading processor to appear as the usual "physical" processor and an extra "logical" processor to the host operating system, allowing the operating system to schedule two threads or processes and appropriately; when execution resources would not be used by the current task in a processor without hyper-threading, when the processor is stalled, a hyper-threading equipped processor can use those execution resources to execute another scheduled task. This technology is transparent to operating programs; the minimum, required to take advantage of hyper-threading is symmetric multiprocessing support in the operating system, as the logical processors appear as standard separate processors. It is possible to optimize operating system behavior on multi-processor hyper-threading capable systems. For example, consider an SMP system with two physical processors that are both hyper-threaded.
If the operating system's thread scheduler is unaware of hyper-threading, it will treat all four logical processors the same. If only two threads are eligible to run, it might choose to schedule those threads on the two logical processors that happen to belong to the same physical processor; this problem can be avoided by improving the scheduler to treat logical processors differently from physical processors. Denelcor, Inc. introduced multi-threading with the Heterogeneous Element Processor in 1982. The HEP pipeline could not hold multiple instructions from the same process. Only one instruction from a given process was allowed to be present in the pipeline at any point in time. Should an instruction from a given process block the pipe, instructions from other processes would continue after the pipeline drained. US patent for the technology behind hyper-threading was granted to Kenneth Okin at Sun Microsystems in November 1994. At that time, CMOS process technology was not advanced enough to allow for a cost-effective implementation.
Intel implemented hyper-threading on an x86 architecture processor in 2002 with the Foster MP-based Xeon. It was included on the 3.06 GHz Northwood-based Pentium 4 in the same year, remained as a feature in every Pentium 4 HT, Pentium 4 Extreme Edition and Pentium Extreme Edition processor since. Previous generations of Intel's processors based on the Core microarchitecture do not have Hyper-Threading, because the Core microarchitecture is a descendant of the P6 microa
Socket 604 is a 604-pin microprocessor socket designed to interface an Intel's Xeon processor to the rest of the computer. It provides both an electrical interface as well as physical support; this socket is designed to support a heatsink. Socket 604 was designed by Intel as a zero insertion force socket intended for workstations and server platforms. While the socket contains 604 pins, it only has 603 the last being a dummy pin; each contact has a 1.27 mm pitch with regular pin array. Socket 604 processors utilize a bus speed of either 400, 533, 667, 800, or 1066 MHz and were manufactured in either a 130, 90, 65 or 45 nm process. Socket 604 processors cannot be inserted into Socket 603 designed motherboards due to one additional pin being present, but Socket 603 processors can be inserted into Socket 604 designed motherboards, since the extra pin slot does not do anything for a 603 CPU. Socket 604 processors range from 1.60 GHz through 3.80 GHz, with the higher clock rates only found among older, slower NetBurst-based Xeons.
The following Intel Xeon chipsets used Socket 604: Intel E7205 Intel E7210 Canterwood-ES Intel E7320 Intel E7500 Intel E7501 Intel E7505 Intel E7520 Intel E7525Late Socket 604 "revivals": Intel Xeon 7300 Intel Xeon 7400. List of Intel microprocessors List of Intel Xeon microprocessors Intel.com
Central processing unit
A central processing unit called a central processor or main processor, is the electronic circuitry within a computer that carries out the instructions of a computer program by performing the basic arithmetic, logic and input/output operations specified by the instructions. The computer industry has used the term "central processing unit" at least since the early 1960s. Traditionally, the term "CPU" refers to a processor, more to its processing unit and control unit, distinguishing these core elements of a computer from external components such as main memory and I/O circuitry; the form and implementation of CPUs have changed over the course of their history, but their fundamental operation remains unchanged. Principal components of a CPU include the arithmetic logic unit that performs arithmetic and logic operations, processor registers that supply operands to the ALU and store the results of ALU operations and a control unit that orchestrates the fetching and execution of instructions by directing the coordinated operations of the ALU, registers and other components.
Most modern CPUs are microprocessors, meaning they are contained on a single integrated circuit chip. An IC that contains a CPU may contain memory, peripheral interfaces, other components of a computer; some computers employ a multi-core processor, a single chip containing two or more CPUs called "cores". Array processors or vector processors have multiple processors that operate in parallel, with no unit considered central. There exists the concept of virtual CPUs which are an abstraction of dynamical aggregated computational resources. Early computers such as the ENIAC had to be physically rewired to perform different tasks, which caused these machines to be called "fixed-program computers". Since the term "CPU" is defined as a device for software execution, the earliest devices that could rightly be called CPUs came with the advent of the stored-program computer; the idea of a stored-program computer had been present in the design of J. Presper Eckert and John William Mauchly's ENIAC, but was omitted so that it could be finished sooner.
On June 30, 1945, before ENIAC was made, mathematician John von Neumann distributed the paper entitled First Draft of a Report on the EDVAC. It was the outline of a stored-program computer that would be completed in August 1949. EDVAC was designed to perform a certain number of instructions of various types; the programs written for EDVAC were to be stored in high-speed computer memory rather than specified by the physical wiring of the computer. This overcame a severe limitation of ENIAC, the considerable time and effort required to reconfigure the computer to perform a new task. With von Neumann's design, the program that EDVAC ran could be changed by changing the contents of the memory. EDVAC, was not the first stored-program computer. Early CPUs were custom designs used as part of a sometimes distinctive computer. However, this method of designing custom CPUs for a particular application has given way to the development of multi-purpose processors produced in large quantities; this standardization began in the era of discrete transistor mainframes and minicomputers and has accelerated with the popularization of the integrated circuit.
The IC has allowed complex CPUs to be designed and manufactured to tolerances on the order of nanometers. Both the miniaturization and standardization of CPUs have increased the presence of digital devices in modern life far beyond the limited application of dedicated computing machines. Modern microprocessors appear in electronic devices ranging from automobiles to cellphones, sometimes in toys. While von Neumann is most credited with the design of the stored-program computer because of his design of EDVAC, the design became known as the von Neumann architecture, others before him, such as Konrad Zuse, had suggested and implemented similar ideas; the so-called Harvard architecture of the Harvard Mark I, completed before EDVAC used a stored-program design using punched paper tape rather than electronic memory. The key difference between the von Neumann and Harvard architectures is that the latter separates the storage and treatment of CPU instructions and data, while the former uses the same memory space for both.
Most modern CPUs are von Neumann in design, but CPUs with the Harvard architecture are seen as well in embedded applications. Relays and vacuum tubes were used as switching elements; the overall speed of a system is dependent on the speed of the switches. Tube computers like EDVAC tended to average eight hours between failures, whereas relay computers like the Harvard Mark I failed rarely. In the end, tube-based CPUs became dominant because the significant speed advantages afforded outweighed the reliability problems. Most of these early synchronous CPUs ran at low clock rates compared to modern microelectronic designs. Clock signal frequencies ranging from 100 kHz to 4 MHz were common at this time, limited by the speed of the switching de