A general-purpose input/output is an uncommitted digital signal pin on an integrated circuit or electronic circuit board whose behavior—including whether it acts as input or output—is controllable by the user at run time. GPIOs are unused by default. If used, the purpose and behavior of a GPIO is defined and implemented by the designer of higher assembly-level circuitry: the circuit board designer in the case of integrated circuit GPIOs, or system integrator in the case of board-level GPIOs. Integrated circuit GPIOs are implemented in a variety of ways; some ICs provide GPIOs as a primary function whereas others include GPIOs as a convenient "accessory" to some other primary function. Examples of the former include the Intel 8255, which interfaces 24 GPIOs to a parallel bus, various GPIO "expander" ICs, which interface GPIOs to serial buses such as I²C and SMBus. An example of the latter is the Realtek ALC260 IC, which provides eight GPIOs in addition to its primary function of audio codec. Microcontroller ICs include GPIOs.
Depending on the application, a microcontroller's GPIOs may comprise its primary interface to external circuitry or they may be just one type of I/O used among several, such as analog I/O, counter/timer, serial communication. In some ICs microcontrollers, a GPIO pin may be capable of alternate functions. In such cases, it is necessary to configure the pin to operate as a GPIO in addition to configuring the GPIO's behavior; some microcontroller devices incorporate internal signal routing circuitry that allows GPIOs to be programmatically mapped to device pins. FPGAs extend this capability by allowing GPIO pin mapping and architecture to be programmatically controlled. Many circuit boards expose board-level GPIOs to external circuitry through integrated electrical connectors; each such GPIO is accessible via a dedicated connector pin. Like IC-based GPIOs, some boards include GPIOs as a convenient, auxiliary resource that augments the board's primary function, whereas in other boards the GPIOs are the central, primary function of the board.
Some boards, which are classified as multi-function I/O boards, are a combination of both. GPIOs are found on embedded controller boards such as Arduino, BeagleBone and Raspberry Pi. Board-level GPIOs are endowed with capabilities which are not found in IC-based GPIOs. For example, schmitt-trigger inputs, high-current output drivers, optical isolators, or combinations of these may be used to buffer and condition the GPIO signals and to protect board circuitry. Higher-level functions are sometimes implemented, such as input debounce, input signal edge detection, pulse-width modulation output. GPIOs are used in a diverse variety of applications, limited only by the electrical and timing specifications of the GPIO interface and the ability of software to interact with GPIOs in a sufficiently timely manner. GPIOs employ standard logic levels and cannot supply significant current to output loads; when followed by an appropriate high-current output buffer, a GPIO may be used to control high-power devices such as lights, solenoids and motors.
An input buffer, relay or optoisolator is used to translate an otherwise incompatible signal to the logic levels required by a GPIO. Integrated circuit GPIOs are used to control or monitor other circuitry on a board. Examples of this include enabling and disabling the operation of other circuitry, reading the states of on-board switches and configuration shunts, driving LED status indicators. In the latter case, a GPIO can, in many cases, supply enough output current to directly power an LED without using an intermediate buffer. Multiple GPIOs are sometimes used together as a bit-banged communication interface. For example, two GPIOs may be used to implement a serial communication bus such as I²C, four GPIOs can be used to implement an SPI bus. Taken to the extreme, this technique may be used to implement an entire parallel bus, thus allowing communication with bus-oriented ICs or circuit boards. Although GPIOs are fundamentally digital in nature, they are used to control linear processes. For example, a GPIO may be used to control light intensity, or temperature.
This is accomplished via PWM, in which the duty cycle of the GPIO output signal determines the effective magnitude of the process control signal. For example, when controlling light intensity, the light may be dimmed by reducing the GPIO duty cycle; some linear processes require a linear control voltage. GPIO interfaces vary widely. In some cases, they are simple -- a group of pins that can switch as a group to either output. In others, each pin can be set up to accept or source different logic voltages, with configurable drive strengths and pull ups/downs. Input and output voltages are typically—though not always—limited to the supply voltage of the device with the GPIOs, may be damaged by greater voltages. A GPIO pin's state may be exposed to the software developer through one of a number of different interfaces, such as a memory mapped peripheral
A semiconductor package is a metal, glass, or ceramic casing containing one or more discrete semiconductor devices or integrated circuits. Individual components are fabricated on semiconductor wafers before being diced into die and packaged; the package provides a means for connecting the package to the external environment, such as printed circuit board, via leads such as lands, balls, or pins. Additionally, it helps dissipate heat produced by the device, with or without the aid of a heat spreader. There are thousands of package types in use; some are defined by international, national, or industry standards, while others are particular to an individual manufacturer. A semiconductor package may have as few as two leads or contacts for devices such as diodes, or in the case of advanced microprocessors, a package may have hundreds of connections. Small packages may be supported only by their wire leads. Larger devices, intended for high-power applications, are installed in designed heat sinks so that they can dissipate hundred or thousands of watts of waste heat.
In addition to providing connections to the semiconductor and handling waste heat, the semiconductor package must protect the "chip" from the environment the ingress of moisture. Stray particles or corrosion products inside the package may degrade performance of the device or cause failure. A hermetic package allows no gas exchange with the surroundings. Manufacturers print -- using ink or laser marking -- the manufacturer's logo and the manufacturer's part number on the package, to make it easier to distinguish the many different and incompatible devices packaged in few kinds of packages; the markings include a 4 digit date code represented as YYWW where YY is replaced by the last 2 digits of the calendar year and WW is replaced by the two-digit week number. To make connections between an integrated circuit and the leads of the package, wire bonds are used, with fine wires connected from the package leads and bonded to conductive pads on the semiconductor die. At the outside of the package, wire leads may be soldered to a printed circuit board or used to secure the device to a tag strip.
Modern surface mount devices eliminate most of the drilled holes through circuit boards, have short metal leads or pads on the package that can be secured by oven-reflow soldering. Aerospace devices in flat packs may use flat metal leads secured to a circuit board by spot welding, though this type of construction is now uncommon. Early semiconductor devices were inserted in sockets, like vacuum tubes; as devices improved sockets proved unnecessary for reliability, devices were directly soldered to printed circuit boards. The package must handle the high temperature gradients of soldering without putting stress on the semiconductor die or its leads. Sockets are still used for experimental, prototype, or educational applications, for testing of devices, for high-value chips such as microprocessors where replacement is still more economical than discarding the product, for applications where the chip contains firmware or unique data that might be replaced or refreshed during the life of the product.
Devices with hundreds of leads may be inserted in zero insertion force sockets, which are used on test equipment or device programmers. Many devices are molded out of an epoxy plastic that provides adequate protection of the semiconductor devices, mechanical strength to support the leads and handling of the package; some devices, intended for high-reliability or aerospace or radiation environments, use ceramic packages, with metal lids that are brazed on after assembly, or a glass frit seal. All-metal packages are used with high power devices, since they conduct heat well and allow for easy assembly to a heat sink; the package forms one contact for the semiconductor device. Lead materials must be chosen with a thermal coefficient of expansion to match the package material. A few early semiconductors were packed in miniature evacuated glass envelopes, like flashlight bulbs. Glass packages are still used with diodes, glass seals are used in metal transistor packages. Package materials for high-density dynamic memory must be selected for low background radiation.
Spaceflight and military applications traditionally used hermetically packaged microcircuits. However, most modern integrated circuits are only available as plastic encapsulated microcircuits. Proper fabrication practices using properly qualified PEMs can be used for spaceflight. Multiple semiconductor dies and discrete components can be assembled on a ceramic substrate and interconnected with wire bonds; the substrate bears leads for connection to an external circuit, the whole is covered with a welded or frit cover. Such devices are used when requirements exceed the performance available in a single-die integrated circuit, or for mixing analog and digital functions in the same package; such packages are expensive to manufacture, but provide most of the other benefits of integrated circuits. A modern example of multi-chip integrated circuit packages would be certain models of microprocessor, which may include separate dies for such things as cache memory within the same package
A footprint or land pattern is the arrangement of pads or through-holes used to physically attach and electrically connect a component to a printed circuit board. The land pattern on a circuit board matches the arrangement of leads on a component. Component manufacturers produce multiple pin-compatible product variants to allow systems integrators to change the exact component in use without changing the footprint on the circuit board; this can provide large cost savings for integrators with dense BGA components where the footprint pads may be connected to multiple layers of the circuit board. Surface-mount technology Through-hole technology Chip carrier List of integrated circuit packaging types IPC JEDEC
In a computer system, a chipset is a set of electronic components in an integrated circuit known as a "Data Flow Management System" that manages the data flow between the processor and peripherals. It is found on the motherboard. Chipsets are designed to work with a specific family of microprocessors; because it controls communications between the processor and external devices, the chipset plays a crucial role in determining system performance. In computing, the term chipset refers to a set of specialized chips on a computer's motherboard or an expansion card. In personal computers, the first chipset for the IBM PC AT of 1984 was the NEAT chipset developed by Chips and Technologies for the Intel 80286 CPU. In home computers, game consoles and arcade-game hardware of the 1980s and 1990s, the term chipset was used for the custom audio and graphics chips. Examples include SEGA's System 16 chipset; the term chipset refers to a specific pair of chips on the motherboard: the northbridge and the southbridge.
The northbridge links the CPU to high-speed devices RAM and graphics controllers, the southbridge connects to lower-speed peripheral buses. In many modern chipsets, the southbridge contains some on-chip integrated peripherals, such as Ethernet, USB, audio devices. Motherboards and their chipsets come from different manufacturers; as of 2015, manufacturers of chipsets for x86 motherboards include AMD, Intel, NVIDIA, SiS and VIA Technologies. Apple computers and Unix workstations have traditionally used custom-designed chipsets; some server manufacturers develop custom chipsets for their products. In the 1980s, Chips and Technologies pioneered the manufacturing of chipsets for PC-compatible computers. Computer systems produced since often share used chipsets across disparate computing specialties. For example, the NCR 53C9x, a low-cost chipset implementing a SCSI interface to storage devices, could be found in Unix machines such as the MIPS Magnum, embedded devices, personal computers. Traditionally in x86 computers, the processor's primary connection to the rest of the machine was through the motherboard chipset's northbridge.
The northbridge was directly responsible for communications with high-speed devices and conversely any system communication back to the processor. This connection between the processor and northbridge is designated the front side bus. Requests to resources not directly controlled by the northbridge were offloaded to the southbridge, with the northbridge being an intermediary between the processor and the southbridge; the southbridge handled "everything else" lower-speed peripherals and board functions such as USB, parallel and serial communications. The connection between the northbridge and southbridge was the PCI bus. Before 2003, any interaction between a CPU and main memory or an expansion device such as a graphics card — whether AGP, PCI or integrated into the motherboard — was directly controlled by the northbridge IC on behalf of the processor; this made processor performance dependent on the system chipset the northbridge's memory performance and ability to shuttle this information back to the processor.
In 2003, however, AMD's introduction of the Athlon 64-bit series of processors changed this. The Athlon64 marked the introduction of an integrated memory controller being incorporated into the processor itself thus allowing the processor to directly access and handle memory, negating the need for a traditional northbridge to do so. Intel followed suit in 2008 with the release of its Core i series the X58 platform. In newer processors integration has further increased through the inclusion of the system's primary PCIe controller and integrated graphics directly on the CPU itself; as fewer functions are left un-handled by the processor, chipset vendors have condensed the remaining northbridge and southbridge functions into a single chip. Intel's version of this is the "Platform Controller Hub" an enhanced southbridge for the remaining peripherals—as traditional northbridge duties, such as memory controller, expansion bus interface and on-board video controller, are integrated into the CPU die itself.
However, the Platform Controller Hub was integrated into the processor package as a second die for mobile variants of the Skylake processors. Acer Laboratories Incorporated Comparison of AMD chipsets Comparison of ATI chipsets Comparison of Nvidia chipsets List of Intel chipsets Northbridge Redpine Signals Silicon Integrated Systems Southbridge Very-large-scale integration or VLSI VIA chipsets
Small Outline Integrated Circuit
A Small Outline Integrated Circuit is a surface-mounted integrated circuit package which occupies an area about 30–50% less than an equivalent dual in-line package, with a typical thickness being 70% less. They are available in the same pin-outs as their counterpart DIP ICs; the convention for naming the package is SO followed by the number of pins. For example, a 14-pin 4011 would be housed in an SO-14 package. SOIC refers to at least two different package standards: The EIAJ SOIC body is 5.3 mm wide, while the JEDEC SOIC body is 3.8 mm wide. The EIAJ packages are thicker and longer. Otherwise the packages are similar. Note that because of this, SOIC is not specific enough of a term to describe parts which are interchangeable. Many electronic retailers will list parts in either package as SOIC whether they are referring to the JEDEC or EIAJ standards; the wider EIAJ packages are more common with higher pin count ICs, but there is no guarantee that an SOIC package with any number of pins will be either one or the other.
The SOIC package is shorter and narrower than DIPs, the side-to-side pitch being 6 mm for an SOIC-14 and the body width being 3.9 mm. These dimensions differ depending on the SOIC in question, there are several variants; this package has "gull wing" leads protruding from the two long sides and a lead spacing of 0.050 in. The picture below shows the general shape of a SOIC narrow package, with major dimensions; the values of these dimensions for common SOICs is shown in the table. Next to the narrow SOIC package, there's the wide version; this package is represented as SOx_W or SOICx_W. The difference is related to the parameters WB and WL; as an example, the values WB and WL are given for an 8-pins wide SOIC package. Another SOIC variant, available only for 8-pins and 10-pins ICs, is the mini-SOIC called micro-SOIC; this case is much smaller with a pitch of only 0.5 mm. See the following table for the 10-pin model: An excellent overview of different semiconductor packages can be found here. Small-outline J-leaded package is a version of SOIC with J-type leads instead of gull-wing leads.
After SOIC came a family of smaller form factors, small-outline package, with pin spacings less than 1.27 mm: Plastic small outline package Thin small outline package Thin-shrink small outline package Shrink small-outline package chips have "gull wing" leads protruding from the two long sides, a lead spacing of 0.0256 inches or 0.025 inches. 0.5 mm lead spacing is not rare. The body size of a SOP was compressed and the lead pitch tightened to obtain a smaller version SOP; this yields an IC package, a significant reduction in the size. All IC assembly processes remain the same as with standard SOPs. Applications for a SSOP enable end-products to be reduced in weight. Semiconductor families such as operational amplifiers, optoelectronics, logic, memory and more using BiCMOS, CMOS or other silicon / GaAs technologies are well addressed by the SSOP product family. A thin small-outline package is a thin bodied component; the ICs on DRAM memory modules were TSOPs until they were replaced by ball grid array.
A thin-shrink small-outline package is a thin body size component. A Type I TSSOP has legs protruding from the width portion of the package. A Type II TSSOP has the legs protruding from the length portion of the package. A TSSOP's leg count can range from 8 to 64. TSSOPs are suited for gate drivers, wireless / RF, op-amps, analog, ASICs, memory and optoelectronics. Memory modules, disk drives, recordable optical disks, telephone handsets, speed dialers, video / audio and consumer electronics / appliances are suggested uses for TSSOP packaging; the Exposed Pad variant of small outline packages can increase heat dissipation by as much as 1.5 times over a standard TSSOP, thereby expanding the margin of operating parameters. Additionally, the Exposed Pad can be connected to ground, thereby reducing loop inductance for high frequency applications; the ExposedPad should be soldered directly to the PCB to realize the thermal and electrical benefits. Fairchild CAD drawing and footprint for SOIC-8 Amkor Technology SOIC Package Amkor Technology ExposedPad SOIC/SSOP Package Amkor Technology SSOP package.
Image of a 74HC4067 multiplexer chip in a SSOP package. A US quarter is shown for a size reference
The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by Arm Holdings. They are intended for microcontroller use, have been shipped in tens of billions of devices; the cores consist of the Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M35P. The Cortex-M4 / M7 / M33 / M35P cores have an FPU silicon option, when included in the silicon these cores are known as "Cortex-Mx with FPU" or "Cortex-MxF", where'x' is the core number; the ARM Cortex-M family are ARM microprocessor cores which are designed for use in microcontrollers, ASICs, ASSPs, FPGAs, SoCs. Cortex-M cores are used as dedicated microcontroller chips, but are "hidden" inside of SoC chips as power management controllers, I/O controllers, system controllers, touch screen controllers, smart battery controllers, sensors controllers. Though 8-bit microcontrollers were popular in the past, Cortex-M has been chipping away at the 8-bit market as the prices of low-end Cortex-M chips have moved downward.
Cortex-M have become a popular replacements for 8-bit chips in applications that benefit from 32-bit math operations, replacing older legacy ARM cores such as ARM7 and ARM9. Arm Holdings neither manufactures nor sells CPU devices based on its own designs, but rather licenses the processor architecture to interested parties. Arm offers a variety of varying in cost and deliverables. To all licensees, Arm provides an integratable hardware description of the ARM core, as well as complete software development toolset and the right to sell manufactured silicon containing the ARM CPU. Integrated device manufacturers receive the ARM Processor IP as synthesizable RTL. In this form, they have the ability to perform architectural level extensions; this allows the manufacturer to achieve custom design goals, such as higher clock speed low power consumption, instruction set extensions, optimizations for size, debug support, etc. To determine which components have been included in a particular ARM CPU chip, consult the manufacturer datasheet and related documentation.
Some of the silicon options for the Cortex-M cores are: SysTick timer: A 24-bit system timer that extends the functionality of both the processor and the Nested Vectored Interrupt Controller. When present, it provides an additional configurable priority SysTick interrupt. Though the SysTick timer is optional, it is rare to find a Cortex-M microcontroller without it. If a Cortex-M33 microcontroller has the Security Extension option it has two SysTicks, one Secure and one Non-secure. Bit-Band: Maps a complete word of memory onto a single bit in the bit-band region. For example, writing to an alias word will set or clear the corresponding bit in the bit-band region; this allows every individual bit in the bit-band region to be directly accessible from a word-aligned address. In particular, individual bits can be set, cleared, or toggled from C/C++ without performing a read-modify-write sequence of instructions. Though the bit-band is optional, it is less common to find a Cortex-M3 and Cortex-M4 microcontroller without it.
Some Cortex-M0 and Cortex-M0+ microcontrollers have bit-band. Memory Protection Unit: Provides support for protecting regions of memory through enforcing privilege and access rules, it supports up to eight different regions, each of which can be split into a further eight equal-size sub-regions. Tightly-Coupled Memory: Low-latency RAM, used to hold critical routines, stacks. Other than cache, it is the fastest RAM in the microcontroller. Note: Most Cortex-M3 and M4 chips have bit-band and MPU; the bit-band option can be added to the M0/M0+ using the Cortex-M System Design Kit. Note: Software should validate the existence of a feature before attempting to use it. Note: Limited public information is available for the Cortex-M35P until its Technical Reference Manual is released in 2019. Additional silicon options: Data endianness: Little-endian or big-endian. Unlike legacy ARM cores, the Cortex-M is permanently fixed in silicon as one of these choices. Interrupts: 1 to 32, 1 to 240, 1 to 480. Wake-up interrupt controller: Optional.
Vector Table Offset Register: Optional.. Instruction fetch width: 16-bit only, or 32-bit. User/privilege support: Optional. Reset all registers: Optional. Single-cycle I/O port: Optional.. Debug Access Port: None, SWD, JTAG and SWD. Halting debug support: Optional. Number of watchpoint comparators: 0 to 2, 0 to 4. Number of breakpoint comparators: 0 to 4, 0 to 8; the Cortex-M0 / M0+ / M1 implement the ARMv6-M architecture, the Cortex-M3 implements the ARMv7-M architecture, the Cortex-M4 / Cortex-M7 implements the ARMv7E-M architecture. The architectures are binary instruction upward compatible from ARMv6-M to ARMv7-M to ARMv7E-M. Binary instructions available for the Cortex-M0 / Cortex-M0+ / Cortex-M1 can execute without modification on the Cortex-M3 / Cortex-M4 / Cortex-M7. Binary instructions available for the Cortex-M3 can execute without modification on the Cortex-M4 / Cortex-M7 / Cortex-M33 / Cortex-M35P. Only Thumb-1 and Thumb-2 instruction sets are supported in Cortex-M architectures. All six Cortex-M cores implement a common subset of instructions that consists of most Thumb-1, some Thumb-2, including a 32-bit result multiply.
The Cortex-M0 / Cortex-M0+ / Cortex-M1 / Cortex-M23 were designed to create the smallest silicon die, thus having the fewest instructions of the Cortex-M family. The Cortex-M0 / M0+ / M1 include Th
Market segmentation is the activity of dividing a broad consumer or business market consisting of existing and potential customers, into sub-groups of consumers based on some type of shared characteristics. In dividing or segmenting markets, researchers look for common characteristics such as shared needs, common interests, similar lifestyles or similar demographic profiles; the overall aim of segmentation is to identify high yield segments – that is, those segments that are to be the most profitable or that have growth potential – so that these can be selected for special attention. Many different ways to segment a market have been identified. Business-to-business sellers might segment the market into different types of businesses or countries. While business to consumer sellers might segment the market into demographic segments, lifestyle segments, behavioural segments or any other meaningful segment. Market segmentation assumes that different market segments require different marketing programs – that is, different offers, promotion, distribution or some combination of marketing variables.
Market segmentation is not only designed to identify the most profitable segments, but to develop profiles of key segments in order to better understand their needs and purchase motivations. Insights from segmentation analysis are subsequently used to support marketing strategy development and planning. Many marketers use the S-T-P approach; that is, a market is segmented, one or more segments are selected for targeting, products or services are positioned in a way that resonates with the selected target market or markets. Market segmentation is the process of dividing up mass markets into groups with similar needs and wants; the rationale for market segmentation is that in order to achieve competitive advantage and superior performance, firms should: " identify segments of industry demand, target specific segments of demand, develop specific'marketing mixes' for each targeted market segment. " From an economic perspective, segmentation is built on the assumption that heterogeneity in demand allows for demand to be disaggregated into segments with distinct demand functions.
The business historian, Richard S. Tedlow, identifies four stages in the evolution of market segmentation: Fragmentation: The economy was characterised by small regional suppliers who sold goods on a local or regional basis Unification or mass marketing: As transportation systems improved, the economy became unified. Standardised, branded goods were distributed at a national level. Manufacturers tended to insist on strict standardisation in order to achieve scale economies with a view to penetrating markets in the early stages of a product's lifecycle. E.g. the Model T Ford Segmentation: As market size increased, manufacturers were able to produce different models pitched at different quality points to meet the needs of various demographic and psychographic market segments. This is the era of market differentiation based on demographic, socio-economic and lifestyle factors. Hyper-segmentation: a shift towards the definition of more narrow market segments. Technological advancements in the area of digital communications, allow marketers to communicate with individual consumers or small groups.
This is sometimes known as one-to-one marketing. The practice of market segmentation emerged well before marketers thought about it at a theoretical level. Archaeological evidence suggests that Bronze Age traders segmented trade routes according to geographical circuits. Other evidence suggests that the practice of modern market segmentation was developed incrementally from the 16th century onwards. Retailers, operating outside the major metropolitan cities, could not afford to serve one type of clientele yet retailers needed to find ways to separate the wealthier clientele from the "riff raff". One simple technique was to have a window opening out onto the street from which customers could be served; this allowed the sale of goods without encouraging them to come inside. Another solution, that came into vogue from the late sixteenth century, was to invite favored customers into a back-room of the store, where goods were permanently on display, yet another technique that emerged around the same time was to hold a showcase of goods in the shopkeeper's private home for the benefit of wealthier clients.
Samuel Pepys, for example, writing in 1660, describes being invited to the home of a retailer to view a wooden jack. The eighteenth-century English entrepreneurs, Josiah Wedgewood and Matthew Boulton, both staged expansive showcases of their wares in their private residences or in rented halls to which only the upper classes were invited while Wedgewood used a team of itinerant salesmen to sell wares to the masses. Evidence of early marketing segmentation has been noted elsewhere in Europe. A study of the German book trade found examples of both product differentiation and market segmentation in the 1820s. From the 1880s, German toy manufacturers were producing models of tin toys for specific geographic markets; such activities suggest that basic forms of market segmentation have been practised since the 17th century and earlier. Contemporary market segmentation emerged in the first decades of the twentieth century as marketers responded to two pressing issues. Demographic and purchasing data were available for groups but for indi