SGI Origin 200
The SGI Origin 200, code named Speedo, was an entry-level server computer developed and manufactured by SGI, introduced in October 1996 to accompany their mid-range and high-end Origin 2000. It is based on the same architecture as the Origin 2000 but has an unrelated hardware implementation. At the time of introduction, these systems ran the IRIX 6.4, the IRIX 6.5 operating systems. The Origin 200 was discontinued on 30 June 2002; the Origin 200 consists of two modules. In configurations with two modules, the NUMAlink 2 interconnection fabric is used to connect the two modules together. Using two modules, the Origin 200's capabilities is doubled; the Origin 200 and the Origin 200 GIGAchannel enclosures can be configured as a tower with "skins" that covered the bare metal for cosmetic purposes, or as a rackmountable enclosure compatible with 19- or 21-inch racks. Each module contains seven 3.5-inch drive bays and two 5.25-inch drive bays. In configurations where an Origin 200 GIGAchannel expansion cabinet is used, the module contains a Crosstown board that plugs into the motherboard.
Each module was limited to two CPUs. The motherboard contains the Hub ASIC, a PCI bridge, two SCSI controllers, two UARTs and an Ethernet controller; the PCI bridge provides the PCI bus for the I/O controllers. The processor are located on a PIMM; when first introduced, the Origin 200 supported one or two R10000 processors with 1 or 4 MB L2 cache each. In August 1998, an upgraded PIMM featuring the 225 MHz R10000 processors was introduced. 270 MHz R12000 processors became available. The PIMMs come in two versions: single processor and dual processor, it is not possible to upgrade these systems to a dual processor system by using two single processor PIMMs, as there is only one PIMM connector on the motherboard. The motherboard supports 32 MB to 2 GB of memory through eight DIMM slots organised into four banks. DIMMs with capacities of 16, 32, 64 and 256 MB are supported. DIMMs are installed in pairs; the Origin 200 GIGAchannel is an expansion cabinet that connects to the Origin 200 modules via two XIO cables.
It provides five XIO slots. The GIGAchannel contains a Crossbow ASIC, an eight-port crossbar provides the five datapaths to the five XIO slots and a single datapath to PCI bridge; the remaining two ports on the ASIC are connected to the XIO connectors used to interface the subsystem to the Origin 200 modules. Origin 200 and Origin 200 GIGAchannel Owner's Guide, 007-3708-002, 5 May 1999, Silicon Graphics
The SGI Tezro is a series of high-end computer workstations sold by SGI from 2003 until 2006. Using MIPS CPUs and running IRIX, it is the immediate successor to the SGI Octane line; the systems were produced in both rack-mount and tower versions, the series was released in June 2003 with a list price of US$20,500. The Tezro was released alongside the SGI Onyx4 and rack-mountable Tezros share many components with it, including plastic skins; the rack-mounted Tezros are functionally similar to an Infinite Performance-equipped SGI Onyx350. Tezro marked the return of the original cube logo to SGI machines, it was replaced in 2008 by the SGI Virtu product line. Similar to other SGI systems, the Tezro uses a non-blocking crossbar interconnect to connect all subsystems together. Tezro is based on SGI's Origin 3000 architecture. ARCS is provided as the boot firmware, as with other SGI computer systems of that era. Tezro systems use four 64-bit MIPS R16000 microprocessors; the following R16000 processor types were available options: Node boards from Onyx/Origin 350/3900 systems are compatible and use the same RAM.
For example, a quad-R16K/700 MHz board from a CX-Brick will work in a Tezro. The Tezro shipped with 512MB of DDR SDRAM, it can be expanded using proprietary DIMMs. The tower version can hold up to 8GB of main memory total, the rack version can hold up to 8GB per brick. Tezro supports the VPro V12 graphics options. Dual-channel options were produced for the desktop variants allowing up to two 1920x1200 displays, while dual-head, dual-channel were available for the rack version, allowing a equipped rackmount Tezro to drive up to four 1920x1200 displays at once. Tower systems shipped with analog audio output as standard, PCI cards provide audio capabilities on rack-mountable versions; the number of available 64-bit PCI slots included in a Tezro system depends upon the number of CPUs installed in the system: 7 133/100 MHz slots in two- or four-CPU tower systems 3 133/100 MHz slots in single-CPU tower systems 6 100 MHz slots and two 66 MHz slots in 4U rackmountable systems 2 100 MHz slots and one 66 MHz slot in 2U rackmountable systems.
All PCI slots in each Tezro model are 3.3V card slots. A single U160 SCSI connector was produced for attaching external peripherals, as was an optional FireWire card. Remotely installing SGI IRIX 6.5 from a GNU/Linux server
Itanium is a family of 64-bit Intel microprocessors that implement the Intel Itanium architecture. Intel markets the processors for high-performance computing systems; the Itanium architecture originated at Hewlett-Packard, was jointly developed by HP and Intel. Itanium-based systems have been produced by several other manufacturers. In 2008, Itanium was the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, Power ISA, SPARC. In February 2017, Intel released the current generation, Kittson, to test customers, in May began shipping in volume, it is the last processor of the Itanium family. Intel announced the end of life and product discontinuance of the Itanium CPU family on January 30th, 2019. In 1989, HP determined that Reduced Instruction Set Computing architectures were approaching a processing limit at one instruction per cycle. HP researchers investigated a new architecture named Explicitly Parallel Instruction Computing, that allows the processor to execute multiple instructions in each clock cycle.
EPIC implements a form of long instruction word architecture, in which a single instruction word contains multiple instructions. With EPIC, the compiler determines in advance which instructions can be executed at the same time, so the microprocessor executes the instructions and does not need elaborate mechanisms to determine which instructions to execute in parallel; the goal of this approach is twofold: to enable deeper inspection of the code at compile time to identify additional opportunities for parallel execution, to simplify processor design and reduce energy consumption by eliminating the need for runtime scheduling circuitry. HP believed that it was no longer cost-effective for individual enterprise systems companies such as itself to develop proprietary microprocessors, so it partnered with Intel in 1994 to develop the IA-64 architecture, derived from EPIC. Intel was willing to undertake a large development effort on IA-64 in the expectation that the resulting microprocessor would be used by the majority of enterprise systems manufacturers.
HP and Intel initiated a large joint development effort with a goal of delivering the first product, Merced, in 1998. During development, Intel, HP, industry analysts predicted that IA-64 would dominate in servers and high-end desktops, supplant RISC and complex instruction set computing architectures for all general-purpose applications. Compaq and Silicon Graphics decided to abandon further development of the Alpha and MIPS architectures in favor of migrating to IA-64. Several groups ported operating systems for the architecture, including Microsoft Windows, OpenVMS, Linux, HP-UX, Solaris,Tru64 UNIX, Monterey/64; the latter three were canceled before reaching the market. By 1997, it was apparent that the IA-64 architecture and the compiler were much more difficult to implement than thought, the delivery timeframe of Merced began slipping. Intel announced the official name of the processor, Itanium, on October 4, 1999. Within hours, the name Itanic had been coined on a Usenet newsgroup, a reference to the RMS Titanic, the "unsinkable" ocean liner that sank on her maiden voyage in 1912.
"Itanic" has since been used by The Register, others, to imply that the multibillion-dollar investment in Itanium—and the early hype associated with it—would be followed by its quick demise. By the time Itanium was released in June 2001, its performance was not superior to competing RISC and CISC processors. Itanium competed at the low-end with servers based on x86 processors, at the high-end with IBM POWER and Sun Microsystems SPARC processors. Intel repositioned Itanium to focus on high-end business and HPC computing, attempting to duplicate x86's successful "horizontal" market; the success of this initial processor version was limited to replacing PA-RISC in HP systems, Alpha in Compaq systems and MIPS in SGI systems, though IBM delivered a supercomputer based on this processor. POWER and SPARC remained strong, while the 32-bit x86 architecture continued to grow into the enterprise space, building on economies of scale fueled by its enormous installed base. Only a few thousand systems using the original Merced Itanium processor were sold, due to poor performance, high cost and limited software availability.
Recognizing that the lack of software could be a serious problem for the future, Intel made thousands of these early systems available to independent software vendors to stimulate development. HP and Intel brought the next-generation Itanium 2 processor to market a year later; the Itanium 2 processor was released in 2002, was marketed for enterprise servers rather than for the whole gamut of high-end computing. The first Itanium 2, code-named McKinley, was jointly developed by Intel, it relieved many of the performance problems of the original Itanium processor, which were caused by an inefficient memory subsystem. McKinley contains 221 million transistors, measured 19.5 mm by 21.6 mm and was fabricated in a 180 nm, bulk CMOS process with six layers of aluminium metallization. In 2003, AMD released the Opteron CPU, which implements its own 64-bit architecture called AMD64. Opteron gained rapid acceptance in the enterprise server space because it provided an easy upgrade from x86. Under influence by Microsoft, Intel responded by implementing AMD's x86-64 instruction set architecture instead of IA-64 in its Xeon microprocessors in 2004, resulting in a new indu
SGI Onyx, code named Eveready and Terminator, is a series of visualization systems designed and manufactured by SGI, introduced in 1993 and offered in two models and rackmount. The Onyx's basic system architecture is based on the SGI Challenge servers, but with the notable inclusion of graphics hardware; the Onyx was employed in early 1995 for development kits used to produce software for the Nintendo 64 and, because the technology was so new, the Onyx was noted as the major factor for the impressively high price of US$100,000–US$250,000 for such kits. The Onyx was succeeded by the Onyx2 in 1996 and was discontinued on March 31, 1999; the deskside variant can accept one CPU board, the rackmount variant can take up to six CPU boards. Both models were launched with the IP19 CPU board with one, two or four MIPS R4400 microprocessors with 100 and 150 MHz options and increased to 200 and 250 MHz; the IP21 CPU board was introduced, with one or two R8000 microprocessors at 75 or 90 MHz. SGI introduced the IP25 board with one, two or four R10000 microprocessors at 195 MHz.
The Onyx used the RealityEngine2 or VTX graphics subsystems, InfiniteReality, introduced in 1995. The RealityEngine2 is the original high-end graphics subsystem for the Onyx and was produced in two models; the deskside model has one GE12 board with 12 GE processors, up to four RM4 boards, a DG4 board. The rackmount model is otherwise the same; the VTX graphics subsystem is a cost reduced version of the RealityEngine2, using the same hardware but in a feature reduced configuration that can not be upgraded. It consists of one GE10 board with an RM4 board and a DG2 board; the InfiniteReality succeeded the RealityEngine2 as the high-end graphics subsystem for the Onyx when introduced in 1996. It was produced in two models. POWER Onyx and Onyx Deskside Owner's Guide. POWER Onyx and Onyx Rackmount Owner's Guide
SGI Origin 2000
The SGI Origin 2000 is a family of mid-range and high-end server computers developed and manufactured by Silicon Graphics. They were introduced in 1996 to succeed the SGI POWER Challenge. At the time of introduction, these ran the IRIX operating system version 6.4 and 6.5. A variant of the Origin 2000 with graphics capability is known as the Onyx2. An entry-level variant based on the same architecture but with a different hardware implementation is known as the Origin 200; the Origin 2000 was succeeded by the Origin 3000 in July 2000, was discontinued on June 30, 2002. The family was announced on October 7, 1996; the project was code named Lego, known as SN0, to indicate the first in a series of scalable node architectures, contrasting with previous symmetric multiprocessor architectures in the SGI Challenge series. The Origin 2100 is the same as the other models except that it is not upgradeable to other models; the highest CPU count. Three Origin 2000 models are capable of using 512 CPUs and 512 GB of memory but these were never marketed as a system to customers.
One of the 512-CPU Origin 2000 series was installed at SGI's facility in Eagan, Minnesota for test purposes and the other two were sold to NASA Ames Research Center in Mountain View, California for specialized scientific computing. The 512-CPU Origin 2800s cost $40 million each and the delivery of the Origin 3000 systems, scalable up to 512 or 1024 CPUs at a lower price per performance, made the 512-CPU Origin 2800 obsolete. Several customers bought 256-CPU Origin 2000 series systems, although they were never marketed as a product by SGI either; the largest installation of SGI Origin 2000 series was Accelerated Strategic Computing Initiative Blue Mountain at Los Alamos National Labs. It included 48 Origin 2000 series 128-CPU systems all connected via High Performance Parallel Interface for a total of 6144 processors. At the time it was tested, it placed second on the TOP500 list of fastest computers in the world; that test recorded a sustained 1.6 teraflops. With all nodes connected, it was able to sustain peak of over 2.5 teraflops.
Los Alamos National Laboratory had another 12 Origin 128-CPU system as part of the same testing. The climate simulation laboratory at the National Center for Atmospheric Research had an Origin 2000 system named "Ute" with 128 CPUs, it was delivered on May 18, 1998, decommissioned on July 15, 2002. A smaller system at NCAR was named delivered on March 29, with 16 CPUs; the systems at NASA Ames included the one named for Harvard Lomax with 512 CPUs, one named for Joseph Steger with 128 CPUs, one named for Grace Hopper with 64CPUs, one named for Alan Turing with 24 CPUs. Each Origin 2000 module is based on nodes; each module can contain up to two router boards and twelve XIO options. The modules are mounted inside a deskside enclosure or a rack. Deskside enclosures can only contain one module. In configurations with more than two modules, multiple racks are used. ^1 Figures specified are for maximum configurations. The Origin 200 uses some of the architectural components, but in a different physical realization, not scalable.
An Origin 2000 system is composed of nodes linked together by an interconnection network. It uses the distributed shared memory sometimes called Scalable Shared-Memory Multiprocessing architecture; the Origin 2000 uses NUMAlink for its system interconnect. The nodes are connected to router boards, which use NUMAlink cables to connect to other nodes through their routers; the Origin 2000's network topology is a bristled fat hypercube. In configurations with more than 64 processors, a hierarchical fat hypercube network topology is used instead. Additional NUMAlink cables, called Xpress links can be installed between unused Standard Router ports to reduce latency and increase bandwidth. Xpress links can only be used in systems that have 16 or 32 processors, as these are the only configurations with a network topology that enables unused ports to be used in such a way; the architecture has its roots in the DASH project at Stanford University, led by John L. Hennessy, which included two of the Origin designers.
There are four different router boards used by the Origin 2000. Each successive router board allows a larger amount of nodes to be connected; the Null Router connects two nodes in the same module. A system using the Null Router can not be expanded; the Star Router can connect up to four nodes. It is always used in conjunction with a Standard Router to function correctly; the Standard Router can connect up to 32 nodes. It contains an application specific integrated circuit known as the scalable pipelined interconnect for distributed endpoint routing, which serves as a router for the NUMAlink network; the SPIDER ASIC has six ports, each with a pair of unidirectional links, connected to a crossbar which enables the ports to communicate with one another. The Meta Router is used in conjunction with Standard Routers to connect more than 32 nodes, it can connect up to 64 nodes. Each Origin 2000 node fits on a single 16" by 11" printed circuit board that contains one or two processors, the main memory, the directory memory and the Hub ASIC.
The node board plugs into the backplane through a 300-pad CPOP connector. The connector combines two c
The O2 is an entry-level Unix workstation introduced in 1996 by Silicon Graphics, Inc. to replace their earlier Indy series. Like the Indy, the O2 used a single MIPS microprocessor and was intended to be used for multimedia, its larger counterpart is the SGI Octane. The O2 was SGI's last attempt at a low-end workstation. Known as the "Moosehead" project, the O2 architecture featured a proprietary high-bandwidth Unified Memory Architecture to connect system components. A PCI bus is bridged onto the UMA with one slot available, it had an internal modular construction. Two SCSI drives could be mounted on special caddies and an optional video capture / sound cassette mounted on the far left side; the O2 comes in two distinct CPU flavours. The 200 MHz R5000 CPUs with 1 MB L2-cache are noticeably faster than the 180 MHz R5000s with only 512 KB cache. There is a hobbyist project that has retrofitted a 600 MHz RM7xxx MIPS processor into the O2. There are eight DIMM slots on the motherboard and memory on all O2s is expandable to 1 GB using proprietary 239-pin SDRAM DIMMs.
The Memory & Rendering Engine ASIC contains the memory controller. Memory is accessed via a 133 MHz 144-bit bus, of which 128 bits are for data and the remaining for ECC; this bus is interfaced by a set of buffers to the 66 MHz 256-bit memory system. I/O functionality is provided by the IO Engine ASIC; the ASIC provides a 33-bit PCI-X bus, an ISA bus, two PS/2 ports for keyboard and mouse, a 10/100 Base-T Ethernet port. The PCI-X bus has one slot, but the ISA bus is present for attaching a Super I/O chip to provide serial and parallel ports; the O2 carries an UltraWide SCSI drive subsystem. Older O2's have 4x speed Toshiba CD-ROMs, but any Toshiba SCSI CD-ROM can be used. Units have Toshiba DVD-ROMs; the R5000/RM7000 units have two available drive sleds for SCA UltraWide SCSI hard-disks. Because the R10000/R12000 CPU module has a much higher cooling-fan assembly, the R10000/R12000 units have room for only one drive-sled; the O2 used the CRM chipset developed by SGI for the O2. It was developed to be a low-cost implementation of the OpenGL 1.1 architecture with ARB image extensions in both software and hardware.
The chipset consists of the microprocessor, the ICE, MRE and Display ASICs. All display list and vertex processing, as well as the control of the MRE ASIC is performed by the microprocessor; the ICE ASIC performs the unpacking of pixels as well as operations on pixel data. The MRE ASIC performs texture mapping. Due to the unified memory architecture, the texture and framebuffer memory comes from main memory, resulting in a system that has a variable amount of each memory; the Display Engine generates analog video signals from framebuffer data fetched from the memory for display. Several operating systems support the O2. IRIX 6.3 or 6.5.x. Linux port is working. Both Gentoo and Debian have releases that work on the O2. See the IP32 port page on linux-mips.org. OpenBSD has run on the O2 since OpenBSD 3.7. See the sgi port page. NetBSD has run on the O2 since NetBSD 2.0. It was the first Open Source operating system to be ported to the O2. See the sgimips port page; the SGI O2 has an Imaging and Compression Engine application-specific integrated circuit for processing streaming media and still images.
ICE operates at 66 MHz and contains a R3000-derived microprocessor serving as the scalar unit to which a 128-bit SIMD unit is attached using the MIPS coprocessor interface. ICE operates on eight 16-bit or sixteen 8-bit integers, but still provides a significant amount of computational power which enables the O2 to do video decoding and audio tasks that would require a much faster CPU if done without SIMD instructions. ICE only works with the IRIX operating system, as this is the only system that has drivers capable of taking advantage of this device; the Unified Memory Architecture means that the O2 uses main memory for graphics textures, making texturing polygons and other graphics elements trivial. Instead of transferring textures over a bus to the graphics subsystem, the O2 passes a pointer to the texture in main memory, accessed by the graphics hardware; this makes using large textures easy, makes using streaming video as a texture possible. Since the CPU performs many of geometry calculations, using a faster CPU will increase the speed of a geometry-limited application.
The O2's graphics is known to have slower rasterization speed than the Indigo2's Maximum IMPACT graphics boards, though the Maximum IMPACT graphics is limited to 4 MB of texture memory, which can result in thrashing, whereas the O2 is limited only by available memory. While CPU frequencies of 180 to 400 MHz seem low today, when the O2 was released in 1996, these speeds were on par with or above the current offerings for the x86 family of computers. Imaging On-air TV graphics.