Intel 8086
The 8086 is a 16-bit microprocessor chip designed by Intel between early 1976 and June 8, 1978, when it was released. The Intel 8088, released July 1, 1979, is a modified chip with an external 8-bit data bus, is notable as the processor used in the original IBM PC design, including the widespread version called IBM PC XT; the 8086 gave rise to the x86 architecture, which became Intel's most successful line of processors. On June 5, 2018, Intel released a limited edition CPU celebrating the anniversary of the Intel 8086, called the Intel Core i7-8086K. In 1972, Intel launched the first 8-bit microprocessor, it implemented an instruction set designed by Datapoint corporation with programmable CRT terminals in mind, which proved to be general-purpose. The device needed several additional ICs to produce a functional computer, in part due to it being packaged in a small 18-pin "memory package", which ruled out the use of a separate address bus. Two years Intel launched the 8080, employing the new 40-pin DIL packages developed for calculator ICs to enable a separate address bus.
It has an extended instruction set, source-compatible with the 8008 and includes some 16-bit instructions to make programming easier. The 8080 device, was replaced by the depletion-load-based 8085, which sufficed with a single +5 V power supply instead of the three different operating voltages of earlier chips. Other well known 8-bit microprocessors that emerged during these years are Motorola 6800, General Instrument PIC16X, MOS Technology 6502, Zilog Z80, Motorola 6809; the 8086 project started in May 1976 and was intended as a temporary substitute for the ambitious and delayed iAPX 432 project. It was an attempt to draw attention from the less-delayed 16- and 32-bit processors of other manufacturers and at the same time to counter the threat from the Zilog Z80, which became successful. Both the architecture and the physical chip were therefore developed rather by a small group of people, using the same basic microarchitecture elements and physical implementation techniques as employed for the older 8085.
Marketed as source compatible, the 8086 was designed to allow assembly language for the 8008, 8080, or 8085 to be automatically converted into equivalent 8086 source code, with little or no hand-editing. The programming model and instruction set is based on the 8080. However, the 8086 design was expanded to support full 16-bit processing, instead of the limited 16-bit capabilities of the 8080 and 8085. New kinds of instructions were added as well. Instructions directly supporting nested ALGOL-family languages such as Pascal and PL/M were added. According to principal architect Stephen P. Morse, this was a result of a more software-centric approach than in the design of earlier Intel processors. Other enhancements included microcoded multiply and divide instructions and a bus structure better adapted to future coprocessors and multiprocessor systems; the first revision of the instruction set and high level architecture was ready after about three months, as no CAD tools were used, four engineers and 12 layout people were working on the chip.
The 8086 took a little more than two years from idea to working product, considered rather fast for a complex design in 1976–1978. The 8086 was sequenced using a mixture of random logic and microcode and was implemented using depletion-load nMOS circuitry with 20,000 active transistors, it was soon moved to a new refined nMOS manufacturing process called HMOS that Intel developed for manufacturing of fast static RAM products. This was followed by HMOS-II, HMOS-III versions, a static CMOS version for battery powered devices, manufactured using Intel's CHMOS processes; the original chip measured minimum feature size was 3.2 μm. The architecture was defined by Stephen P. Morse with some help and assistance by Bruce Ravenel in refining the final revisions. Logic designer Jim McKevitt and John Bayliss were the lead engineers of the hardware-level development team and Bill Pohlman the manager for the project; the legacy of the 8086 is enduring in the basic instruction set of today's personal computers and servers.
All internal registers, as well as internal and external data buses, are 16 bits wide, which established the "16-bit microprocessor" identity of the 8086. A 20-bit external address bus provides a 1 MB physical address space; this address space is addressed by means of internal memory "segmentation". The data bus is multiplexed with the address bus in order to fit all of the control lines into a standard 40-pin dual in-line package, it provides a 16-bit I/O address bus. The maximum line
Number One Electronic Switching System
The Number One Electronic Switching System was the first large-scale stored program control telephone exchange or electronic switching system in the Bell System. It was manufactured by Western Electric and first placed into service in Succasunna, New Jersey, in May 1965; the switching fabric was composed of a reed relay matrix controlled by wire spring relays which in turn were controlled by a central processing unit. The 1AESS central office switch was a plug compatible, higher capacity upgrade from 1ESS with a faster 1A processor that incorporated the existing instruction set for programming compatibility, used smaller remreed switches, fewer relays, featured disk storage, it was in service from 1976 to 2017. The voice switching fabric plan was similar to that of the earlier 5XB switch in being bidirectional and in using the call-back principle; the largest full access matrix switches in the system, were 8x8 rather than 10x10 or 20x16. Thus they required eight stages rather than four to achieve large enough junctor groups in a large office.
Crosspoints being more expensive in the new system but switches cheaper, system cost was minimized with fewer crosspoints organized into more switches. The fabric was divided into Line Networks and Trunk Networks of four stages, folded to allow connecting line-to-line or trunk-to-trunk without exceeding eight stages of switching. For a switch with 1000 input customers and 1000 output customers, a full connection would require a matrix of 1000x1000, or 1 million, physical switches for full interconnection possibility; when one considers that a large telephone system can have many more than 1000 x 1000 customers, the hardware to establish a full interconnection can grow and exceed practical implementations. Agner Krarup Erlang first theorized a compromise, based upon the concept that not all telephones lines are connected at the same time. From statistical theory, it is possible to design hardware that can connect most of the calls, in the sense of a high percentage, block others as exceeding the design capacity.
These are referred to as blocking switches and are the most common in modern telephone exchanges. They are implemented as smaller switch fabrics in cascade. In many, a randomizer is used to select the start of a path through the multistage fabric so that the statistical properties predicted by the theory can be gained; each four stage Line Network or Trunk Network was divided into Junctor Switch Frames and either Line Switch Frames in the case of a Line Network, or Trunk Switch Frames in the case of a Trunk Network. Links were designated A, B, C, J for Junctor. A Links were internal to the LSF or TSF. All JSFs had a unity concentration ratio, the number of B links within the network equalled the number of junctors to other networks. Most LSFs had a 4:1 Line Concentration Ratio. In some urban areas 2:1 LSF were used; the B links were multipled to make a higher LCR, such as 3:1 or 5:1. Line Networks always had 1024 Junctors, arranged in 16 grids that each switched 64 junctors to 64 B links. Four grids were grouped for control purposes in each of four LJFs.
TSF had a unity concentration. Thus their B links were multipled to make a Trunk Concentration Ratio of 1.25:1 or 1.5:1, the latter being common in 1A offices. TSFs and JSFs were identical except for their position in the fabric and the presence of a ninth test access level or no-test level in the JSF; each JSF or TSF was divided into 4 two-stage grids. Early TNs had four JSF, for a total of 16 grids, 1024 J links and the same number of B links, with four B links from each Trunk Junctor grid to each Trunk Switch grid. Starting in the mid-1970s, larger offices had their B links wired differently, with only two B links from each Trunk Junctor Grid to each Trunk Switch Grid; this allowed a larger TN, with 8 JSF containing 32 grids, connecting 2048 B links. Thus the junctor groups could be more efficient; these TN had eight TSF, giving the TN a unity trunk concentration ratio. Within each LN or TN, the A, B, C and J links were counted from the outer termination to the inner; that is, for a trunk, the trunk Stage 0 switch could connect each trunk to any of eight A links, which in turn were wired to Stage 1 switches to connect them to B links.
Trunk Junctor grids had Stage 0 and Stage 1 switches, the former to connect B links to C links, the latter to connect C to J links called Junctors. Junctors were gathered into cables, 16 twisted pairs per cable constituting a Junctor Subgroup, running to the Junctor Grouping Frame where they were plugged into cables to other networks; each network had 64 or 128 subgroups, was connected to each other network by one or several subgroups. The original 1ESS Ferreed switching fabric was packaged as separate 8x8 switches or other sizes, tied into the rest of the speech fabric and control circuitry by wire wrap connections; the transmit/receive path of the analog voice signal is through a series of magnetic-latching reed switches. The much smaller Remreed crosspoints, introduced at about the same time as 1AESS, were packaged as grid boxes of four principal types. Type 10A Junctor Grids and 11A Trunk Grids were a box about 16x16x5 inches with sixteen 8x8 switches inside. Type 12A Line Grids with 2:1 LCR were only about 5 inches wide, with eight 4x4 Stage 0 line switches with ferrods and cutoff contacts for 32 lines, co
Nokia
Nokia Corporation is a Finnish multinational telecommunications, information technology, consumer electronics company, founded in 1865. Nokia's headquarters are in the greater Helsinki metropolitan area. In 2017, Nokia employed 102,000 people across over 100 countries, did business in more than 130 countries, reported annual revenues of around €23 billion. Nokia is a public limited company listed on New York Stock Exchange, it is the world's 415th-largest company measured by 2016 revenues according to the Fortune Global 500, having peaked at 85th place in 2009. It is a component of the Euro Stoxx 50 stock market index; the company has had various industries in over 150 years. It was founded as a pulp mill and had long been associated with rubber and cables, but since the 1990s focuses on large-scale telecommunications infrastructures, technology development, licensing. Nokia is a notable major contributor to the mobile telephony industry, having assisted in the development of the GSM, 3G and LTE standards, is best known for having been the largest worldwide vendor of mobile phones and smartphones for a period.
After a partnership with Microsoft and market struggles, its mobile phone business was bought by the former, creating Microsoft Mobile as its successor in 2014. After the sale, Nokia began to focus more extensively on its telecommunications infrastructure business and on the Internet of things, marked by the divestiture of its Here mapping division and the acquisition of Alcatel-Lucent, including its Bell Labs research organization; the company also experimented with virtual reality and digital health, the latter through the purchase of Withings. The Nokia brand has since returned to the mobile and smartphone market through a licensing arrangement with HMD Global. Nokia continues to be a major patent licensor for most large mobile phone vendors; as of 2018 Nokia is the world's third largest network equipment manufacturer. The company was viewed with national pride by Finns, as its successful mobile phone business made it by far the largest worldwide company and brand from Finland. At its peak in 2000, during the telecoms bubble, Nokia alone accounted for 4% of the country's GDP, 21% of total exports, 70% of the Helsinki Stock Exchange market capital.
Nokia's history dates back to 1865, when Finnish-Swede mining engineer Fredrik Idestam established a pulp mill near the town of Tampere, Finland. A second pulp mill was opened in 1868 near the neighboring town of Nokia, offering better hydropower resources. In 1871, together with friend Leo Mechelin, formed a shared company from it and called it Nokia Ab, after the site of the second pulp mill. Idestam retired in 1896. Mechelin expanded into electricity generation by 1902. In 1904 Suomen Gummitehdas, a rubber business founded by Eduard Polón, established a factory near the town of Nokia and used its name. In 1922, Nokia Ab entered into a partnership with Finnish Rubber Works and Kaapelitehdas, all now jointly under the leadership of Polón. Finnish Rubber Works company grew when it moved to the Nokia region in the 1930s to take advantage of the electrical power supply, the cable company soon did too. Nokia at the time made respirators for both civilian and military use, from the 1930s well into the early 1990s.
In 1967, the three companies - Nokia and Finnish Rubber Works - merged and created a new Nokia Corporation, a new restructured form divided into four major businesses: forestry, cable and electronics. In the early 1970s, it entered the radio industry. Nokia started making military equipment for Finland's defence forces, such as the Sanomalaite M/90 communicator in 1983, the M61 gas mask first developed in the 1960s. Nokia was now making professional mobile radios, telephone switches and chemicals. After Finland's trade agreement with the Soviet Union in the 1960s, Nokia expanded into the Soviet market, it soon widened trade. Nokia co-operated on scientific technology with the Soviet Union; the U. S. government became suspicious of that technologic co-operation after the end of the Cold War détente in the early 1980s. Nokia imported many US-made components and used them for the Soviets, according to U. S. Deputy Minister of Defence, Richard Perle, Nokia had a secret co-operation with The Pentagon that allowed the U.
S. to keep track in technologic developments in the Soviet Union through trading with Nokia. However this was a demonstration of Finland trading with both sides, as it was neutral during the Cold War. In 1977, Kari Kairamo became. By this time Finland were becoming what has been called "Nordic Japan". Under his leadership Nokia acquired many companies. In 1984, Nokia acquired television maker Salora, followed by Swedish electronics and computer maker Luxor AB in 1985, French television maker Oceanic in 1987; this made Nokia the third-largest television manufacturer of Europe. The existing brands continued to be used until the end of the television business in 1996. In 1987, Nokia acquired Schaub-Lorenz, the consumer operations of Germany's Standard Elektrik Lorenz, which included its "Schaub-Lorenz" and "Graetz" brands, it was part of American conglomerate Internationa
DMS-100
The DMS-100 Switch Digital Multiplex System was a line of telephone exchange switches manufactured by Northern Telecom. Designed during the 1970s and released in 1979, it can control 100,000 telephone lines; the purpose of the DMS-100 Switch is to provide local service and connections to the PSTN public telephone network. It is designed to deliver services over subscribers' telephone trunks, it provides Plain Old Telephone Service, mobility management for cellular phone systems, sophisticated business services such as Automatic Call Distribution, Integrated Services Digital Network, Meridian Digital Centrex called Integrated Business Network. It provides Intelligent Network functions, it is used in countries throughout the world. Much of the hardware used in the DMS-100, with the possible exception of the Line Cards, is used in other members of the DMS family, including the DMS-200 Toll switch. All power distribution is at -48 VDC, from which DC to DC converters on every shelf provide other necessary voltages.
The Central Control Complex comprises the Central Processing Unit, Program Store, Data Store and the Central Message Controller. The CPU contains two identical 16-bit processors running in hot standby mode; the original CPU core was referred to as the NT40 CPU and was implemented in 250 discrete logic devices across several circuit boards running at 36 MHz. The NT40 core consisted of the NT1X44 stack card, which provides some register and stack functions of the processor, the NT1X45 which contained the arithmetic and logic functions, the NT1X46 which provides more registers and the load-route read-only memory and the NT1X47 timing and control card which provides the micro-cycle source and microstore decoding functions of the processor; the NT1X47 card contained the 2-digit hexadecimal display to indicate test result codes and the condition of the core. The NT1X48 processor maintenance card contained a thumbwheel on the faceplate to enable various diagnostic tests of the CPU. A modification of these same five circuit boards with faster pin-compatible discrete logic devices enabled the CPU to operate at 40 MHz allowing central offices to improve call throughput capacity by 10 percent.
When the CPU is configured in dual hot standby mode, a mate exchange bus between the two CPUs enables the state of one CPU to be continuously compared to that of the other CPU on a cycle by cycle basis. Any discrepancy between the two CPUs results in maintenance circuitry determining which CPU is at fault and activity to change to the same CPU. A Program Store is dedicated to each CPU and is a memory for the program instructions required by that CPU for processing calls and for administrative tasks; the PS associated with the other CPU contains identical program instructions. A Data Store is dedicated with each CPU and contains dynamic information on a per-call basis, as well as customer data and office-specific settings; the other CPU is associated with its own DS containing duplicate data. The Central Message Controller controls the flow of messages between the other units of the CCC and prioritizes them for the Network Message Controller in the various Network Modules, or the Input/Output Controller.
Both CPUs have access to either CMC which share the message load to peripherals. The original NT40 based CCC was replaced by the compatible DMS SuperNode in 1987; the DMS SuperNode Computing Module was first based on the Motorola 68020 Central Processing Unit and upgraded to the Motorola 68030. In the early 1990s it was further upgraded to use the Motorola 88100 and 88110 Reduced Instruction Set Computing CPUs; this RISC version of the SuperNode Computing Module was known as the BRISC CPU. With the BRISC CPU the DMS SuperNode had a processing capacity of 1,500,000 call attempts per hour. DMS SuperNode featured increased processing capacity across a distributed architecture allowing for the development of new features and services; each of the elements of the DMS SuperNode uses a common SuperNode CPU hardware design differing only in the software used to control them. The SuperNode consists of two main elements: DMS Bus. DMS Core provides the main computing facility and is made up of the Compute Module, System Load Module and a Message Controller.
The Compute Module contains redundant SuperNode CPUs to handle call processing and maintenance functions and, like the NT40 core, can operate in a synchronized mode with its mate. The System Load Module contains all the necessary software for every element of the DMS switch and provides file system and data storage functions on magnetic tape and hard disk; the Message Controller provides communications links between the DMS Bus. DMS Bus is used to interconnect the DMS Core, the switching network and the Input/Output controller and manage message flows between these units and consists of redundant Message Switches; the Message Switches of the DMS Bus operate in a load-sharing mode and one of them provides the main clock source for the DMS-100 system while the others are synchronized to it. Messages between all SuperNode units are carried by optical DS512 links; the operating system used by both generations of the DMS-100 switch was called Support Operating System and was written in a high level language called PROTEL which stood for PRocedure Oriented Type Enforcing Language developed at Bell Northern Research.
Hardware and maintenance are administered locally through cathode-ray terminals, through a multilevel menu system called MAPCI. There are various methods used to access the DMS remotely as well, including telnet. Ba
Computer memory
In computing, memory refers to the computer hardware integrated circuits that store information for immediate use in a computer. Computer memory operates at a high speed, for example random-access memory, as a distinction from storage that provides slow-to-access information but offers higher capacities. If needed, contents of the computer memory can be transferred to secondary storage. An archaic synonym for memory is store; the term "memory", meaning "primary storage" or "main memory", is associated with addressable semiconductor memory, i.e. integrated circuits consisting of silicon-based transistors, used for example as primary storage but other purposes in computers and other digital electronic devices. There are two main kinds of semiconductor memory and non-volatile. Examples of non-volatile memory are ROM, PROM, EPROM and EEPROM memory. Examples of volatile memory are primary storage, dynamic random-access memory, fast CPU cache memory, static random-access memory, fast but energy-consuming, offering lower memory areal density than DRAM.
Most semiconductor memory is organized into memory cells or bistable flip-flops, each storing one bit. Flash memory organization includes multiple bits per cell; the memory cells are grouped into words of fixed word length, for example 1, 2, 4, 8, 16, 32, 64 or 128 bit. Each word can be accessed by a binary address of N bit, making it possible to store 2 raised by N words in the memory; this implies that processor registers are not considered as memory, since they only store one word and do not include an addressing mechanism. Typical secondary storage devices are solid-state drives. In the early 1940s, memory technology permitted a capacity of a few bytes; the first electronic programmable digital computer, the ENIAC, using thousands of octal-base radio vacuum tubes, could perform simple calculations involving 20 numbers of ten decimal digits which were held in the vacuum tube accumulators. The next significant advance in computer memory came with acoustic delay line memory, developed by J. Presper Eckert in the early 1940s.
Through the construction of a glass tube filled with mercury and plugged at each end with a quartz crystal, delay lines could store bits of information in the form of sound waves propagating through mercury, with the quartz crystals acting as transducers to read and write bits. Delay line memory would be limited to a capacity of up to a few hundred thousand bits to remain efficient. Two alternatives to the delay line, the Williams tube and Selectron tube, originated in 1946, both using electron beams in glass tubes as means of storage. Using cathode ray tubes, Fred Williams would invent the Williams tube, which would be the first random-access computer memory; the Williams tube would prove less expensive. The Williams tube would prove to be frustratingly sensitive to environmental disturbances. Efforts began in the late 1940s to find non-volatile memory. Jay Forrester, Jan A. Rajchman and An Wang developed magnetic-core memory, which allowed for recall of memory after power loss. Magnetic core memory would become the dominant form of memory until the development of transistor-based memory in the late 1960s.
Developments in technology and economies of scale have made possible so-called Very Large Memory computers. The term "memory" when used with reference to computers refers to random-access memory. Volatile memory is computer memory. Most modern semiconductor volatile memory is either static RAM or dynamic RAM. SRAM retains its contents as long as the power is connected and is easy for interfacing, but uses six transistors per bit. Dynamic RAM is more complicated for interfacing and control, needing regular refresh cycles to prevent losing its contents, but uses only one transistor and one capacitor per bit, allowing it to reach much higher densities and much cheaper per-bit costs. SRAM is not worthwhile for desktop system memory, where DRAM dominates, but is used for their cache memories. SRAM is commonplace in small embedded systems. Forthcoming volatile memory technologies that aim at replacing or competing with SRAM and DRAM include Z-RAM and A-RAM. Non-volatile memory is computer memory that can retain the stored information when not powered.
Examples of non-volatile memory include read-only memory, flash memory, most types of magnetic computer storage devices, optical discs, early computer storage methods such as paper tape and punched cards. Forthcoming non-volatile memory technologies include FERAM, CBRAM, PRAM, STT-RAM, SONOS, RRAM, racetrack memory, NRAM, 3D XPoint, millipede memory. A third category of memory is "semi-volatile"; the term is used to describe a memory which has some limited non-volatile duration after power is removed, but data is lost. A typical goal when using a semi-volatile memory is to provide high performance/durability/etc. Associated with volatile memories, while providing some benefits of a true non-volatile memory. For example, some non-volatile memory types can wear out, where a "worn" cell has increased volatility but otherwise continues to work. Data locations which are written
Magnetic tape data storage
Magnetic tape data storage is a system for storing digital information on magnetic tape using digital recording. Modern magnetic tape is most packaged in cartridges and cassettes; the device that performs writing or reading of data is a tape drive. Autoloaders and tape libraries automate cartridge handling. For example, a common cassette-based format is Linear Tape-Open, which comes in a variety of densities and is manufactured by several companies. Although magnetic tape was primarily for data storage, newer uses included system backup, data archive and data exchange. Magnetic tape for data storage was wound on 10.5-inch reels. This de facto standard for large computer systems persisted through the late 1980s, with increasing capacity due to thinner substrates and changes in encoding. Tape cartridges and cassettes were available starting in the mid-1970s and were used with small computer systems. With the introduction of the IBM 3480 cartridge in 1984, described as "about one-fourth the size... yet it stored up to 20 percent more data," large computer systems started to move away from open reel tapes and towards cartridges.
Magnetic tape was first used to record computer data in 1951 on the Eckert-Mauchly UNIVAC I. The UNISERVO drive recording medium was a thin metal strip of 0.5-inch wide nickel-plated phosphor bronze. Recording density was 128 characters per inch on eight tracks at a linear speed of 100 in/s, yielding a data rate of 12,800 characters per second. Of the eight tracks, six were data, one was a parity track, one was a clock, or timing track. Making allowances for the empty space between tape blocks, the actual transfer rate was around 7,200 characters per second. A small reel of mylar tape provided separation from the read/write head. IBM computers from the 1950s used ferrous-oxide coated tape similar to that used in audio recording. IBM's technology soon became the de facto industry standard. Magnetic tape dimensions were 0.5-inch wide and wound on removable reels up to 10.5 inches in diameter. Different tape lengths were available with 1,200 feet and 2,400 feet on mil and one half thickness being somewhat standard.
During the 1980s, longer tape lengths such as 3,600 feet became available using a much thinner PET film. Most tape drives could support a maximum reel size of 10.5 inches. CDC used IBM compatible 1/2 inch magnetic tapes, but offered a 1 inch wide variant, with 14 tracks in the CDC 626 drive. A so-called mini-reel was common for smaller data sets, such as for software distribution; these were 7-inch reels with no fixed length—the tape was sized to fit the amount of data recorded on it as a cost-saving measure. Early IBM tape drives, such as the IBM 727 and IBM 729, were mechanically sophisticated floor-standing drives that used vacuum columns to buffer long u-shaped loops of tape. Between servo control of powerful reel motors, a low-mass capstan drive, the low-friction and controlled tension of the vacuum columns, fast start and stop of the tape at the tape-to-head interface could be achieved: 1.5 ms from stopped tape to full speed of 112.5 inches per second. The fast acceleration is possible.
When active, the two tape reels thus fed tape into or pulled tape out of the vacuum columns, intermittently spinning in rapid, unsynchronized bursts resulting in visually striking action. Stock shots of such vacuum-column tape drives in motion were used to represent "the computer" in movies and television. Early half-inch tape had seven parallel tracks of data along the length of the tape, allowing six-bit characters plus one bit of parity written across the tape; this was known as seven-track tape. With the introduction of the IBM System/360 mainframe, nine-track tapes were introduced to support the new 8-bit characters that it used. Recording density increased over time. Common seven-track densities started at 200 six-bit characters per inch 556, 800. Nine-track tapes had densities of 800 1600, 6250; this translates into about 5 megabytes to 140 megabytes per standard length reel of tape. The end of a file was designated by a special recorded pattern called a tape mark, end of the recorded data on a tape by two successive tape marks.
The physical beginning and end of usable tape was indicated by reflective adhesive strips of aluminum foil placed on the back side. At least due to the success of the S/360, the resultant standardization on 8-bit character codes and byte addressing, nine-track tapes were widely used throughout the computer industry during the 1970s and 1980s. LINCtape, its derivative, DECtape, were variations on this "round tape", they were a personal storage medium. The tape was 0.75 inches wide and featured a fixed formatting track which, unlike standard tape, made it feasible to read and rewrite blocks in place. LINCtapes and DECtapes had similar capacity and data transfer rate to the diskettes that displaced them, but their "seek times" were on the order of thirty seconds to a minute. In the context of magnetic tape, the term cassette refers to an enclosure that holds two reels with a single span of magnetic tape; the term cartridge is more generic, but means a single reel of tape in a plastic enclosure. The type o
Integrated Services Digital Network
Integrated Services Digital Network is a set of communication standards for simultaneous digital transmission of voice, video and other network services over the traditional circuits of the public switched telephone network. It was first defined in 1988 in the CCITT red book. Prior to ISDN, the telephone system was viewed as a way to transport voice, with some special services available for data; the key feature of ISDN is that it integrates speech and data on the same lines, adding features that were not available in the classic telephone system. The ISDN standards define several kinds of access interfaces, such as Basic Rate Interface, Primary Rate Interface, Narrowband ISDN, Broadband ISDN. ISDN is a circuit-switched telephone network system, which provides access to packet switched networks, designed to allow digital transmission of voice and data over ordinary telephone copper wires, resulting in better voice quality than an analog phone can provide, it offers circuit-switched connections, packet-switched connections, in increments of 64 kilobit/s.
In some countries, ISDN found major market application for Internet access, in which ISDN provides a maximum of 128 kbit/s bandwidth in both upstream and downstream directions. Channel bonding can achieve a greater data rate. ISDN is employed as data-link and physical layers in the context of the OSI model. In common use, ISDN is limited to usage to Q.931 and related protocols, which are a set of signaling protocols establishing and breaking circuit-switched connections, for advanced calling features for the user. They were introduced in 1986. In a videoconference, ISDN provides simultaneous voice and text transmission between individual desktop videoconferencing systems and group videoconferencing systems. Integrated services refers to ISDN's ability to deliver at minimum two simultaneous connections, in any combination of data, voice and fax, over a single line. Multiple devices can be attached to the line, used as needed; that means an ISDN line can take care of what were expected to be most people's complete communications needs at a much higher transmission rate, without forcing the purchase of multiple analog phone lines.
It refers to integrated switching and transmission in that telephone switching and carrier wave transmission are integrated rather than separate as in earlier technology. The entry level interface to ISDN is the Basic Rate Interface, a 128 kbit/s service delivered over a pair of standard telephone copper wires; the 144 kbit/s overall payload rate is divided into two 64 kbit/s bearer channels and one 16 kbit/s signaling channel. This is sometimes referred to as 2B+D; the interface specifies the following network interfaces: The U interface is a two-wire interface between the exchange and a network terminating unit, the demarcation point in non-North American networks. The T interface is a serial interface between a computing device and a terminal adapter, the digital equivalent of a modem; the S interface is a four-wire bus. The R interface defines the point between a non-ISDN device and a terminal adapter which provides translation to and from such a device. BRI-ISDN is popular in Europe but is much less common in North America.
It is common in Japan — where it is known as INS64. The other ISDN access available is the Primary Rate Interface, carried over T-carrier with 24 time slots in North America, over E-carrier with 32 channels in most other countries; each channel provides transmission at a 64 kbit/s data rate. With the E1 carrier, the available channels are divided into 30 bearer channels, one data channel, one timing and alarm channel; this scheme is referred to as 30B+2D. In North America, PRI service is delivered via T1 carriers with only one data channel referred to as 23B+D, a total data rate of 1544 kbit/s. Non-Facility Associated Signalling allows two or more PRI circuits to be controlled by a single D channel, sometimes called 23B+D + n*24B. D-channel backup allows for a second D channel in case the primary fails. NFAS is used on a Digital Signal 3. PRI-ISDN is popular throughout the world for connecting private branch exchanges to the public switched telephone network. Though many network professionals use the term ISDN to refer to the lower-bandwidth BRI circuit, in North America BRI is uncommon whilst PRI circuits serving PBXs are commonplace.
The bearer channel is a standard 64 kbit/s voice channel of 8 bits sampled at 8 kHz with G.711 encoding. B-channels can be used to carry data, since they are nothing more than digital channels; each one of these channels is known as a DS0. Most B channels can carry a 64 kbit/s signal, but some were limited to 56K because they traveled over RBS lines; this has since become less so. X.25 can be carried over the B or D channels of a BRI line, over the B channels of a PRI line. X.25 over the D channel is used at many point-of-sale terminals because it eliminates the modem setup, because it connects to the central system over a B channel, thereby eliminating the need for modems and making much better use of the central system's telephone lines. X.25 was part of an ISDN protocol
