Sempron
Sempron has been the marketing name used by AMD for several different budget desktop CPUs, using several different technologies and CPU socket formats. The Sempron replaced the AMD Duron processor and competes against Intel's Celeron series of processors. AMD coined the name from the Latin semper, which means "always", to suggest the Sempron is suitable for "daily use and part of everyday life"; the first Sempron CPUs were based on the Athlon XP architecture using the Thoroughbred or Thorton core. These models were equipped with 256 KiB L2 cache and 166 MHz Front side bus. Thoroughbred cores natively had 256 KiB L2 cache, but Thortons had 512 KiB L2 cache, half of, disabled and could sometimes be reactivated with a slight physical modification to the chip. AMD introduced the Sempron 3000+ CPU, based on the Barton core with 512 KiB L2 cache. From a hardware and user standpoint, the Socket A Sempron CPUs were identical to Athlon XP desktop CPUs with a new brand name. AMD has ceased production of all Socket A Sempron CPUs.
The second generation was based on the architecture of the Socket 754 Athlon 64. Some differences from Athlon 64 processors include a reduced cache size, the absence of AMD64 support in earlier models. Apart from these differences, the Socket 754 Sempron CPUs share most features with the more powerful Athlon 64, including an integrated memory controller, the HyperTransport link, AMD's "NX bit" feature. In the second half of 2005, AMD added 64-bit support to the Sempron line; some journalists refer to this revision of chips as "Sempron 64" to distinguish it from the previous revision. AMD's intent in releasing 64-bit entry-level processors was to extend the market for 64-bit processors, which at the time of Sempron 64's first release, was a niche market. In 2006, AMD announced the Socket Socket S1 line of Sempron processors; these are functionally equivalent to the previous generation, except they have a dual-channel DDR2 SDRAM memory controller which replaces the single-channel DDR SDRAM version.
The TDP of the standard version remains at 62 W, while the new "Energy Efficient Small Form Factor" version has a reduced 35 W TDP. The Socket AM2 version does not require a minimum voltage of 1.1 volts to operate, whereas all socket 754 Semprons with Cool'n'Quiet did. In 2006, AMD was selling both Socket Socket AM2 Sempron CPUs concurrently. In the middle of 2007 AMD is shipping AM2 and S1 Semprons. L1-Cache: 64 + 64 KiB L2-Cache: 256 KiB, full speed MMX, 3DNow!, SSE Socket A Front side bus: 166 MHz VCore: 1.6 V First release: July 28, 2004 Clockrate: 1500 MHz – 2000 MHz L1-Cache: 64 + 64 KiB L2-Cache: 512 KiB, full speed MMX, 3DNow!, SSE Socket A Front side bus: 166 MHz – 200 MHz VCore: 1.6 – 1.65 V First release: September 17, 2004 Clockrate: 2000–2200 MHz L1-Cache: 64 + 64 KiB L2-Cache: 256 KiB, full speed MMX, 3DNow!, SSE, SSE2 Enhanced Virus Protection Integrated 72-bit DDR memory controller Socket 754, 800 MHz HyperTransport VCore: 1.4 V First release: July 28, 2004 Clockrate: 1800 MHz Stepping: CG Early models are downlabeled "Oakville" mobile Athlon64 L1-Cache: 64 + 64 KiB L2-Cache: 128/256 KiB, full speed MMX, 3DNow!, SSE, SSE2 SSE3 support on E3 and E6 steppings AMD64 on E6 stepping Cool'n'Quiet Enhanced Virus Protection Integrated 72-bit DDR memory controller Socket 754, 800 MHz HyperTransport VCore: 1.4 V First release: February 2005 Clockrate: 1400–2000 MHz 128 KiB L2-Cache 256 KiB L2-Cache Steppings: D0, E3, E6 L1-Cache: 64 + 64 KiB L2-Cache: 128/256 KiB, full speed MMX, 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit Integrated 144-bit DDR memory controller Socket 939, 800 MHz HyperTransport VCore: 1.35/1.4 V First release: October 2005 Clockrate: 1800–2000 MHz 128 KiB L2-Cache 256 KiB L2-Cache Steppings: E3, E6 L1-Cache: 64 + 64 KiB L2-Cache: 128/256 KiB, full speed MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit Integrated 128-bit DDR2 memory controller Socket AM2, 800 MHz HyperTransport VCore: 1.25/1.35/1.40 V First release: May 23, 2006 Clockrate: 1600–2200 MHz 128 KiB L2-Cache 256 KiB L2-Cache Stepping: F2 L1-Cache: 64 + 64 KiB L2-Cache: 256/512 KiB, full speed MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, Cool'n'Quiet, NX bit Integrated 128-bit DDR2 memory controller Socket AM2, 800 MHz HyperTransport VCore: 1.20/1.40 V First release: August 20, 2007 Clockrate: 1900–2300 MHz 256 KiB L2-Cache 512 KiB L2-Cache Stepping: G1, G2 Chip harvests from Regor with one core disabled Core Speed – 2600–2900 Max Temps: 63 VCore: 1.35 V TDP: 45 W L1 Cache Size 128 L2 Cache Size 1024 CPU Arch: 1 CPU – 1 Cores – 1 Threads CPU EXT: MMX 3DNow!
SSE SSE2 SSE3 SSE4A x86-64 AMD-V, Cool'n'Quiet, NX bit Integrated 128-bit DDR2 + DDR3 Memory Controller Socket AM3, 2000 MHz HyperTransport Steppings: C2, C3
Athlon
Athlon is the brand name applied to a series of x86-compatible microprocessors designed and manufactured by Advanced Micro Devices. The original Athlon was the first seventh-generation x86 processor and was the first desktop processor to reach speeds of one gigahertz, it made its debut on June 23, 1999. AMD has continued using the Athlon name with the 64-bit Athlon 64 architecture, the Athlon II, Accelerated Processing Unit chips targeting the Socket AM1 desktop SoC architecture, Socket AM4 Zen microarchitecture. Athlon comes from the Ancient Greek ἆθλον meaning " contest", or "prize of a contest", or "place of a contest. AMD founder Jerry Sanders aggressively pursued strategic partnerships and engineering talent in the late 1990s, desiring to leverage the success AMD had gained in the PC market with the preceding AMD K6 line of processors. One major partnership announced in 1998 paired AMD with semiconductor giant Motorola to co-develop copper-based semiconductor technology, resulted with the K7 project being the first commercial processor to utilize copper fabrication technology.
In the announcement, Sanders referred to the partnership as creating a "virtual gorilla" that would enable AMD to compete with Intel on fabrication capacity while limiting AMD's financial outlay for new facilities. The K7 design team was led by Dirk Meyer, who had worked as a lead engineer at DEC on multiple Alpha microprocessors during his employment at DEC; when DEC was sold to Compaq in 1998, the company discontinued Alpha processor development. Sanders approached many of the Alpha engineering staff as Compaq/DEC wound down their semiconductor business, was able to bring in nearly all of the Alpha design team; the K7 engineering design team was thus now consisted of both the acquired NexGen K6 team and the nearly complete Alpha design team. In August 1999, AMD released the Athlon processor. By working with Motorola, AMD was able to refine copper interconnect manufacturing to the production stage about one year before Intel; the revised process permitted 180-nanometer processor production. The accompanying die-shrink resulted in lower power consumption, permitting AMD to increase Athlon clock speeds to the 1 GHz range.
Yields on the new process exceeded expectations, permitting AMD to deliver high speed chips in volume in March 2000. The Athlon architecture used the EV6 bus licensed from DEC as its main system bus. Intel required licensing to use the GTL+ bus used by its Slot 1 Pentium II and processors. By licensing the EV6 bus used by the Alpha line of processors from DEC, AMD was able to develop its own chipsets and motherboards, avoid being dependent on licensing from its direct competitor. Internally, the Athlon is a seventh generation x86 processor, the first of its kind. Like the AMD K5 and K6, the Athlon dynamically buffers internal micro-instructions at runtime resulting from parallel x86 instruction decoding; the CPU is an out-of-order design, again like previous post-5x86 AMD CPUs. The Athlon utilizes the Alpha 21264's EV6 bus architecture with double data rate technology; this means that at 100 MHz, the Athlon front side bus transfers at a rate similar to a 200 MHz single data rate bus, superior to the method used on Intel's Pentium III.
AMD designed the CPU with more robust x86 instruction decoding capabilities than that of K6, to enhance its ability to keep more data in-flight at once. The Athlon's three decoders could decode three x86 instructions to six microinstructions per clock, although this was somewhat unlikely in real-world use; the critical branch predictor unit, essential to keeping the pipeline busy, was enhanced compared to what was on board the K6. Deeper pipelining with more stages allowed higher clock speeds to be attained. Whereas the AMD K6-III+ topped out at 570 MHz due to its short pipeline when built on the 180 nm process, the Athlon was capable of clocking much higher. AMD ended its long-time handicap with floating point x87 performance by designing a super-pipelined, out-of-order, triple-issue floating point unit; each of its three units was tailored to be able to calculate an optimal type of instructions with some redundancy. By having separate units, it was possible to operate on more than one floating point instruction at once.
This FPU was a huge step forward for AMD. While the K6 FPU had looked anemic compared to the Intel P6 FPU, with Athlon this was no longer the case; the 3DNow! Floating point SIMD technology, again present, received some revisions and a name change to "Enhanced 3DNow!". Additions included DSP instructions and an implementation of the extended MMX subset of Intel SSE; the Athlon's CPU cache consisted of the typical two levels. Athlon was the first x86 processor with a 128 kB split level 1 cache; this cache was double the size of K6's large 2×32 kB cache, quadruple the size of Pentium II and III's 2×16 kB L1 cache. The initial Athlon used 512 kB of level 2 cache separate from the CPU, on the processor cartridge board, running at 50% to 33% of core speed; this was done because the 250 nm manufacturing process was too large to allow for on-die cache while maintaining cost-effective die size. Athlon CPUs, afforded greater transistor budgets by smaller 180 nm and 130 nm process nodes, moved to on-die L2 cache at full CPU clock speed.
The AMD Athlon processor launched on June 23, 1999, with general availability by August'99. It launched at 500 MHz and was, on average, 10% faster than the Pent
Pentium III
The Pentium III brand refers to Intel's 32-bit x86 desktop and mobile microprocessors based on the sixth-generation P6 microarchitecture introduced on February 26, 1999. The brand's initial processors were similar to the earlier Pentium II-branded microprocessors; the most notable differences were the addition of the SSE instruction set, the introduction of a controversial serial number embedded in the chip during the manufacturing process. After the release of the Pentium 4 in late 2000, the Pentium III continued to be produced until March 2003. To the Pentium II it superseded, the Pentium III was accompanied by the Celeron brand for lower-end versions, the Xeon for high-end derivatives; the Pentium III was superseded by the Pentium 4, but its Tualatin core served as the basis for the Pentium M CPUs, which used many ideas from the P6 microarchitecture. Subsequently, it was the Pentium M microarchitecture of Pentium M branded CPUs, not the NetBurst found in Pentium 4 processors, that formed the basis for Intel's energy-efficient Core microarchitecture of CPUs branded Core 2, Pentium Dual-Core and Xeon.
The first Pentium III variant was the Katmai. It was a further development of the Deschutes Pentium II; the Pentium III saw an increase of 2 million transistors over the Pentium II. The differences were the addition of execution units and SSE instruction support, an improved L1 cache controller, which were responsible for the minor performance improvements over the "Deschutes" Pentium IIs, it was first released at speeds of 450 and 500 MHz in February 1999. Two more versions were released: 550 MHz on May 17, 1999 and 600 MHz on August 2, 1999. On September 27, 1999 Intel released the 600B running at 533 & 600 MHz respectively. The'B' suffix indicated that it featured a 133 MHz FSB, instead of the 100 MHz FSB of previous models; the Katmai contains 9.5 million transistors, not including the 512 Kbytes L2 cache, has dimensions of 12.3 mm by 10.4 mm. It is fabricated in Intel's P856.5 process, a 0.25 micrometre CMOS process with five levels of aluminum interconnect. The Katmai used the same slot-based design as the Pentium II but with the newer SECC2 cartridge that allowed direct CPU core contact with the heat sink.
There have been some early models of the Pentium III with 450 and 500 MHz packaged in an older SECC cartridge intended for OEMs. A notable stepping for enthusiasts was SL35D; this version of Katmai was rated for 450 MHz, but contained cache chips for the 600 MHz model and thus was capable of running at 600 MHz. The second version, codenamed Coppermine, was released on October 25, 1999, running at 500, 533, 550, 600, 650, 667, 700, 733 MHz. From December 1999 to May 2000, Intel released Pentium IIIs running at speeds of 750, 800, 850, 866, 900, 933 and 1000 MHz. Both 100 MHz FSB and 133 MHz FSB models were made. For models that were available with the same frequency, an "E" was appended to the model name to indicate cores using the new 0.18 μm fabrication process. An additional "B" was appended to designate 133 MHz FSB models, resulting in an "EB" suffix. In terms of overall performance, the Coppermine held a slight advantage over the AMD Athlons it was released against, reversed when AMD applied their own die shrink and added an on-die L2 cache to the Athlon.
Athlon held the advantage in floating-point intensive code, while the Coppermine could perform better when SSE optimizations were used, but in practical terms there was little difference in how the two chips performed, clock-for-clock. However, AMD were able to clock the Athlon higher, reaching speeds of 1.2 GHz before the launch of the Pentium 4. In terms of performance, Coppermine arguably marked a bigger step than Katmai by introducing an on-chip L2 cache; the ATC operates at the core clock rate and has a capacity of 256 KB, twice that of the on-chip cache seen on Mendocino Celerons. It is eight-way set-associative and is accessed via a Double Quad Word Wide 256-bit bus, four times as wide as Katmai's. Furthermore, latency was dropped to a quarter compared to Katmai. Another marketing term by Intel was Advanced System Buffering, which encompassed improvements to better take advantage of a 133 MHz system bus; these include 8 bus queue entries and 4 write-back buffers. Under competitive pressure from the AMD Athlon, Intel re-worked the internals removing some well-known pipeline stalls.
The result was that applications affected by these pipeline stalls ran faster on the Coppermine by up to 30%. The Coppermine was fabricated in a 0.18 µm process. Although its codename could give the impression that it used copper interconnects, its interconnects were in fact aluminium; the Coppermine was available in 370-pin FC-PGA or FC-PGA2 for use with Socket 370, or in SECC2 for Slot 1. FC-PGA and Slot 1 Coppermine CPUs have an exposed die, however most higher frequency SKUs starting with the 866 MHz model were produced in FC-PGA2 variants that feature an integrated heat spreader; this in itself did not improve thermal conductivity, since it added another layer of metal and thermal paste between the die and the heatsink, but it assisted in holding the heatsink flat against the die. Earlier Coppermines without the IHS made he
Socket A
Socket A is the CPU socket used for AMD processors ranging from the Athlon Thunderbird to the Athlon XP/MP 3200+, AMD budget processors including the Duron and Sempron. Socket A supports AMD Geode NX embedded processors; the socket is a zero insertion force pin grid array type with 462 pins. The front side bus frequencies supported for the AMD Athlon XP and Sempron are 133 MHz, 166 MHz, 200 MHz. Socket A supports 32-bit CPUs only. Socket A was replaced by Socket 754 and Socket 939 during 2003 and 2004 except for its use with Geode NX processors. Support of processor clock-speeds between 600 MHz to 2333 MHz Double data rate 100, 133, 166 and 200 MHz front side bus on Duron, XP and Sempron processors, based on the Alpha 21264 EV6 bus. Launched with 100 MHz FSB support in the earliest chipsets it evolved stepwise to faster 200 MHz FSB while maintaining pin compatibility throughout its lifetime. However, timing, BIOS and voltage differences restrict compatibility between older chipsets and processors.
Socket dimensions are 5.59 cm x 6.55 cm or 2.2" x 2.58". AMD recommends. Heavier coolers may result in damage to the die. All socket A processors have the following mechanical maximum load limits which should not be exceeded during heatsink assembly, shipping conditions, or standard use. Load above those limits may crack the processor make it unusable; those load limits are quite small compared to the load limits of Socket 478 processors. Indeed, they were so small that many users ended up with cracked processors while trying to remove or attach heatsinks to their fragile processor core; this made installing non-certified heatsink solutions a risky business. List of AMD microprocessors
Celeron
Celeron is a brand name given by Intel to a number of different low-end IA-32 and x86-64 computer microprocessor models targeted at low-cost personal computers. Celeron processors are compatible with IA-32 computer programs, but their performance is significantly lower when compared to similar CPUs with higher-priced Intel CPU brands. For example, the Celeron brand will have less cache memory, or have advanced features intentionally disabled; these missing features can have a variable impact on performance, but is very substantial. While a few of the Celeron designs have achieved surprising performance, most of the Celeron line has exhibited noticeably degraded performance; this has been the primary justification for the higher cost of other Intel CPU brands versus the Celeron range. Introduced in April 1998, the first Celeron branded CPU was based on the Pentium II. Subsequent Celeron branded CPUs were based on the Pentium III, Pentium 4, Pentium M, Intel Core; the latest Celeron design is based on the seventh generation Core i3/i5/i7 series.
This design features independent processing cores, but with only 66% as much cache memory as the comparable Core i3 offering. As a product concept, the Celeron was introduced in response to Intel's loss of the low-end market, in particular to the Cyrix 6x86, the AMD K6, the IDT Winchip. Intel's existing low-end product, the Pentium MMX, was no longer performance competitive at 233 MHz. Although a faster Pentium MMX would have been a lower-risk strategy, the industry standard Socket 7 platform hosted a market of competitor CPUs which could be drop-in replacements for the Pentium MMX. Instead, Intel pursued a budget part, to be pin-compatible with their high-end Pentium II product, using the Pentium II's proprietary Slot 1 interface; the Celeron effectively killed off the 9-year-old 80486 chip, the low-end processor brand for laptops until 1998. Intel hired marketing firm Lexicon Branding, which had come up with the name "Pentium", to devise a name for the new product as well; the San Jose Mercury News described Lexicon's reasoning behind the name they chose: "Celer is Latin for swift.
As in'accelerate.' And'on.' As in'turned on.' Celeron is three syllables, like Pentium. The'Cel' of Celeron rhymes with'tel' of Intel." Launched in April 1998, the first Covington Celeron was a 266 MHz Pentium II manufactured without any secondary cache at all. Covington shared the 80523 product code of Deschutes. Although clocked at 266 or 300 MHz, the cacheless Celerons had trouble outcompeting the parts they were designed to replace. Substantial numbers were sold on first release on the strength of the Intel name, but the Celeron achieved a poor reputation both in the trade press and among computer professionals; the initial market interest faded in the face of its poor performance and with sales at a low level, Intel felt obliged to develop a faster replacement as soon as possible. The first Celerons were quite popular among some overclockers, for their flexible overclockability and reasonable price. Covington was only manufactured in Slot 1 SEPP format; the Mendocino Celeron, launched August 24, 1998, was the first retail CPU to use on-die L2 cache.
Whereas Covington had no secondary cache at all, Mendocino included 128 KB of L2 cache running at full clock rate. The first Mendocino-core Celeron was clocked at a then-modest 300 MHz but offered twice the performance of the old cacheless Covington Celeron at the same clock rate. To distinguish it from the older Covington 300 MHz, Intel called the Mendocino core Celeron 300A. Although the other Mendocino Celerons did not have an A appended, some people call all Mendocino processors Celeron-A regardless of clock rate; the new Mendocino-core Celeron was a good performer from the outset. Indeed, most industry analysts regarded the first Mendocino-based Celerons as too successful—performance was sufficiently high to not only compete with rival parts, but to attract buyers away from Intel's high-profit flagship, the Pentium II. Overclockers soon discovered that, given a high-end motherboard, many Celeron 300A CPUs could run reliably at 450 MHz; this was achieved by increasing the front-side bus clock rate from the stock 66 MHz to the 100 MHz clock of the Pentium II, helped by several facts: the 440BX chipset with nominal support for 100 MHz and correspondent memory had been on the market, the internal L2 cache was more tolerant to overclocking than external cache chips, which had to run at half-CPU speed by design.
At this frequency, the budget Mendocino Celeron rivaled the fastest x86 processors available. Some motherboards were designed to prevent this modification, by restricting the Celeron's front side bus to 66 MHz. However, overclockers soon found that putting tape over pin B21 of the Celeron's interface slot circumvented this, allowing a 100 MHz bus. At the time on-die cache was difficult to manufacture. A benefit of on-die cache is that it operates at the same clock rate as the CPU. All other Intel CPUs at that time used motherboard mounted or slot mounted secondary L2 cache, easy to manufacture and simple to enlarge to any desired size, but they carried the performance penalty of slower cache performance running at FSB frequency of 60 to 100 MHz; the Pentium II's 512 KB of L2 cache was implemented with a pair of high-performance L2 cache chips mounted on a special-purpose board along
Intel
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, in the Silicon Valley. It is the world's second largest and second highest valued semiconductor chip manufacturer based on revenue after being overtaken by Samsung, is the inventor of the x86 series of microprocessors, the processors found in most personal computers. Intel ranked No. 46 in the 2018 Fortune 500 list of the largest United States corporations by total revenue. Intel supplies processors for computer system manufacturers such as Apple, Lenovo, HP, Dell. Intel manufactures motherboard chipsets, network interface controllers and integrated circuits, flash memory, graphics chips, embedded processors and other devices related to communications and computing. Intel Corporation was founded on July 18, 1968, by semiconductor pioneers Robert Noyce and Gordon Moore, associated with the executive leadership and vision of Andrew Grove; the company's name was conceived as portmanteau of the words integrated and electronics, with co-founder Noyce having been a key inventor of the integrated circuit.
The fact that "intel" is the term for intelligence information made the name appropriate. Intel was an early developer of SRAM and DRAM memory chips, which represented the majority of its business until 1981. Although Intel created the world's first commercial microprocessor chip in 1971, it was not until the success of the personal computer that this became its primary business. During the 1990s, Intel invested in new microprocessor designs fostering the rapid growth of the computer industry. During this period Intel became the dominant supplier of microprocessors for PCs and was known for aggressive and anti-competitive tactics in defense of its market position against Advanced Micro Devices, as well as a struggle with Microsoft for control over the direction of the PC industry; the Open Source Technology Center at Intel hosts PowerTOP and LatencyTOP, supports other open-source projects such as Wayland, Mesa3D, Intel Array Building Blocks, Threading Building Blocks, Xen. Client Computing Group – 55% of 2016 revenues – produces hardware components used in desktop and notebook computers.
Data Center Group – 29% of 2016 revenues – produces hardware components used in server and storage platforms. Internet of Things Group – 5% of 2016 revenues – offers platforms designed for retail, industrial and home use. Non-Volatile Memory Solutions Group – 4% of 2016 revenues – manufactures NAND flash memory and 3D XPoint, branded as Optane, products used in solid-state drives. Intel Security Group – 4% of 2016 revenues – produces software security, antivirus software. Programmable Solutions Group – 3% of 2016 revenues – manufactures programmable semiconductors. In 2017, Dell accounted for about 16% of Intel's total revenues, Lenovo accounted for 13% of total revenues, HP Inc. accounted for 11% of total revenues. According to IDC, while Intel enjoyed the biggest market share in both the overall worldwide PC microprocessor market and the mobile PC microprocessor in the second quarter of 2011, the numbers decreased by 1.5% and 1.9% compared to the first quarter of 2011. In the 1980s, Intel was among the top ten sellers of semiconductors in the world.
In 1992, Intel became the biggest chip maker by revenue and has held the position since. Other top semiconductor companies include TSMC, Advanced Micro Devices, Texas Instruments, Toshiba and STMicroelectronics. Competitors in PC chipsets include Advanced Micro Devices, VIA Technologies, Silicon Integrated Systems, Nvidia. Intel's competitors in networking include NXP Semiconductors, Broadcom Limited, Marvell Technology Group and Applied Micro Circuits Corporation, competitors in flash memory include Spansion, Qimonda, Toshiba, STMicroelectronics, SK Hynix; the only major competitor in the x86 processor market is Advanced Micro Devices, with which Intel has had full cross-licensing agreements since 1976: each partner can use the other's patented technological innovations without charge after a certain time. However, the cross-licensing agreement is canceled in the event of takeover; some smaller competitors such as VIA Technologies produce low-power x86 processors for small factor computers and portable equipment.
However, the advent of such mobile computing devices, in particular, has in recent years led to a decline in PC sales. Since over 95% of the world's smartphones use processors designed by ARM Holdings, ARM has become a major competitor for Intel's processor market. ARM is planning to make inroads into the PC and server market. Intel has been involved in several disputes regarding violation of antitrust laws, which are noted below. Intel was founded in Mountain View, California, in 1968 by Gordon E. Moore, a chemist, Robert Noyce, a physicist and co-inventor of the integrated circuit. Arthur Rock helped. Moore and Noyce had left Fairchild Semiconductor to found Intel. Rock was not an employee; the total initial investment in Intel was $10,000 from Rock. Just 2 years Intel became a public company via an initial public offering, raising $6.8 million. Intel's third employee was Andy Grove, a chemical engineer, who ran the company through much of the 1980s and the high-growth 1990s. In dec
MMX (instruction set)
MMX is a single instruction, multiple data instruction set designed by Intel, introduced in 1997 with its P5-based Pentium line of microprocessors, designated as "Pentium with MMX Technology". It developed out of a similar unit introduced on the Intel i860, earlier the Intel i750 video pixel processor. MMX is a processor supplementary capability, supported on recent IA-32 processors by Intel and other vendors; the New York Times described the initial push, including Super Bowl ads, as focused on "a new generation of glitzy multimedia products, including videophones and 3-D video games."MMX has subsequently been extended by several programs by Intel and others: 3DNow!, Streaming SIMD Extensions, ongoing revisions of Advanced Vector Extensions. MMX is a meaningless initialism trademarked by Intel. Newsweek described it as "57 new'instructions' etched microscopically onto the face of the chip."AMD, during one of its numerous court battles with Intel, produced marketing material from Intel indicating that MMX stood for "Matrix Math Extensions".
Since an initialism cannot be trademarked, this was an attempt to invalidate Intel's trademark. In 1995, Intel filed suit against AMD and Cyrix Corp. for misuse of its trademark MMX. AMD and Intel settled, with AMD acknowledging MMX as a trademark owned by Intel, with Intel granting AMD rights to use the MMX trademark as a technology name, but not a processor name. MMX defines eight registers, called MM0 through MM7, operations that operate on them; each register is 64 bits wide and can be used to hold either 64-bit integers, or multiple smaller integers in a "packed" format: a single instruction can be applied to two 32-bit integers, four 16-bit integers, or eight 8-bit integers at once. MMX provides only integer operations; when developed, for the Intel i860, the use of integer math made sense, but as graphics cards that did much of this became common, integer SIMD in the CPU became somewhat redundant for graphical applications. On the other hand, the saturation arithmetic operations in MMX could speed up some digital signal processing applications.
To avoid compatibility problems with the context switch mechanisms in existing operating systems, the MMX registers are aliases for the existing x87 FPU registers, which context switches would save and restore. Unlike the x87 registers, which behave like a stack, the MMX registers are each directly addressable. Any operation involving the floating point stack might affect the MMX registers and vice versa, so this aliasing makes it difficult to work with floating point and SIMD operations in the same application. To maximize performance, programmers used the processor in one mode or the other, deferring the slow switch between them as long as possible; each 64-bit MMX register corresponds to the mantissa part of an 80-bit x87 register. The upper 16 bits of the x87 registers thus go unused in MMX, these bits are all set to ones, making them NaNs or infinities in the floating point representation; this can be used by applications to decide whether a particular register's content is intended as floating point or SIMD data.
Software support for MMX was slow in coming. Intel's C Compiler and related development tools obtained intrinsics for invoking MMX instructions and Intel released libraries of common vectorized algorithms using MMX. Both Intel and Metrowerks attempted automatic vectorization in their compilers, but the operations in the C programming language mapped poorly onto the MMX instruction set and custom algorithms as of 2000 still had to be written in assembly. AMD, a competing x86 microprocessor vendor, enhanced Intel's MMX with their own 3DNow! Instruction set. 3DNow is best known for adding single-precision floating-point support to the SIMD instruction-set, among other integer and more general enhancements. Following MMX, Intel's next major x86 extension was the SSE, introduced with the Pentium-III family. SSE addressed the core shortcomings of MMX by creating a new 128-bit wide register file and new SIMD instructions for it. Like 3DNow!, SSE focused on single-precision floating-point operations. However, the new XMM register-file allowed SSE SIMD-operations to be mixed with either MMX or x87 FPU ops.
SSE2, introduced with the Pentium 4, further extended the x86 SIMD instruction set with integer and double-precision floating-point data support for the XMM register file. SSE2 allowed the MMX opcodes to use XMM register operands, extended to wider YMM and ZMM registers by SSE revisions. Intel's and Marvell's XScale microprocessor core starting with PXA270 include an SIMD instruction set extension to the ARM core called iwMMXt whose functions are similar to those of the IA-32 MMX extension. IwMMXt stands for "Intel Wireless MMX Technology", it provides logic operations on 64-bit integer numbers. The extension contains. All registers are accessed through standard ARM architecture coprocessor mapping mechanism. IwMMXt occupies coprocessors 0 and 1 space, some of its opcodes clash with the opcodes of the earlier floating-point extension, FPA. Versions of Marvell's ARM processo
