1.
Bubble (computing)
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In computing, a bubble or pipeline stall is a delay in execution of an instruction in an instruction pipeline in order to resolve a hazard. During the decoding stage, the unit will determine if the decoded instruction reads from a register that the instruction currently in the execution stage writes to. If this condition holds, the unit will stall the instruction by one clock cycle. It also stalls the instruction in the stage, to prevent the instruction in that stage from being overwritten by the next instruction in the program. The values are preserved until the bubble has passed through the execution stage, the execution stage of the pipeline must always be performing an action. A bubble is represented in the stage as a NOP instruction. The below example shows a bubble being inserted into a classic RISC pipeline, in this example, data available after the MEM stage of the first instruction is required as input by the EX stage of the second instruction. Without a bubble, the EX stage only has access to the output of the previous EX stage, thus adding a bubble resolves the time dependence without needing to propagate data backwards in time. Branch predication Delay slot Pipeline flush Wait state
2.
Intel
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Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California that was founded by Gordon Moore and Robert Noyce. It is the worlds largest and highest valued semiconductor chip makers based on revenue, and is the inventor of the x86 series of microprocessors, Intel supplies processors for computer system manufacturers such as Apple, Lenovo, HP, and Dell. Intel Corporation was founded on July 18,1968, by semiconductor pioneers Robert Noyce and Gordon Moore, the companys name was conceived as portmanteau of the words integrated and electronics. The fact that intel is the term for intelligence information made the name appropriate. Intel was a developer of SRAM and DRAM memory chips. Although Intel created the worlds first commercial microprocessor chip in 1971, during the 1990s, Intel invested heavily in new microprocessor designs fostering the rapid growth of the computer industry. The Open Source Technology Center at Intel hosts PowerTOP and LatencyTOP, and supports other projects such as Wayland, Intel Array Building Blocks, and Threading Building Blocks. Client Computing Group – 55% of 2016 revenues – produces hardware components used in desktop, data Center Group – 29% of 2016 revenues – produces hardware components used in server, network, and storage platforms. Internet of Things Group – 5% of 2016 revenues – offers platforms designed for retail, transportation, industrial, buildings, non-Volatile Memory Solutions Group – 4% of 2016 revenues – manufactures NAND flash memory products primarily used in solid-state drives. Intel Security Group – 4% of 2016 revenues – produces software, particularly security, programmable Solutions Group – 3% of 2016 revenues – manufactures programmable semiconductors. In 2016, Dell accounted for 15% of Intels total revenues, Lenovo accounted for 13% of total revenues, in the 1980s, Intel was among the top ten sellers of semiconductors in the world. In 1991, Intel became the biggest chip maker by revenue and has held the position ever since, other top semiconductor companies include TSMC, Advanced Micro Devices, Samsung, Texas Instruments, Toshiba and STMicroelectronics. Competitors in PC chip sets include Advanced Micro Devices, VIA Technologies, Silicon Integrated Systems, however, the cross-licensing agreement is canceled in the event of an AMD bankruptcy or takeover. Some smaller competitors such as VIA Technologies produce low-power x86 processors for small factor computers, however, the advent of such mobile computing devices, in particular, smartphones, has in recent years led to a decline in PC sales. Since over 95% of the worlds smartphones currently use processors designed by ARM Holdings, ARM is also planning to make inroads into the PC and server market. Intel has been involved in disputes regarding violation of antitrust laws. Intel was founded in Mountain View, California in 1968 by Gordon E. Moore, a chemist, and Robert Noyce, arthur Rock helped them find investors, while Max Palevsky was on the board from an early stage. Moore and Noyce had left Fairchild Semiconductor to found Intel, Rock was not an employee, but he was an investor and was chairman of the board
3.
Parallel computation
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Parallel computing is a type of computation in which many calculations or the execution of processes are carried out simultaneously. Large problems can often be divided into smaller ones, which can then be solved at the same time, there are several different forms of parallel computing, bit-level, instruction-level, data, and task parallelism. Parallelism has been employed for years, mainly in high-performance computing. As power consumption by computers has become a concern in recent years, parallel computing has become the dominant paradigm in computer architecture, specialized parallel computer architectures are sometimes used alongside traditional processors, for accelerating specific tasks. Communication and synchronization between the different subtasks are typically some of the greatest obstacles to getting good parallel program performance, a theoretical upper bound on the speed-up of a single program as a result of parallelization is given by Amdahls law. Traditionally, computer software has been written for serial computation, to solve a problem, an algorithm is constructed and implemented as a serial stream of instructions. These instructions are executed on a central processing unit on one computer, only one instruction may execute at a time—after that instruction is finished, the next one is executed. Parallel computing, on the hand, uses multiple processing elements simultaneously to solve a problem. This is accomplished by breaking the problem into independent parts so that each processing element can execute its part of the algorithm simultaneously with the others. The processing elements can be diverse and include such as a single computer with multiple processors, several networked computers, specialized hardware. Frequency scaling was the dominant reason for improvements in performance from the mid-1980s until 2004. The runtime of a program is equal to the number of instructions multiplied by the time per instruction. Maintaining everything else constant, increasing the frequency decreases the average time it takes to execute an instruction. An increase in frequency thus decreases runtime for all compute-bound programs. However, power consumption P by a chip is given by the equation P = C × V2 × F, where C is the capacitance being switched per clock cycle, V is voltage, increases in frequency increase the amount of power used in a processor. Moores law is the observation that the number of transistors in a microprocessor doubles every 18 to 24 months. Despite power consumption issues, and repeated predictions of its end, with the end of frequency scaling, these additional transistors can be used to add extra hardware for parallel computing. Optimally, the speedup from parallelization would be linear—doubling the number of processing elements should halve the runtime, however, very few parallel algorithms achieve optimal speedup
4.
X86
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X86 is a family of backward-compatible instruction set architectures based on the Intel 8086 CPU and its Intel 8088 variant. The term x86 came into being because the names of several successors to Intels 8086 processor end in 86, many additions and extensions have been added to the x86 instruction set over the years, almost consistently with full backward compatibility. The architecture has been implemented in processors from Intel, Cyrix, AMD, VIA and many companies, there are also open implementations. In the 1980s and early 1990s, when the 8088 and 80286 were still in common use, today, however, x86 usually implies a binary compatibility also with the 32-bit instruction set of the 80386. An 8086 system, including such as 8087 and 8089. There were also terms iRMX, iSBC, and iSBX – all together under the heading Microsystem 80, however, this naming scheme was quite temporary, lasting for a few years during the early 1980s. Today, x86 is ubiquitous in both stationary and portable computers, and is also used in midrange computers, workstations, servers. A large amount of software, including operating systems such as DOS, Windows, Linux, BSD, Solaris and macOS, functions with x86-based hardware. There have been attempts, including by Intel itself, to end the market dominance of the inelegant x86 architecture designed directly from the first simple 8-bit microprocessors. Examples of this are the iAPX432, the Intel 960, Intel 860, however, the continuous refinement of x86 microarchitectures, circuitry and semiconductor manufacturing would make it hard to replace x86 in many segments. The table below lists processor models and model series implementing variations of the x86 instruction set, each line item is characterized by significantly improved or commercially successful processor microarchitecture designs. Such x86 implementations are seldom simple copies but often employ different internal microarchitectures as well as different solutions at the electronic, quite naturally, early compatible microprocessors were 16-bit, while 32-bit designs were developed much later. For the personal computer market, real quantities started to appear around 1990 with i386 and i486 compatible processors, other companies, which designed or manufactured x86 or x87 processors, include ITT Corporation, National Semiconductor, ULSI System Technology, and Weitek. Some early versions of these microprocessors had heat dissipation problems, AMD later managed to establish itself as a serious contender with the K6 set of processors, which gave way to the very successful Athlon and Opteron. There were also other contenders, such as Centaur Technology, Rise Technology, VIA Technologies energy efficient C3 and C7 processors, which were designed by the Centaur company, have been sold for many years. Centaurs newest design, the VIA Nano, is their first processor with superscalar and it was, perhaps interestingly, introduced at about the same time as Intels first in-order processor since the P5 Pentium, the Intel Atom. The instruction set architecture has twice been extended to a word size. In 1999-2003, AMD extended this 32-bit architecture to 64 bits and referred to it as x86-64 in early documents, Intel soon adopted AMDs architectural extensions under the name IA-32e, later using the name EM64T and finally using Intel 64
5.
Xeon
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The Xeon /ˈziːɒn/ is a brand of x86 microprocessors designed, manufactured, and marketed by Intel Corporation, targeted at the non-consumer workstation, server, and embedded system markets. Despite such disadvantages, Xeon processors have always had popularity among users, mainly due to higher core count potential. Because most Intel Xeon CPUs lack an integrated GPU, systems built with such integrated GPU lacking processors require a discrete graphics card if a VDU output is desired, the Xeon brand has been maintained over several generations of x86 and x86-64 processors. Older models added the Xeon moniker to the end of the name of their corresponding desktop processor, the Xeon CPUs generally have more cache than their desktop counterparts in addition to multiprocessing capabilities. The first Xeon-branded processor was the Pentium II Xeon and it was released in 1998, replacing the Pentium Pro in Intels server lineup. The Pentium II Xeon was a Deschutes Pentium II with a full-speed 512 kB,1 MB, the L2 cache was implemented with custom 512 kB SRAMs developed by Intel. The number of SRAMs depended on the amount of cache, a 512 kB configuration required one SRAM, a 1 MB configuration, two SRAMs, and a 2 MB configuration, four SRAMs on both sides of the PCB. Each SRAM was a 12.90 mm by 17.23 mm die fabricated in a 0.35 µm four-layer metal CMOS process, the additional cache required a larger module and thus the Pentium II Xeon used a larger slot, Slot 2. It was supported by the 440GX dual-processor workstation chipset and the 450NX quad- or octo-processor chipset, in 1999, the Pentium II Xeon was replaced by the Pentium III Xeon. The product codes for Tanner mirrored that of Katmai,80525, the second version, named Cascades, was based on the Pentium III Coppermine core. To improve this situation, Intel released another version, officially also named Cascades and that came in two variants, with 1 MB or 2 MB of L2 cache. Its bus speed was fixed at 100 MHz, though in practice the cache was able to offset this, the product code for Cascades mirrored that of Coppermine,80526. In mid-2001, the Xeon brand was introduced, the initial variant that used the new NetBurst microarchitecture, Foster, was slightly different from the desktop Pentium 4. It was a decent chip for workstations, but for server applications it was almost always outperformed by the older Cascades cores with a 2 MB L2 cache, combined with the need to use expensive Rambus Dynamic RAM, the Fosters sales were somewhat unimpressive. This improved performance slightly, but not enough to lift it out of third place and it was also priced much higher than the dual-processor versions. The Foster shared the 80528 product code with Willamette, in 2002 Intel released a 130 nm version of Xeon branded CPU, codenamed Prestonia. It supported Intels new Hyper-Threading technology and had a 512 kB L2 cache and this was based on the Northwood Pentium 4 core. A new server chipset, E7500, was released to support this processor in servers, the Prestonia performed much better than its predecessor and noticeably better than Athlon MP
6.
Central processing unit
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The computer industry has used the term central processing unit at least since the early 1960s. The form, design and implementation of CPUs have changed over the course of their history, most modern CPUs are microprocessors, meaning they are contained on a single integrated circuit chip. An IC that contains a CPU may also contain memory, peripheral interfaces, some computers employ a multi-core processor, which is a single chip containing two or more CPUs called cores, in that context, one can speak of such single chips as sockets. Array processors or vector processors have multiple processors that operate in parallel, there also exists the concept of virtual CPUs which are an abstraction of dynamical aggregated computational resources. Early computers such as the ENIAC had to be rewired to perform different tasks. Since the term CPU is generally defined as a device for software execution, the idea of a stored-program computer was already present in the design of J. Presper Eckert and John William Mauchlys ENIAC, but was initially omitted so that it could be finished sooner. On June 30,1945, before ENIAC was made, mathematician John von Neumann distributed the paper entitled First Draft of a Report on the EDVAC and it was the outline of a stored-program computer that would eventually be completed in August 1949. EDVAC was designed to perform a number of instructions of various types. Significantly, the programs written for EDVAC were to be stored in high-speed computer memory rather than specified by the wiring of the computer. This overcame a severe limitation of ENIAC, which was the considerable time, with von Neumanns design, the program that EDVAC ran could be changed simply by changing the contents of the memory. Early CPUs were custom designs used as part of a larger, however, this method of designing custom CPUs for a particular application has largely given way to the development of multi-purpose processors produced in large quantities. This standardization began in the era of discrete transistor mainframes and minicomputers and has accelerated with the popularization of the integrated circuit. The IC has allowed increasingly complex CPUs to be designed and manufactured to tolerances on the order of nanometers, both the miniaturization and standardization of CPUs have increased the presence of digital devices in modern life far beyond the limited application of dedicated computing machines. Modern microprocessors appear in electronic devices ranging from automobiles to cellphones, the so-called Harvard architecture of the Harvard Mark I, which was completed before EDVAC, also utilized a stored-program design using punched paper tape rather than electronic memory. Relays and vacuum tubes were used as switching elements, a useful computer requires thousands or tens of thousands of switching devices. The overall speed of a system is dependent on the speed of the switches, tube computers like EDVAC tended to average eight hours between failures, whereas relay computers like the Harvard Mark I failed very rarely. In the end, tube-based CPUs became dominant because the significant speed advantages afforded generally outweighed the reliability problems, most of these early synchronous CPUs ran at low clock rates compared to modern microelectronic designs. Clock signal frequencies ranging from 100 kHz to 4 MHz were very common at this time, the design complexity of CPUs increased as various technologies facilitated building smaller and more reliable electronic devices
7.
Pentium 4
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Pentium 4 was a line of single-core central processing units for desktops, laptops and entry-level servers introduced by Intel on November 20,2000 and shipped through August 8,2008. They had a seventh-generation x86 microarchitecture, called NetBurst, which was the companys first all-new design since the introduction of the P6 microarchitecture of the Pentium Pro CPUs in 1995, NetBurst differed from P6 by featuring a very deep instruction pipeline to achieve very high clock speeds. Intel claimed that NetBurst would allow speeds of up to 10 GHz in future chips, however. In 2004, the initial 32-bit x86 instruction set of the Pentium 4 microprocessors was extended by the 64-bit x86-64 set, the first Pentium 4 cores, codenamed Willamette, were clocked from 1.3 GHz to 2 GHz. They were released on November 20,2000, using the Socket 423 system, notable with the introduction of the Pentium 4 was the 400 MT/s FSB. It actually operated at 100 MHz, but the FSB was quad-pumped, meaning that the transfer rate was four times the base clock of the bus. The AMD Athlons double-pumped FSB was running at 100 or 133 MHz at that time, Pentium 4 CPUs introduced the SSE2 and, in the Prescott-based Pentium 4s, SSE3 instruction sets to accelerate calculations, transactions, media processing, 3D graphics, and games. Later versions featured Hyper-Threading Technology, a feature to one physical CPU work as two logical CPUs. Intel also marketed a version of their low-end Celeron processors based on the NetBurst microarchitecture, in 2005, the Pentium 4 was complemented by the Pentium D and Pentium Extreme Edition dual-core CPUs. In benchmark evaluations, the advantages of the NetBurst microarchitecture were unclear, with carefully optimized application code, the first Pentium 4s outperformed Intels fastest Pentium III, as expected. But in legacy applications with many branching or x87 floating-point instructions and its main handicap was a shared unidirectional bus. Furthermore, the NetBurst microarchitecture consumed more power and emitted more heat than any previous Intel or AMD microarchitectures, as a result, the Pentium 4s introduction was met with mixed reviews, Developers disliked the Pentium 4, as it posed a new set of code optimization rules. For example, in applications, AMDs lower-clocked Athlon easily outperformed the Pentium 4. Tom Yager of Infoworld magazine called it the fastest CPU - for programs that fit entirely in cache, computer-savvy buyers avoided Pentium 4 PCs due to their price premium, questionable benefit, and initial restriction to Rambus RAM. In terms of marketing, the Pentium 4s singular emphasis on clock frequency made it a marketers dream. The result of this was that the NetBurst microarchitecture was often referred to as a marchitecture by various computing websites and it was also called NetBust, a term popular with reviewers who reflected negatively upon the processors performance. The two classical metrics of CPU performance are IPC and clock speed, while IPC is difficult to quantify due to dependence on the benchmark applications instruction mix, clock speed is a simple measurement yielding a single absolute number. Unsophisticated buyers would simply consider the processor with the highest clock speed to be the best product, because AMDs processors had slower clock speeds, it countered Intels marketing advantage with the megahertz myth campaign
8.
Itanium
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Itanium is a family of 64-bit Intel microprocessors that implement the Intel Itanium architecture. Intel markets the processors for servers and high-performance computing systems. The Itanium architecture originated at Hewlett-Packard, and was jointly developed by HP. Itanium-based systems have produced by HP and several other manufacturers. In 2008, Itanium was the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, Power Architecture, the currently shipping Itanium processor generation, Poulson, was released on November 8,2012. In February 2017, Intel began releasing its successor, Kittson, to test customers, as Intel has not provided a roadmap beyond it and Hewlett-Packard is the only remaining major Itanium vendor, press and analysts have speculated that it will be the last Itanium generation. In 1989, HP determined that Reduced Instruction Set Computing architectures were approaching a processing limit at one instruction per cycle, HP researchers investigated a new architecture, later named Explicitly Parallel Instruction Computing, that allows the processor to execute multiple instructions in each clock cycle. EPIC implements a form of very long instruction word architecture, in which a single instruction word contains multiple instructions, Intel was willing to undertake a very large development effort on IA-64 in the expectation that the resulting microprocessor would be used by the majority of enterprise systems manufacturers. HP and Intel initiated a joint development effort with a goal of delivering the first product, Merced. Compaq and Silicon Graphics decided to further development of the Alpha. Several groups developed operating systems for the architecture, including Microsoft Windows, OpenVMS, Linux, and UNIX variants such as HP-UX, Solaris, Tru64 UNIX, and Monterey/64. By 1997, it was apparent that the IA-64 architecture and the compiler were much more difficult to implement than originally thought, technical difficulties included the very high transistor counts needed to support the wide instruction words and the large caches. There were also structural problems within the project, as the two parts of the joint team used different methodologies and had different priorities. Since Merced was the first EPIC processor, the development effort encountered more unanticipated problems than the team was accustomed to, in addition, the EPIC concept depends on compiler capabilities that had never been implemented before, so more research was needed. Intel announced the name of the processor, Itanium, on October 4,1999. Within hours, the name Itanic had been coined on a Usenet newsgroup, a reference to Titanic, by the time Itanium was released in June 2001, its performance was not superior to competing RISC and CISC processors. Itanium competed at the low-end with servers based on x86 processors, Intel repositioned Itanium to focus on high-end business and HPC computing, attempting to duplicate x86s successful horizontal market. POWER and SPARC remained strong, while the 32-bit x86 architecture continued to grow into the enterprise space, only a few thousand systems using the original Merced Itanium processor were sold, due to relatively poor performance, high cost and limited software availability
9.
Intel Atom
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Intel Atom was the brand name for a line of ultra-low-voltage IA-32 and x86-64 microprocessors by Intel Corporation. Atom was mainly used in netbooks, nettops, embedded applications ranging from health care to advanced robotics, the line was originally designed in 45 nm complementary metal–oxide–semiconductor technology and subsequent models, codenamed Cedar, used a 32 nm process. The first generation of Atom processors are based on the Bonnell microarchitecture, on 21 December 2009, Intel announced the Pine Trail platform, including new Atom processor code-named Pineview, with total kit power consumption down 20%. On 28 December 2011, Intel updated the Atom line with the Cedar processors, in December 2012, Intel launched the 64-bit Centerton family of Atom CPUs, designed specifically for use in servers. Centerton adds features previously unavailable in Atom processors, such as Intel VT virtualization technology, on 4 September 2013 Intel launched a 22 nm successor to Centerton, codenamed Avoton. In 2012, Intel announced a new system on chip platform designed for smartphones and it was a continuation of the partnership announced by Intel and Google on 13 September 2011 to provide support for the Android operating system on Intel x86 processors. This range competed with existing SoCs developed for the smartphone and tablet market from companies like Texas Instruments, Nvidia, Qualcomm, on April 29,2016, Intel announced the decision to cancel the Broxton SoC for Smartphones and Tablets. Broxton was to use the newest Atom microarchitecture in combination with an Intel modem, apollo Lake, announced early the same month for low-cost entry PCs, will continue using Atom cores. Intel Atom is a successor of the Intel A100 and A110 low-power microprocessors. However, Intel revealed on 15 October 2007 that it was developing another new mobile processor, codenamed Diamondville, Atom was the name under which Silverthorne would be sold, while the supporting chipset formerly code-named Menlow was called Centrino Atom. At Spring Intel Developer Forum 2008 in Shanghai, Intel officially announced that Silverthorne, Silverthorne would be called the Atom Z5xx series and Diamondville would be called the Atom N2xx series. The more expensive lower-power Silverthorne parts will be used in Intel mobile Internet devices whereas Diamondville will be used in low-cost desktop, several Mini-ITX motherboard samples have also been revealed. Intel and Lenovo also jointly announced an Atom powered MID called the IdeaPad U8, in April 2008, a MID development kit was announced by Sophia Systems and the first board called CoreExpress-ECO was revealed by a German company LiPPERT Embedded Computers, GmbH. In December 2012, Intel released Atom for servers, the S1200 series, Atom processors became available to system manufacturers in 2008. The Pineview line is used in multiple AAC devices for the disabled individual who is unable to speak. Intel consumer electronic SoCs are marketed under the Atom brand, prior to application of the Atom brand, there were number of Intel CE SoCs including, Olo River and Canmore. Intel Atom CE branded SoCs include, Sodaville, Groveland, all Atom processors implement the x86 instruction set, however, support for the Intel 64 instruction set was not added until the desktop Diamondville and desktop and mobile Pineview cores. The Atom N2xx and Z5xx series Atom models cannot run x86-64 code, the Centerton server processors will support the Intel 64 instruction set
10.
Multi-core processor
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A multi-core processor is a single computing component with two or more independent actual processing units, which are units that read and execute program instructions. The instructions are ordinary CPU instructions, but the multiple cores can run multiple instructions at the same time, manufacturers typically integrate the cores onto a single integrated circuit die, or onto multiple dies in a single chip package. A multi-core processor implements multiprocessing in a physical package. Designers may couple cores in a multi-core device tightly or loosely, for example, cores may or may not share caches, and they may implement message passing or shared-memory inter-core communication methods. Common network topologies to interconnect cores include bus, ring, two-dimensional mesh, homogeneous multi-core systems include only identical cores, heterogeneous multi-core systems have cores that are not identical. Just as with single-processor systems, cores in multi-core systems may implement architectures such as VLIW, superscalar, Multi-core processors are widely used across many application domains, including general-purpose, embedded, network, digital signal processing, and graphics. The improvement in performance gained by the use of a multi-core processor depends very much on the algorithms used. In particular, possible gains are limited by the fraction of the software that can run in parallel simultaneously on multiple cores, most applications, however, are not accelerated so much unless programmers invest a prohibitive amount of effort in re-factoring the whole problem. The parallelization of software is a significant ongoing topic of research, the terms multi-core and dual-core most commonly refer to some sort of central processing unit, but are sometimes also applied to digital signal processors and system on a chip. This article uses the terms multi-core and dual-core for CPUs manufactured on the integrated circuit. In contrast to systems, the term multi-CPU refers to multiple physically separate processing-units. The terms many-core and massively multi-core are sometimes used to describe multi-core architectures with a high number of cores. Some systems use many soft microprocessor cores placed on a single FPGA, each core can be considered a semiconductor intellectual property core as well as a CPU core. While manufacturing technology improves, reducing the size of individual gates and these physical limitations can cause significant heat dissipation and data synchronization problems. Various other methods are used to improve CPU performance, some instruction-level parallelism methods such as superscalar pipelining are suitable for many applications, but are inefficient for others that contain difficult-to-predict code. Many applications are better suited to thread-level parallelism methods, and multiple independent CPUs are commonly used to increase a systems overall TLP, a combination of increased available space and the demand for increased TLP led to the development of multi-core CPUs. Several business motives drive the development of multi-core architectures, for decades, it was possible to improve performance of a CPU by shrinking the area of the integrated circuit, which reduced the cost per device on the IC. Alternatively, for the circuit area, more transistors could be used in the design
11.
Operating system
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An operating system is system software that manages computer hardware and software resources and provides common services for computer programs. All computer programs, excluding firmware, require a system to function. Operating systems are found on many devices that contain a computer – from cellular phones, the dominant desktop operating system is Microsoft Windows with a market share of around 83. 3%. MacOS by Apple Inc. is in place, and the varieties of Linux is in third position. Linux distributions are dominant in the server and supercomputing sectors, other specialized classes of operating systems, such as embedded and real-time systems, exist for many applications. A single-tasking system can run one program at a time. Multi-tasking may be characterized in preemptive and co-operative types, in preemptive multitasking, the operating system slices the CPU time and dedicates a slot to each of the programs. Unix-like operating systems, e. g. Solaris, Linux, cooperative multitasking is achieved by relying on each process to provide time to the other processes in a defined manner. 16-bit versions of Microsoft Windows used cooperative multi-tasking, 32-bit versions of both Windows NT and Win9x, used preemptive multi-tasking. Single-user operating systems have no facilities to distinguish users, but may allow multiple programs to run in tandem, a distributed operating system manages a group of distinct computers and makes them appear to be a single computer. The development of networked computers that could be linked and communicate with each other gave rise to distributed computing, distributed computations are carried out on more than one machine. When computers in a work in cooperation, they form a distributed system. The technique is used both in virtualization and cloud computing management, and is common in large server warehouses, embedded operating systems are designed to be used in embedded computer systems. They are designed to operate on small machines like PDAs with less autonomy and they are able to operate with a limited number of resources. They are very compact and extremely efficient by design, Windows CE and Minix 3 are some examples of embedded operating systems. A real-time operating system is a system that guarantees to process events or data by a specific moment in time. A real-time operating system may be single- or multi-tasking, but when multitasking, early computers were built to perform a series of single tasks, like a calculator. Basic operating system features were developed in the 1950s, such as resident monitor functions that could run different programs in succession to speed up processing
12.
Superscalar processor
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A superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. It therefore allows for more throughput than would otherwise be possible at a clock rate. A superscalar processor can execute more than one instruction during a cycle by simultaneously dispatching multiple instructions to different execution units on the processor. Each execution unit is not a processor, but an execution resource within a single CPU such as an arithmetic logic unit. In Flynns taxonomy, a superscalar processor is classified as an SISD processor, though many superscalar processors support short vector operations. A multi-core superscalar processor is classified as an MIMD processor, while a superscalar CPU is typically also pipelined, pipelining and superscalar execution are considered different performance enhancement techniques. The Motorola MC88100, the Intel i960CA and the AMD 29000-series 29050 microprocessors were the first commercial single-chip superscalar microprocessors, RISC microprocessors like these were the first to have superscalar execution, because RISC architectures frees transistors and die area which could be used to include multiple execution units. Except for CPUs used in applications, embedded systems, and battery-powered devices. The simplest processors are scalar processors, each instruction executed by a scalar processor typically manipulates one or two data items at a time. By contrast, each executed by a vector processor operates simultaneously on many data items. An analogy is the difference between scalar and vector arithmetic, a superscalar processor is a mixture of the two. Each instruction processes one data item, but there are multiple execution units within each CPU thus multiple instructions can be processing separate data items concurrently, superscalar CPU design emphasizes improving the instruction dispatcher accuracy, and allowing it to keep the multiple execution units in use at all times. This has become important as the number of units has increased. While early superscalar CPUs would have two ALUs and a single FPU, a modern design such as the PowerPC970 includes four ALUs, two FPUs, and two SIMD units. If the dispatcher is ineffective at keeping all of these units fed with instructions, a superscalar processor usually sustains an execution rate in excess of one instruction per machine cycle. In a superscalar CPU the dispatcher reads instructions from memory and decides which ones can be run in parallel, therefore, a superscalar processor can be envisioned having multiple parallel pipelines, each of which is processing instructions simultaneously from a single instruction thread. Available performance improvement from superscalar techniques is limited by three key areas, The degree of parallelism in the instruction stream. The complexity and time cost of dependency checking logic and register renaming circuitry The branch instruction processing, existing binary executable programs have varying degrees of intrinsic parallelism
13.
Sun Microsystems
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Sun contributed significantly to the evolution of several key computing technologies, among them Unix, RISC processors, thin client computing, and virtualized computing. Sun was founded on February 24,1982, at its height, the Sun headquarters were in Santa Clara, California, on the former west campus of the Agnews Developmental Center. On January 27,2010, Oracle Corporation acquired Sun by for US$7.4 billion, other technologies include the Java platform, MySQL, and NFS. Sun was a proponent of open systems in general and Unix in particular, the initial design for what became Suns first Unix workstation, the Sun-1, was conceived by Andy Bechtolsheim when he was a graduate student at Stanford University in Palo Alto, California. Bechtolsheim originally designed the SUN workstation for the Stanford University Network communications project as a personal CAD workstation and it was designed around the Motorola 68000 processor with an advanced memory management unit to support the Unix operating system with virtual memory support. He built the first ones from spare parts obtained from Stanfords Department of Computer Science, on February 24,1982, Vinod Khosla, Andy Bechtolsheim, and Scott McNealy, all Stanford graduate students, founded Sun Microsystems. Bill Joy of Berkeley, a developer of the Berkeley Software Distribution. The Sun name is derived from the initials of the Stanford University Network, Sun was profitable from its first quarter in July 1982. By 1983 Sun was known for producing 68000-based systems with high-quality graphics that were the only computers other than DECs VAX to run 4. 2BSD and it licensed the computer design to other manufacturers, which typically used it to build Multibus-based systems running Unix from UniSoft. Suns initial public offering was in 1986 under the stock symbol SUNW, the symbol was changed in 2007 to JAVA, Sun stated that the brand awareness associated with its Java platform better represented the companys current strategy. Suns logo, which features four interleaved copies of the sun in the form of a rotationally symmetric ambigram, was designed by professor Vaughan Pratt. The initial version of the logo was orange and had the sides oriented horizontally and vertically, but it was rotated to stand on one corner and re-colored purple. In the dot-com bubble, Sun began making more money. It also began spending more, hiring workers and building itself out. Some of this was because of demand, but much was from web start-up companies anticipating business that would never happen. Sales in Suns important hardware division went into free-fall as customers closed shop, several quarters of steep losses led to executive departures, rounds of layoffs, and other cost cutting. In December 2001, the fell to the 1998, pre-bubble level of about $100. But it kept falling, faster than many other tech companies, a year later it had dipped below $10 but bounced back to $20
14.
CPU cache
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Cache memory makes use of the fast technology SRAM, against a slower MM DRAM, connected directly to the processor. The term cache is derived from the French and refers to a place one can hide something. This term has many meanings depending on the context, examples are, disk cache, TLB, branch prediction cache, branch history table, Branch Address Cache, trace cache, that are physical memories. Others are handled by the software, to store data in reserved MM space. Note – CPU cache is a term and rarely or wrongly used in both literature and in industrial environment. For instance, in the US patents documents relating to the cache, the term CPU cache is used in less of 2% of the documents against to the Cache Memory and the Memory Cache. Cache general definition The Cache is a memory that stores data, in silent mode to upper level of utilization. In MM read operation, the controller first of all checks if the data is stored in cache. In case of match the data is fastly and directly supplied from the cache to the processor without involving the MM.3, else the data is read from MM. A cache stores only a subset of MM data – the most recent-used MRU, Data read from MM are temporary stored in cache. If the processor requires the data, this is supplied by the cache. The cache is effective because short instruction loops and routines are a common program structure, spatial locality - If a data is referenced, it is very likely that nearby data will be accessed soon. Instructions and data are transferred from MM to the cache in fixed blocks, Cache line size is in the range of 4 to 512 bytes so that more than one processing data is stored in each cache entry. After a first MM access, all cache line data are available in cache, next instruction usually comes from the next memory location. Data is usually structured and data in these structures normally are stored in memory locations. Large lines size increase the spatial locality but increase also the number of invalidated data in case of line replacement, Cache efficiency is measured in terms of Hit Rate. Hit Rate represents the percentage of Hits compared to the number of cache accesses. The opposite of Hit is called Miss The cache efficiency depends by several elements, cache size, line size, type and cache architecture, a good figure of the cache efficiency, for business applications, may be in the range of 80-95 % of hit
15.
Symmetric multiprocessing
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Most multiprocessor systems today use an SMP architecture. In the case of processors, the SMP architecture applies to the cores. SMP systems are tightly coupled multiprocessor systems with a pool of homogeneous processors running independently of each other, each processor, executing different programs and working on different sets of data, has the capability of sharing common resources that are connected using a system bus or a crossbar. SMP systems have centralized shared memory called main memory operating under an operating system with two or more homogeneous processors. Usually each processor has an associated private high-speed memory known as memory to speed up the main memory data access. Processors may be interconnected using buses, crossbar switches or on-chip mesh networks, the bottleneck in the scalability of SMP using buses or crossbar switches is the bandwidth and power consumption of the interconnect among the various processors, the memory, and the disk arrays. A single programming language would have to be able to not only partition the workload, but also comprehend the memory locality, with proper operating system support, SMP systems can easily move tasks between processors to balance the workload efficiently. The earliest production system with multiple identical processors was the Burroughs B5000, however at run-time this was asymmetric, with one processor restricted to application programs while the other processor mainly handled the operating system and hardware interrupts. IBM offered dual-processor computer systems based on its System/360 model 65, the operating systems that ran on these machines were OS/360 M65MP and TSS/360. Other software developed at universities, notably the Michigan Terminal System, both processors could access data channels and initiate I/O. In OS/360 M65MP, peripherals could generally be attached to either processor since the system kernel ran on both processors. The MTS supervisor has the ability to run on both CPUs of the IBM System/360 model 67-2, supervisor locks were small and used to protect individual common data structures that might be accessed simultaneously from either CPU. Starting with its version 7.0, Digital Equipment Corporations operating system TOPS-10 implemented the SMP feature, later KL10 system could aggregate up to 8 CPUs in a SMP manner. In contrast, DECs first multi-processor VAX system, the VAX-11/782, was asymmetric, the first commercial Unix SMP implementation was the NUMA based Honeywell Information Systems Italy XPS-100 designed by Dan Gielan of VAST Corporation in 1985. Its design supported up to 14 processors, but due to electrical limitations, the operating system was derived and ported by VAST Corporation from AT&T 3B20 Unix SysVr3 code used internally within AT&T. On personal computers, SMP is less useful for applications that have not been modified, if the system rarely runs more than one process at a time, SMP is useful only for applications that have been modified for multithreaded processing. Custom-programmed software can be written or modified to use multiple threads, multithreaded programs can also be used in time-sharing and server systems that support multithreading, allowing them to make more use of multiple processors. In SMP, all of the processors are tightly coupled inside the box with a bus or switch
16.
Non-uniform memory access
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Non-uniform memory access is a computer memory design used in multiprocessing, where the memory access time depends on the memory location relative to the processor. Under NUMA, a processor can access its own local memory faster than non-local memory, the benefits of NUMA are limited to particular workloads, notably on servers where the data are often associated strongly with certain tasks or users. NUMA architectures logically follow in scaling from symmetric multiprocessing architectures and they were developed commercially during the 1990s by Burroughs, Convex Computer, Honeywell Information Systems Italy, Silicon Graphics, Sequent Computer Systems, Data General, and Digital. Techniques developed by these companies later featured in a variety of Unix-like operating systems, modern CPUs operate considerably faster than the main memory they use. In the early days of computing and data processing, the CPU generally ran slower than its own memory, the performance lines of processors and memory crossed in the 1960s with the advent of the first supercomputers. Since then, CPUs increasingly have found themselves starved for data, limiting the number of memory accesses provided the key to extracting high performance from a modern computer. For commodity processors, this meant installing an ever-increasing amount of high-speed cache memory, but the dramatic increase in size of the operating systems and of the applications run on them has generally overwhelmed these cache-processing improvements. Multi-processor systems without NUMA make the problem considerably worse, now a system can starve several processors at the same time, notably because only one processor can access the computers memory at a time. NUMA attempts to address this problem by providing separate memory for each processor, for problems involving spread data, NUMA can improve the performance over a single shared memory by a factor of roughly the number of processors. Of course, not all data ends up confined to a single task, to handle these cases, NUMA systems include additional hardware or software to move data between memory banks. This operation slows the processors attached to those banks, so the speed increase due to NUMA depends heavily on the nature of the running tasks. AMD implemented NUMA with its Opteron processor, using HyperTransport, Intel announced NUMA compatibility for its x86 and Itanium servers in late 2007 with its Nehalem and Tukwila CPUs. Both CPU families share a common chipset, the interconnection is called Intel Quick Path Interconnect, nearly all CPU architectures use a small amount of very fast non-shared memory known as cache to exploit locality of reference in memory accesses. With NUMA, maintaining cache coherence across shared memory has a significant overhead, although simpler to design and build, non-cache-coherent NUMA systems become prohibitively complex to program in the standard von Neumann architecture programming model. Typically, ccNUMA uses inter-processor communication between cache controllers to keep a consistent memory image when more than one cache stores the same memory location, for this reason, ccNUMA may perform poorly when multiple processors attempt to access the same memory area in rapid succession. Alternatively, cache coherency protocols such as the MESIF protocol attempt to reduce the required to maintain cache coherency. Scalable Coherent Interface is an IEEE standard defining a directory-based cache coherency protocol to avoid scalability limitations found in earlier multiprocessor systems, for example, SCI is used as the basis for the NumaConnect technology. Examples of ccNUMA-enabled chipsets are the SGI Shub, the Intel E8870, the HP sx2000, earlier ccNUMA systems such as those from Silicon Graphics were based on MIPS processors and the DEC Alpha 21364 processor
17.
Intel Core (microarchitecture)
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The Intel Core microarchitecture is a multi-core processor microarchitecture unveiled by Intel in Q12006. It is based on the Yonah processor design and can be considered an iteration of the P6 microarchitecture, while architecturally identical, the three processor lines differ in the socket used, bus speed, and power consumption. Intels CPUs have varied widely in power according to clock rate, architecture. Like the last NetBurst CPUs, Core based processors feature multiple cores and hardware support, as well as Intel 64. However, Core-based processors do not have the Hyper-Threading Technology found in Pentium 4 processors and this is because the Core microarchitecture is a descendant of the P6 microarchitecture used by Pentium Pro, Pentium II, Pentium III, and Pentium M. The L1 cache size was enlarged in the Core microarchitecture, from 32 KB on Pentium II/III to 64 KB L1 cache/core on Pentium M and Core/Core 2. It also lacks an L3 Cache found in the Gallatin core of the Pentium 4 Extreme Edition, both an L3 cache and Hyper-threading were reintroduced in the Nehalem microarchitecture. While the Core microarchitecture is a major architectural revision it is based in part on the Pentium M processor family designed by Intel Israel, the Penryn pipeline is 12–14 stages long — less than half of Prescotts, a signature feature of wide order execution cores. Penryns successor, Nehalem borrowed more heavily from the Pentium 4 and has 20-24 pipeline stages, cores execution unit is 4 issues wide, compared to the 3-issue cores of P6, Pentium M, and 2-issue cores of NetBurst microarchitectures. The new architecture is a core design with linked L1 cache and shared L2 cache engineered for maximum performance per watt. One new technology included in the design is Macro-Ops Fusion, which combines two x86 instructions into a single micro-operation, for example, a common code sequence like a compare followed by a conditional jump would become a single micro-op. Unfortunately, this technology does not work in 64-bit mode, other new technologies include 1 cycle throughput of all 128-bit SSE instructions and a new power saving design. All components will run at speed, ramping up speed dynamically as needed. This allows the chip to less heat, and consume as little power as possible. For most Woodcrest CPUs, the front side bus runs at 1333 MT/s, however, in comparison, an AMD Opteron 875HE processor consumes 55 watts, while the energy efficient Socket AM2 line fits in the 35 watt thermal envelope. Merom, the variant, is listed at 35 watts TDP for standard versions and 5 watts TDP for Ultra Low Voltage versions. Previously, Intel announced that it would now focus on power efficiency, however, at IDF in the spring of 2006, Intel advertised both. Wolfdale-DP and all quad-core processors except Dunnington QC are multi-chip modules combining two dies, for the 65 nm processors, the same product code can be shared by processors with different dies, but the specific information about which one is used can be derived from the stepping
18.
Pentium Pro
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The Pentium Pro is a sixth-generation x86 microprocessor developed and manufactured by Intel introduced in November 1,1995. It introduced the P6 microarchitecture and was intended to replace the original Pentium in a full range of applications. While the Pentium and Pentium MMX had 3.1 and 4.5 million transistors, respectively, the Pentium Pro contained 5.5 million transistors. Later, it was reduced to a narrow role as a server and high-end desktop processor and was used in supercomputers like ASCI Red. The Pentium Pro was capable of both dual- and quad-processor configurations and it only came in one form factor, the relatively large rectangular Socket 8. The Pentium Pro was succeeded by the Pentium II Xeon in 1998, the lead architect of Pentium Pro was Fred Pollack who was specialized in superscalarity and had also worked as the lead engineer of Intel iAPX432. The Pentium Pro incorporated a new microarchitecture in a departure from the Pentium x86 architecture and it has a decoupled, 14-stage superpipelined architecture which used an instruction pool. The Pentium Pro featured many advanced concepts not found in the Pentium, the Pentium Pro thus featured out of order execution, including speculative execution via register renaming. It also had a wider 36-bit address bus, allowing it to access up to 64GB of memory, the Pentium Pro has an 8 KiB instruction cache, from which up to 16 bytes are fetched on each cycle and sent to the instruction decoders. The decoders are not equal in capability, only one can decode any x86 instruction and this restricts the Pentium Pros ability to decode multiple instructions simultaneously, limiting superscalar execution. X86 instructions are decoded into 118-bit micro-operations, the micro-ops are RISC-like, that is, they encode an operation, two sources, and a destination. The general decoder can generate up to four micro-ops per cycle, thus, x86 instructions that operate on the memory can only be processed by the general decoder, as this operation requires a minimum of three micro-ops. Likewise, the simple decoders are limited to instructions that can be translated into one micro-op, instructions that require more micro-ops than four are translated with the assistance of a sequencer, which generates the required micro-ops over multiple clock cycles. Micro-ops exit the re-order buffer and enter a station, where they await dispatch to the execution units. In each clock cycle, up to five micro-ops can be dispatched to five execution units, the Pentium Pro has a total of six execution units, two integer units, one floating-point unit, a load unit, store address unit, and a store data unit. Of the two units, only one has the full complement of functions such as a barrel shifter, multiplier and divider. The second integer unit, which shares paths with the FPU, does not have facilities and is limited to simple operations such as add, subtract. Addition and multiplication are pipelined and have a latency of three and five cycles, respectively, division and square-root are not pipelined and are executed in separate units that share the FPUs ports
19.
Pentium III
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The Pentium III brand refers to Intels 32-bit x86 desktop and mobile microprocessors based on the sixth-generation P6 microarchitecture introduced on February 26,1999. The brands initial processors were very similar to the earlier Pentium II-branded microprocessors, the most notable differences were the addition of the SSE instruction set, and the introduction of a controversial serial number embedded in the chip during the manufacturing process. Similarly to the Pentium II it superseded, the Pentium III was also accompanied by the Celeron brand for lower-end versions, and the Xeon for high-end derivatives. The Pentium III was eventually superseded by the Pentium 4, but its Tualatin core also served as the basis for the Pentium M CPUs, the first Pentium III variant was the Katmai. It was a development of the Deschutes Pentium II. The Pentium III saw an increase of 2 million transistors over the Pentium II and it was first released at speeds of 450 and 500 MHz in February 1999. Two more versions were released,550 MHz on May 17,1999 and 600 MHz on August 2,1999, on September 27,1999 Intel released the 533B and 600B running at 533 &600 MHz respectively. The B suffix indicated that it featured a 133 MHz FSB, the Katmai contains 9.5 million transistors, not including the 512 Kbytes L2 cache, and has dimensions of 12.3 mm by 10.4 mm. It is fabricated in Intels P856.5 process, a 0.25 micrometre CMOS process with five levels of aluminum interconnect, the Katmai used the same slot-based design as the Pentium II but with the newer SECC2 cartridge that allowed direct CPU core contact with the heat sink. There have been some early models of the Pentium III with 450 and 500 MHz packaged in an older SECC cartridge intended for OEMs, a notable stepping for enthusiasts was SL35D. This version of Katmai was officially rated for 450 MHz, but often contained cache chips for the 600 MHz model and thus usually was capable of running at 600 MHz. The second version, codenamed Coppermine, was released on October 25,1999, running at 500,533,550,600,650,667,700, and 733 MHz. From December 1999 to May 2000, Intel released Pentium IIIs running at speeds of 750,800,850,866,900,933 and 1000 MHz, both 100 MHz FSB and 133 MHz FSB models were made. An E was appended to the name to indicate cores using the new 0.18 μm fabrication process. An additional B was later appended to designate 133 MHz FSB models, however, AMD were able to clock the Athlon higher, reaching speeds of 1.2 GHz before the launch of the Pentium 4. The Coppermine core was unable to reach the 1.13 GHz speed without various tweaks to the processors microcode, effective cooling, additional voltage. Intel only officially supported the processor on its own VC820 i820-based motherboard, in benchmarks that were stable, performance was shown to be sub-par, with the 1.13 GHz CPU equalling a 1.0 GHz model. Toms Hardware attributed this performance deficit to relaxed tuning of the CPU, Intel needed at least six months to resolve the problems using a new cD0 stepping and re-released 1.1 GHz and 1.13 GHz versions in 2001
20.
Celeron
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Celeron is a brand name given by Intel Corp. to a number of different low end IA-32 and x86-64 computer microprocessor models targeted at budget personal computers. Celeron processors can run all IA-32 computer programs, but their performance is significantly lower when compared to similar CPUs with higher-priced Intel CPU brands. For example, the Celeron brand will often have less cache memory and these missing features can have a variable impact on performance, but is often very substantial. While a few of the Celeron designs have achieved surprising performance and this has been the primary justification for the higher cost of other Intel CPU brands versus the Celeron range. Introduced in April 1998, the first Celeron branded CPU was based on the Pentium II branded core, subsequent Celeron branded CPUs were based on the Pentium III, Pentium 4, Pentium M, and Intel Core branded processors. The latest Celeron design is based on the sixth generation Core i3/i5/i7 series and this design features independent processing cores, but with only 66% as much cache memory as the comparable Core i3 offering. As a product concept, the Celeron was introduced in response to Intels loss of the market, in particular to the Cyrix 6x86, the AMD K6. Intels existing low-end product, the Pentium MMX, was no longer performance competitive at 233 MHz, instead, Intel pursued a budget part that was pin-compatible with their high-end Pentium II product, using the Pentium IIs Slot 1 interface. Intel hired marketing firm Lexicon Branding, which had come up with the name Pentium. The San Jose Mercury News described Lexicons reasoning behind the name they chose, Celeron is seven letters and three syllables, like Pentium. The Cel of Celeron rhymes with tel of Intel, the first Covington Celeron was essentially a 266 MHz Pentium II manufactured without any secondary cache at all. Covington also shared the 80523 product code of Deschutes, although clocked at 266 or 300 MHz, the cacheless Celerons were a good deal slower than the parts they were designed to replace. Substantial numbers were sold on first release, largely on the strength of the Intel name, but the Celeron quickly achieved a poor reputation both in the trade press and among computer professionals. The initial market interest faded rapidly in the face of its poor performance, nevertheless, the first Celerons were quite popular among some overclockers, for their flexible overclockability and reasonable price. Covington was only manufactured in Slot 1 SEPP format, the Mendocino Celeron, launched 24 August 1998, was the first retail CPU to use on-die L2 cache. Whereas Covington had no secondary cache at all, Mendocino included 128 KB of L2 cache running at full clock rate, the first Mendocino-core Celeron was clocked at a then-modest 300 MHz but offered almost twice the performance of the old cacheless Covington Celeron at the same clock rate. To distinguish it from the older Covington 300 MHz, Intel called the Mendocino core Celeron 300A, although the other Mendocino Celerons did not have an A appended, some people call all Mendocino processors Celeron-A regardless of clock rate. The new Mendocino-core Celeron was a performer from the outset
21.
Nehalem (microarchitecture)
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Nehalem /nəˈheɪləm/ is the codename for an Intel processor microarchitecture, which is the successor to the older Core microarchitecture. The first generation of the Intel Core series of processors, Nehalem designs led to the introduction of Core i7, the subsequent Westmere and Sandy Bridge designs would include Core i3 processors. Nehalem is a recycled Intel codename and namesake of the Nehalem River and it is an architecture that differs radically from Netburst, while retaining some of the latters minor features. Nehalem-based microprocessors use the 45 nm process, run at higher clock speeds, hyper-threading is reintroduced, along with a reduction in L2 cache size, as well as an enlarged L3 cache that is shared among all cores. Nehalem was replaced with the Sandy Bridge microarchitecture, released in January 2011, cache line block on L2/L3 cache was reduced from 128 bytes in Netburst & Conroe/Penryn to 64 bytes per line in this generation. 4–12 MB L3 cache Instruction Fetch Unit containing second-level branch predictor with two level Branch Target Buffer and Return Stack Buffer, Nehalem also supports all predictor types previously used in Intels processors like Indirect Predictor and Loop Detector. Second level unified TLB that contains 512 entries for small pages only,3 integer ALU,2 vector ALU and 2 AGU per core. 20 to 24 pipeline stages It has been reported that Nehalem has a focus on performance, overclocking is possible with Bloomfield processors and the X58 chipset. Lynnfield processors use a PCH removing the need for a northbridge, Nehalem processors incorporate SSE4.2 SIMD instructions, adding seven new instructions to the SSE4.1 set in the Core 2 series. The Nehalem architecture reduces atomic operation latency by 50% in an attempt to eliminate overhead on atomic operations such as the LOCK CMPXCHG compare-and-swap instruction, lynnfield processors feature 16 PCIe lanes, which can be used in 1x16 or 2x8 configuration. 16500 series scalable up to 2 sockets,7500 series scalable up to 4/8 sockets, Intel states the Gainestown processors have six memory channels. Gainestown processors have dual QPI links and have a set of memory registers for each link in effect. The successor to Nehalem and Westmere is Sandy Bridge, list of Intel CPU microarchitectures Tick-Tock model Nehalem processor at Intel. com
22.
Die (integrated circuit)
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A die in the context of integrated circuits is a small block of semiconducting material, on which a given functional circuit is fabricated. Typically, integrated circuits are produced in batches on a single wafer of electronic-grade silicon or other semiconductor through processes such as photolithography. The wafer is cut into pieces, each containing one copy of the circuit. Each of these pieces is called a die, there are three commonly used plural forms, dice, dies, and die
23.
Tom's Hardware
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Toms Hardware is an online publication owned by Purch Group and focused on technology. It was founded in 1996 by Thomas Pabst and it provides articles, news, price comparisons, videos and reviews on computer hardware and high technology. The site features coverage on CPUs, motherboards, RAM, graphics and displays, storage, Toms Hardware has a forum and featured blogs. A unique aspect of Toms Hardware is the Build Your Own section where readers can learn how to build their own computers and it is published in several languages. April 1996 – Website founded in the United States by the German medical doctor Thomas Pabst, august 1998 – The company publishes a hardware book in cooperation with Macmillan Publishers. March 1999 – Establishes testing lab in Pleasanton, California, United States, october 1999 – Set up of Toms Guides Publishing AG in Germany. June 2003 – Italian website goes live, april 2007 – TG Publishing, parent company of Toms Hardware, is acquired by the French company Bestofmedia Group. May 2007 – Toms Hardware and iRobot launch a contest for aspiring roboticists, september 2007 – Company rebrands TwitchGuru to Toms Games and Gear Digest to Toms Guide. February 2008 – Presence-PC become the French version of Toms Hardware, november 2008 – Toms Hardware launches first worldwide overclocking championship. August 2010 – AfterDawn launch Toms Hardware in Finland, july 2013 - Bestofmedia Group, the parent company of Toms Hardware, is acquired by TechMediaNetwork, Inc. April 2014 - TechMediaNetwork, the parent company of Toms Hardware, anandtech CNET The Tech Report List of Internet forums Official website
24.
Network interface controller
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A network interface controller is a computer hardware component that connects a computer to a computer network. Early network interface controllers were commonly implemented on expansion cards that plugged into a computer bus, the low cost and ubiquity of the Ethernet standard means that most newer computers have a network interface built into the motherboard. The network controller implements the electronic circuitry required to communicate using a physical layer and data link layer standard such as Ethernet, Fibre Channel. The NIC allows computers to communicate over a network, either by using cables or wirelessly. Although other network technologies exist, IEEE802 networks including the Ethernet variants have achieved near-ubiquity since the mid-1990s, newer server motherboards may even have dual network interfaces built-in. The Ethernet capabilities are integrated into the motherboard chipset or implemented via a low-cost dedicated Ethernet chip. A separate network card is not required unless additional interfaces are needed or some type of network is used. The NIC may use one or more of the techniques to indicate the availability of packets to transfer. Interrupt-driven I/O is where the peripheral alerts the CPU that it is ready to transfer data, also, NICs may use one or more of the following techniques to transfer packet data, Programmed input/output is where the CPU moves the data to or from the NIC to memory. Direct memory access is where some other device other than the CPU assumes control of the bus to move data to or from the NIC to memory. This removes load from the CPU but requires more logic on the card, in addition, a packet buffer on the NIC may not be required and latency can be reduced. There are two types of DMA, third-party DMA in which a DMA controller other than the NIC performs transfers, an Ethernet network controller typically has an 8P8C socket where the network cable is connected. Older NICs also supplied BNC, or AUI connections, a few LEDs inform the user of whether the network is active, and whether or not data transmission occurs. Ethernet network controllers typically support 10 Mbit/s Ethernet,100 Mbit/s Ethernet, such controllers are designated as 10/100/1000, meaning that they can support a notional maximum transfer rate of 10,100 or 1000 Mbit/s. 10 Gigabit Ethernet NICs are also available, and, as of November 2014, are beginning to be available on computer motherboards, multiqueue NICs provide multiple transmit and receive queues, allowing packets received by the NIC to be assigned to one of its receive queues. The hardware-based distribution of the interrupts, described above, is referred to as receive-side scaling, purely software implementations also exist, such as the receive packet steering and receive flow steering. Examples of such implementations are the RFS and Intel Flow Director, with multiqueue NICs, additional performance improvements can be achieved by distributing outgoing traffic among different transmit queues. By assigning different transmit queues to different CPUs/cores, various operating systems internal contentions can be avoided and those NICs support, Accessing local and remote memory without involving the remote CPU
25.
Arm Holdings
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ARM Holdings plc is a British multinational semiconductor and software design company, owned by SoftBank Group. It is considered to be dominant for processors in mobile phones. The company is one of the best-known Silicon Fen companies, processors based on designs licensed from ARM, or designed by licensees of one of the ARM instruction set architectures, are used in all classes of computing devices. ARMs Mali line of processing units are used in laptops, in over 50% of Android tablets by market share. It is the third most popular GPU in mobile devices, ARMs main CPU competitors in servers include Intel and AMD. In mobile applications, Intels x86 Atom is a competitor, AMD also sells ARM based chips as well as x86, Imagination Technologies offers another RISC design for embedded systems. ARMs main GPU competitors include mobile GPUs from Imagination Technologies, Qualcomm and increasingly Nvidia, despite competing within GPUs, Qualcomm and Nvidia have combined their GPUs with an ARM licensed CPU. ARM had a listing on the London Stock Exchange and was a constituent of the FTSE100 Index. It has a listing on NASDAQ. However Japanese telecommunications company SoftBank Group made an offer for ARM on 18 July 2016, subject to approval by ARMs shareholders. The transaction was completed on 5 September 2016, the acronym ARM was first used in 1983 and originally stood for Acorn RISC Machine. Acorn Computers first RISC processor was used in the original Acorn Archimedes and was one of the first RISC processors used in small computers. However, when the company was incorporated in 1990, the acronym was changed to Advanced RISC Machines, at the time of the IPO in 1998, the company name was changed to ARM Holdings, often just called ARM like the processors. The company was founded in November 1990 as Advanced RISC Machines Ltd, the new company intended to further the development of the Acorn RISC Machine processor, which was originally used in the Acorn Archimedes and had been selected by Apple for their Newton project. Its first profitable year was 1993, the companys Silicon Valley and Tokyo offices were opened in 1994. ARM invested in Palmchip Corporation in 1997 to provide system on chip platforms, in 1998 the Company changed its name from Advanced RISC Machines Ltd to ARM Ltd. The Company was first listed on the London Stock Exchange and NASDAQ in 1998 and by February 1999, in 2010, ARM joined with IBM, Texas Instruments, Samsung, ST-Ericsson and Freescale Semiconductor in forming a non-profit open source engineering company, Linaro. ARM also acquired the team of PowerEscape
26.
Computer multitasking
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In computing, multitasking is a concept of performing multiple tasks over a certain period of time by executing them concurrently. As a result, a computer executes segments of multiple tasks in a manner, while the tasks share common processing resources such as central processing units. Multitasking does not necessarily mean that multiple tasks are executing at exactly the same time, even on multiprocessor or multicore computers, which have multiple CPUs/cores so more than one task can be executed at once, multitasking allows many more tasks to be run than there are CPUs. In the case of a computer with a single CPU, only one task is said to be running at any point in time, multitasking solves the problem by scheduling which task may be the one running at any given time, and when another waiting task gets a turn. The act of reassigning a CPU from one task to one is called a context switch. Multiprogramming systems are designed to maximize CPU usage, in time-sharing systems, the running task is required to relinquish the CPU, either voluntarily or by an external event such as a hardware interrupt. Time sharing systems are designed to allow programs to execute apparently simultaneously. In real-time systems, some waiting tasks are guaranteed to be given the CPU when an event occurs. Real time systems are designed to control devices such as industrial robots. The term multitasking has become a term, as the same word is used in many other languages such as German, Italian, Dutch, Danish. In the early days of computing, CPU time was expensive, when the computer ran a program that needed access to a peripheral, the central processing unit would have to stop executing program instructions while the peripheral processed the data. The first computer using a system was the British Leo III owned by J. Lyons. During batch processing, several different programs were loaded in the memory. When the first program reached an instruction waiting for a peripheral, the context of program was stored away. The process continued until all programs finished running, multiprogramming doesnt give any guarantee that a program will run in a timely manner. Indeed, the very first program may very well run for hours without needing access to a peripheral. As there were no users waiting at a terminal, this was no problem, users handed in a deck of punched cards to an operator. Multiprogramming greatly reduced wait times when multiple batches were being processed, the expression time sharing usually designated computers shared by interactive users at terminals, such as IBMs TSO, and VM/CMS
27.
Ars Technica
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Ars Technica is a website covering news in technology, science, politics, and society, created by Ken Fisher and Jon Stokes in 1998. It publishes news, reviews, and guides on issues such as hardware and software, science, technology policy. Many of the writers are postgraduates and some work for research institutions. Articles on the website are written in a less-formal tone than those in traditional journals, Ars Technica was privately owned until May 2008, when it was sold to Condé Nast Digital, the online division of Condé Nast Publications. Condé Nast purchased the site, along with two others, for $25 million and added it to the companys Wired Digital group, which also includes Wired and, formerly, Reddit. The staff mostly works from home and has offices in Boston, Chicago, London, New York City, the operations of Ars Technica are funded primarily by online advertising, and it has offered a paid subscription service since 2001. The website generated controversy in 2010, when it experimentally prevented readers who used advertisement-blocking software from viewing the site, Ken Fisher and Jon Stokes created the Ars Technica website and limited liability company in 1998. Its purpose was to publish computer hardware- and software-related news articles and guides, in their words, the best multi-OS, PC hardware, having fun, being productive, and being as informative and as accurate as possible. Ars technica is a Latin phrase that translates to technological art, the website published news, reviews, guides, and other content of interest to computer enthusiasts. On May 19,2008, Ars Technica was sold to Condé Nast Digital, the sale was part of a purchase by Condé Nast Digital of three unaffiliated websites costing $25 million in total, Ars Technica, Webmonkey, and HotWired. Ars Technica was added to the companys Wired Digital group, which included Wired, Fisher, Stokes, and the eight other writers at the time were employed by Condé Nast, with Fisher as editor-in-chief. Layoffs at Condé Nast in November 2008 affected websites owned by the company across the board, on May 5,2015, Ars Technica launched its United Kingdom site to expand its coverage of issues related to the U. K. and Europe. The U. K. site began with around 500,000 readers and had reached roughly 1.4 million readers a year after its launch. The content of articles published by Ars Technica has generally remained the same since its creation in 1998 and are categorized by four types, news, guides, reviews, Ars Technica also hosts OpenForum, a free Internet forum for the discussion of a variety of topics. Originally, most news articles published by the website were relayed from other technology-related websites, Ars Technica provided short commentary on the news, generally a few paragraphs, and a link to the original source. After being purchased by Condé Nast, Ars Technica began publishing more news, investigating topics. A significant portion of the articles published there now are original. Relayed news is published on the website, ranging from one or two sentences to a few paragraphs
28.
AnandTech
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AnandTech is an online computer hardware magazine. It was founded in 1997 by then-14-year-old Anand Lal Shimpi, who served as CEO and editor-in-chief until August 30,2014 and its investigative articles have been cited by other technology news sites like PC Magazine and The Inquirer. Some of their articles on the mass market products like mobile phones are syndicated by CNNMoney. The large accompanying forum is recommended by some books for bargain hunting in the technology field, AnandTech was acquired by Purch on 17 December 2014. In its early stages, Matthew Witheiler served as co-owner and Senior Hardware Editor, creating insightful, in 2004 AnandTech added a feature to search for computer prices via a price engine developed in house by the senior editor as a graduate project in data mining. This price engine is called RTPE, in 2006 an AnandTech editor launched a spin-off called DailyTech, a technology news site. The move followed an evolution of the news section of AnandTechs peer publication, Toms Hardware Guide. On August 30,2014, Anand announced his decision to retire from the publishing industry to work at Apple. On December 17,2014, Purch announced the acquisition of Anandtech. com, describing AnandTech in 2008, author Paul McFedries wrote that its heart and its claim to fame is the massive collection of incredibly in-depth reviews. In 2008, blogging expert Bruce C. Brown called AnandTech one of the big dogs in the tech field, AnandTech has over 350,000 registered users and over 35 million posts. The AnandTech forums are home to distributive computing teams known collectively as TeAm AnandTech, AnandTech contains a wide variety of sub-forums, including the casual environment of AnandTech Off-Topic to the far more technical Highly Technical forum. AnandTech also maintains several highly regulated e-commerce forums, such as Hot Deals, in July 2007, the forum underwent major changes that site administrators stated as necessary for furthering userbase growth. The profanity filter was removed, and the identities of traditionally anonymous volunteer moderators were revealed, many sub-forums were restructured and added in this overhaul as well. CNET Maximum PC The Tech Report Toms Hardware ZDNet List of Internet forums Official website
29.
International Standard Book Number
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The International Standard Book Number is a unique numeric commercial book identifier. An ISBN is assigned to each edition and variation of a book, for example, an e-book, a paperback and a hardcover edition of the same book would each have a different ISBN. The ISBN is 13 digits long if assigned on or after 1 January 2007, the method of assigning an ISBN is nation-based and varies from country to country, often depending on how large the publishing industry is within a country. The initial ISBN configuration of recognition was generated in 1967 based upon the 9-digit Standard Book Numbering created in 1966, the 10-digit ISBN format was developed by the International Organization for Standardization and was published in 1970 as international standard ISO2108. Occasionally, a book may appear without a printed ISBN if it is printed privately or the author does not follow the usual ISBN procedure, however, this can be rectified later. Another identifier, the International Standard Serial Number, identifies periodical publications such as magazines, the ISBN configuration of recognition was generated in 1967 in the United Kingdom by David Whitaker and in 1968 in the US by Emery Koltay. The 10-digit ISBN format was developed by the International Organization for Standardization and was published in 1970 as international standard ISO2108, the United Kingdom continued to use the 9-digit SBN code until 1974. The ISO on-line facility only refers back to 1978, an SBN may be converted to an ISBN by prefixing the digit 0. For example, the edition of Mr. J. G. Reeder Returns, published by Hodder in 1965, has SBN340013818 -340 indicating the publisher,01381 their serial number. This can be converted to ISBN 0-340-01381-8, the check digit does not need to be re-calculated, since 1 January 2007, ISBNs have contained 13 digits, a format that is compatible with Bookland European Article Number EAN-13s. An ISBN is assigned to each edition and variation of a book, for example, an ebook, a paperback, and a hardcover edition of the same book would each have a different ISBN. The ISBN is 13 digits long if assigned on or after 1 January 2007, a 13-digit ISBN can be separated into its parts, and when this is done it is customary to separate the parts with hyphens or spaces. Separating the parts of a 10-digit ISBN is also done with either hyphens or spaces, figuring out how to correctly separate a given ISBN number is complicated, because most of the parts do not use a fixed number of digits. ISBN issuance is country-specific, in that ISBNs are issued by the ISBN registration agency that is responsible for country or territory regardless of the publication language. Some ISBN registration agencies are based in national libraries or within ministries of culture, in other cases, the ISBN registration service is provided by organisations such as bibliographic data providers that are not government funded. In Canada, ISBNs are issued at no cost with the purpose of encouraging Canadian culture. In the United Kingdom, United States, and some countries, where the service is provided by non-government-funded organisations. Australia, ISBNs are issued by the library services agency Thorpe-Bowker
30.
Computer architecture
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In computer engineering, computer architecture is a set of rules and methods that describe the functionality, organization, and implementation of computer systems. Some definitions of architecture define it as describing the capabilities and programming model of a computer, in other definitions computer architecture involves instruction set architecture design, microarchitecture design, logic design, and implementation. The first documented computer architecture was in the correspondence between Charles Babbage and Ada Lovelace, describing the analytical engine, johnson had the opportunity to write a proprietary research communication about the Stretch, an IBM-developed supercomputer for Los Alamos National Laboratory. Brooks went on to develop the IBM System/360 line of computers. Later, computer users came to use the term in many less-explicit ways, the earliest computer architectures were designed on paper and then directly built into the final hardware form. The discipline of architecture has three main subcategories, Instruction Set Architecture, or ISA. The ISA defines the code that a processor reads and acts upon as well as the word size, memory address modes, processor registers. Microarchitecture, or computer organization describes how a processor will implement the ISA. The size of a computers CPU cache for instance, is an issue that generally has nothing to do with the ISA, system Design includes all of the other hardware components within a computing system. These include, Data processing other than the CPU, such as memory access Other issues such as virtualization, multiprocessing. There are other types of computer architecture, E. g. the C, C++, or Java standards define different Programmer Visible Macroarchitecture. UISA —a group of machines with different hardware level microarchitectures may share a common microcode architecture, pin Architecture, The hardware functions that a microprocessor should provide to a hardware platform, e. g. the x86 pins A20M, FERR/IGNNE or FLUSH. Also, messages that the processor should emit so that external caches can be invalidated, pin architecture functions are more flexible than ISA functions because external hardware can adapt to new encodings, or change from a pin to a message. The term architecture fits, because the functions must be provided for compatible systems, the purpose is to design a computer that maximizes performance while keeping power consumption in check, costs low relative to the amount of expected performance, and is also very reliable. For this, many aspects are to be considered which includes Instruction Set Design, Functional Organization, Logic Design, the implementation involves Integrated Circuit Design, Packaging, Power, and Cooling. Optimization of the design requires familiarity with Compilers, Operating Systems to Logic Design, an instruction set architecture is the interface between the computers software and hardware and also can be viewed as the programmers view of the machine. Computers do not understand high level languages such as Java, C++, a processor only understands instructions encoded in some numerical fashion, usually as binary numbers. Software tools, such as compilers, translate those high level languages into instructions that the processor can understand, besides instructions, the ISA defines items in the computer that are available to a program—e. g
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