The MC88100 is a microprocessor developed by Motorola that implemented 88000 instruction set architecture. Announced in 1988, the MC88100 was the first 88000 implementation, it was succeeded by the MC88110 in the early 1990s. The microprocessor was a superscalar design with multiple integer and floating-point units that executed instructions in-order; the MC88100 had separate instruction and data caches. These caches were implemented with the MC88200 integrated circuit, which contains a memory management unit and an amount of cache; the MC88100 requires two of these devices for each cache, additional MC88200s could be added to increase the size of the caches. This partitioned scheme was chosen to provide system flexibility, the amount of cache could be varied depending on the price point. In practice, these additional chips required more space on the circuit board and the buses between the MC88200s and MC88100 added complexity and cost; the MC88100 contained the MC88200 750,000 transistors. Both were fabricated by Motorola in its 1.5 μm complementary metal–oxide–semiconductor process.
The MC88100 was commercially unsuccessful. This was due to a number of reasons, including requirement of MC88200s, but was due to Motorola being a vendor of the successful 68000 family; as the 68000 division viewed the 88000 as a competitor, they forced the MC88100 to be priced unacceptably high for a volume part. The part did find use in the high-end embedded market, in Motorola's own computers, in large computers from companies such as Data General and the Unisys S-8400 Unix Servers. Furber, Stephen Bo. VLSI RISC Architecture and Organization. CRC Press. Pp. 184–192. Tabak, Daniel. RISC Systems. Research Studies Press. Pp. 121–143. Tabak, Daniel. Advanced Microprocessors. McGraw-Hill. Pp. 433–434, 437
The Motorola 68020 is a 32-bit microprocessor from Motorola, released in 1984. It is the successor to the Motorola 68010 and is succeeded by the Motorola 68030. A lower cost version was made available, known as the 68EC020. In keeping with naming practices common to Motorola designs, the 68020 is referred to as the "020", pronounced "oh-two-oh" or "oh-twenty"; the 68020 had 32-bit internal and external data and address buses, compared to the early 680x0 models with 16-bit data and 24-bit address buses. The 68020's ALU was natively 32-bit, so could perform 32-bit operations in one clock, whereas the 68000 took two clocks minimum due to its 16-bit ALU. Newer packaging methods allowed the'020 to feature more external pins without the large size that the earlier dual in-line package method required; the 68EC020 lowered cost through a 24-bit address bus. The 68020 was produced at speeds ranging from 12 MHz to 33 MHz; the 68020 added many improvements over the 68010 including a 32-bit arithmetic logic unit, 32-bit external data and address buses, extra instructions and additional addressing modes.
The 68020 had a proper three-stage pipeline. Though the 68010 had a "loop mode", which sped loops through what was a tiny instruction cache, it held only two short instructions and was thus little used; the 68020 replaced this with a proper instruction cache of 256 bytes, the first 68k series processor to feature true on-chip cache memory. The previous 68000 and 68010 processors could only access word and long word data in memory if it were word-aligned; the 68020 had no alignment restrictions on data access. Unaligned accesses were slower than aligned accesses because they required an extra memory access; the 68020 has a coprocessor interface supporting up to eight coprocessors. The main CPU recognizes "F-line" instructions, uses special bus cycles to interact with a coprocessor to execute these instructions. Two types of coprocessors were defined, the floating point unit and the paged memory management unit. Only one PMMU can be used with a CPU. In principle multiple FPUs could be used with a CPU, but it was not done.
The coprocessor interface is asynchronous, so it is possible to run the coprocessors at a different clock rate than the CPU. Multiprocessing support was implemented externally by the use of a RMC pin to indicate an indivisible read-modify-write cycle in progress. All other processors had to hold off memory accesses. Software support for multiprocessing included the CAS and CAS2 instructions. In a multiprocessor system, coprocessors could not be shared between CPUs. To avoid problems with returns from coprocessor, bus error, address error exceptions, it was necessary in a multiprocessor system for all CPUs to be the same model, for all FPUs to be the same model as well; the new instructions included some minor improvements and extensions to the supervisor state, several instructions for software management of a multiprocessing system, some support for high-level languages which did not get used much, bigger multiply and divide instructions, bit field manipulations. While the 68000 had'supervisor mode', it did not meet the Popek and Goldberg virtualization requirements due to the single instruction'MOVE from SR' being unprivileged but sensitive.
Under the 68010 and this was made privileged, to better support virtualization software. The new addressing modes added scaled indexing and another level of indirection to many of the pre-existing modes, added quite a bit of flexibility to various indexing modes and operations. Though it was not intended, these new modes made the 68020 suitable for page printing; the 68020 had a small 256-byte direct-mapped instruction cache, arranged as 64 four-byte entries. Although small, it still made a significant difference in the performance of many applications; the resulting decrease in bus traffic was important in systems relying on DMA. The 68020 was used in the Apple Macintosh II and Macintosh LC personal computers, Sun 3 workstations, Commodore Amiga 1200, the Hewlett-Packard 8711 Series Network Analyzers and members of the HP 9000/300 family and the Alpha Microsystems AM-2000; the 68020 was an alternative upgrade to the Sinclair QL computer's 68008 in the Super Gold Card interface by Miracle Systems.
The Amiga 2500 and A2500UX was shipped with the A2620 Accelerator using a 68020, a 68881 floating point unit and the 68851 Memory Management Unit. The 2500UX shipped with Amiga Unix, requiring an'020 or'030 processor. A number of digital oscilloscopes from the mid-80s to the late-90s used the 68020, including the LeCroy 9300 Series and the earlier LeCroy 9400 series, along with certain Tektronix TDS Series models.. The HP 54520, 54522, 54540 and 54542 use the 68020, together with a 68882 math coprocessor, it is the processor used on board TGV trains to decode signalling information, sent to the trains through the rails. It is further being used in the flight control and radar systems of the Eurofighter Typhoon combat aircraft; the Nortel Networks DMS-100 telephone central office switch used the
The Atari ST is a line of home computers from Atari Corporation and the successor to the Atari 8-bit family. The initial ST model, the 520ST, saw limited release in April–June 1985 and was available in July; the Atari ST is the first personal computer to come with a bitmapped color GUI, using a version of Digital Research's GEM released in February 1985. The 1040ST, released in 1986, is the first personal computer to ship with a megabyte of RAM in the base configuration and the first with a cost-per-kilobyte of less than US$1; the Atari ST is part of a mid-1980s generation of home computers that have 16 or 32-bit processors, 256 KB or more of RAM, mouse-controlled graphical user interfaces. This generation includes the Macintosh, Commodore Amiga, Apple IIGS, and, in certain markets, the Acorn Archimedes. "ST" stands for "Sixteen/Thirty-two", which refers to the Motorola 68000's 16-bit external bus and 32-bit internals. The ST was sold with the less expensive monochrome monitor; the system's two color graphics modes are only available on the former while the highest-resolution mode needs the monochrome monitor.
In some markets Germany, the machine gained a strong foothold as a small business machine for CAD and desktop publishing work. Thanks to its built-in MIDI ports, the ST enjoyed success for running music-sequencer software and as a controller of musical instruments among amateurs and well-known musicians alike; the ST was superseded by the Atari STE, Atari TT, Atari MEGA STE, Falcon computers. The Atari ST was born from the rivalry between home-computer makers Atari, Inc. and Commodore International. Jay Miner, one of the original designers for the custom chips found in the Atari 2600 and Atari 8-bit family, tried to convince Atari management to create a new chipset for a video game console and computer; when his idea was rejected, Miner left Atari to form a small think tank called Hi-Toro in 1982 and began designing the new "Lorraine" chipset. The company, renamed Amiga Corporation, was pretending to sell video game controllers to deceive competition while it developed a Lorraine-based computer.
Amiga ran out of capital to complete Lorraine's development, Atari, owned by Warner Communications, paid Amiga to continue development work. In return Atari received exclusive use of the Lorraine design for one year as a video game console. After one year Atari would have the right to add a keyboard and market the complete computer, designated the 1850XLD; as Atari was involved with Disney at the time, it was code-named "Mickey", the 256K memory expansion board was codenamed "Minnie". After leaving Commodore International in January 1984, Jack Tramiel formed Tramel Technology with his sons and other ex-Commodore employees and, in April, began planning a new computer; the company considered the National Semiconductor NS320xx microprocessor but was disappointed with its performance. This started the move to the 68000; the lead designer of the Atari ST was ex-Commodore employee Shiraz Shivji, who had worked on the Commodore 64's development. Atari in mid-1984 was losing about a million dollars per day.
Interested in Atari's overseas manufacturing and worldwide distribution network for his new computer, Tramiel negotiated with Warner in May and June 1984. He bought Atari's Consumer Division in July; as executives and engineers left Commodore to join Tramiel's new Atari Corporation, Commodore responded by filing lawsuits against four former engineers for theft of trade secrets. The Tramiels did not purchase the employee contracts when they bought the assets of Atari Inc. so one of their first acts was to interview Atari Inc. employees to decide whom to hire at what was a brand new company. This company was called TTL renamed to Atari Corp. At the time of the purchase of Atari Inc's assets, there were 900 employees remaining from a high point of 10,000. After the interviews 100 employees were hired to work at Atari Corp. At one point a custom sound processor called AMY was a planned component for the new ST computer design, but the chip needed more time to complete, so AMY was dropped in favor of an off-the-shelf Yamaha sound chip.
It was during this time in late July/early August that Leonard Tramiel discovered the original Amiga contract, which required Amiga Corporation to deliver the Lorraine chipset to Atari on June 30, 1984. Amiga Corp. had sought more monetary support from investors in spring 1984. Having heard rumors that Tramiel was negotiating to buy Atari, Amiga Corp. entered into discussions with Commodore. The discussions led to Commodore wanting to purchase Amiga Corporation outright, which Commodore believed would cancel any outstanding contracts, including Atari's. Instead of Amiga Corp. delivering Lorraine to Atari, Commodore delivered a check of $500,000 to Atari on Amiga's behalf, in effect returning the funds Atari invested into Amiga for the chipset. Tramiel countersued Amiga Corp. on August 13, 1984. He sought an injunction to bar Amiga from producing anything with its technology. At Commodore, the Amiga team was in limbo during the summer of 1984 because of the lawsuit. No word on the status of the chipset, the Lorraine computer, or the team's fate was known.
In the fall of 1984, Commodore informed the team that the Lorraine project was active again, the chipset was to be improved, the operating system developed, the hardware design completed. While Commodore announced the Amiga 1000 with the Lorraine chipset in July 1985, the delay gave Atari, with its ma
The Amiga is a family of personal computers introduced by Commodore in 1985. The original model was part of a wave of 16- and 32-bit computers that featured 256 KB or more of RAM, mouse-based GUIs, improved graphics and audio over 8-bit systems; this wave included the Atari ST—released the same year—Apple's Macintosh, the Apple IIGS. Based on the Motorola 68000 microprocessor, the Amiga differed from its contemporaries through the inclusion of custom hardware to accelerate graphics and sound, including sprites and a blitter, a pre-emptive multitasking operating system called AmigaOS; the Amiga 1000 was released in July 1985, but a series of production problems kept it from becoming available until early 1986. The best selling model, the Amiga 500, was introduced in 1987 and became one of the leading home computers of the late 1980s and early 1990s with four to six million sold; the A3000, introduced in 1990, started the second generation of Amiga systems, followed by the A500+, the A600 in March 1992.
As the third generation, the A1200 and the A4000 were released in late 1992. The platform became popular for gaming and programming demos, it found a prominent role in the desktop video, video production, show control business, leading to video editing systems such as the Video Toaster. The Amiga's native ability to play back multiple digital sound samples made it a popular platform for early tracker music software; the powerful processor and ability to access several megabytes of memory enabled the development of several 3D rendering packages, including LightWave 3D, Aladdin4D, TurboSilver and Traces, a predecessor to Blender. Although early Commodore advertisements attempt to cast the computer as an all-purpose business machine when outfitted with the Amiga Sidecar PC compatibility add-on, the Amiga was most commercially successful as a home computer, with a wide range of games and creative software. Poor marketing and the failure of the models to repeat the technological advances of the first systems meant that the Amiga lost its market share to competing platforms, such as the fourth generation game consoles and the dropping prices of IBM PC compatibles which gained 256-color VGA graphics in 1987.
Commodore went bankrupt in April 1994 after the Amiga CD32 model failed in the marketplace. Since the demise of Commodore, various groups have marketed successors to the original Amiga line, including Genesi, Eyetech, ACube Systems Srl and A-EON Technology. AmigaOS has influenced replacements and compatible systems such as MorphOS, AmigaOS 4 and AROS. "The Amiga was so far ahead of its time that nobody—including Commodore's marketing department—could articulate what it was all about. Today, it's obvious the Amiga was the first multimedia computer, but in those days it was derided as a game machine because few people grasped the importance of advanced graphics and video. Nine years vendors are still struggling to make systems that work like 1985 Amigas." Jay Miner joined Atari in the 1970s to develop custom integrated circuits, led development of the Atari 2600's TIA. As soon as its development was complete, the team began developing a much more sophisticated set of chips, CTIA, ANTIC and POKEY, that formed the basis of the Atari 8-bit family.
With the 8-bit line's launch in 1979, the team once again started looking at a next generation chipset. Nolan Bushnell had sold the company to Warner Communications in 1978, the new management was much more interested in the existing lines than development of new products that might cut into their sales. Miner wanted to start work with the new Motorola 68000, but management was only interested in another 6502 based system. Miner left the company, for a time, the industry. In 1979, Larry Kaplan founded Activision. In 1982, Kaplan was approached by a number of investors. Kaplan hired Miner to run the hardware side of the newly formed company, "Hi-Toro"; the system was code-named "Lorraine" in keeping with Miner's policy of giving systems female names, in this case the company president's wife, Lorraine Morse. When Kaplan left the company late in 1982, Miner was promoted to head engineer and the company relaunched as Amiga Corporation. A breadboard prototype was completed by late 1983, shown at the January 1984 Consumer Electronics Show.
At the time, the operating system was not ready, so the machine was demonstrated with the Boing Ball demo. A further developed version of the system was demonstrated at the June 1984 CES and shown to many companies in hopes of garnering further funding, but found little interest in a market, in the final stages of the North American video game crash of 1983. In March, Atari expressed a tepid interest in Lorraine for its potential use in a games console or home computer tentatively known as the 1850XLD, but the talks were progressing and Amiga was running out of money. A temporary arrangement in June led to a $500,000 loan from Atari to Amiga to keep the company going; the terms required the loan to be repaid at the end of the month, otherwise Amiga would forfeit the Lorraine design to Atari. During 1983, Atari lost over $1 million a week, due to the combined effects of the crash and the ongoing price war in the home computer market. By the end of the year, Warner was desperate to sell the company.
In January 1984, Jack Tramiel resigned from Commodore due to internal battles over the future direction of the company. A number of Commodore employees followed him to Tramiel Technology; this included a number of the senior technical staff, where they began development of a 68000-based machine of the
The Motorola 68030 is a 32-bit microprocessor in the Motorola 68000 family. It was released in 1987; the 68030 was the successor to the Motorola 68020, was followed by the Motorola 68040. In keeping with general Motorola naming, this CPU is referred to as the 030; the 68030 features 273,000 transistors with on-chip data caches of 256 bytes each. It has an on-chip memory management unit but does not have a built in floating-point unit; the 68881 and the faster 68882 floating point unit chips could be used with the 68030. A lower cost version of the 68030, the Motorola 68EC030, was released, lacking the on-chip MMU, it was available in both 132 pin QFP and 128 pin PGA packages. The poorer thermal characteristics of the QFP package limited the full 68030 QFP variant to 33 MHz. There was a small supply of QFP packaged EC variants; as a microarchitecture, the 68030 is a 68020 core with an additional 256 byte data cache and a process shrink and an added burst mode for the caches, where four longwords can be placed in the cache without further CPU intervention.
Motorola used the process shrink to pack more hardware on the die. The integration of the MMU made it more cost-effective than the 68020 with an external MMU. However, the 68030 can switch between asynchronous buses without a reset; the 68030 lacks some of the 68020's instructions, but it increases performance by ≈5% while reducing power draw by ≈25% compared to the 68020. The 68030 can be used with the 68020 bus, in which case its performance is similar to 68020 that it was derived from. However, the 68030 provides an additional synchronous bus interface which, if used, accelerates memory accesses up to 33% compared to an clocked 68020; the finer manufacturing process allowed Motorola to scale the full-version processor to 50 MHz. The EC variety topped out at 40 MHz; the 68030 was used in many models of the Apple Macintosh II and Commodore Amiga series of personal computers, NeXT Cube Alpha Microsystems multiuser systems, some descendants of the Atari ST line such as the Atari TT and the Atari Falcon.
It was used in Unix workstations such as the Sun Microsystems Sun-3x line of desktop workstations, laser printers and the Nortel Networks DMS-100 telephone central office switch. More the 68030 core has been adapted by Freescale into a microcontroller for embedded applications. LeCroy has used the 68EC030 in certain models of their 9300 Series digital oscilloscopes including “C” suffix models:87-88 and high performance 9300 Series models, along with the Mega Waveform Processing hardware option for 68020-based 9300 Series models; the 68EC030 is a low cost version of the 68030, the difference between the two being that the 68EC030 omits the on-chip memory management unit and is thus an upgraded 68020. The 68EC030 was used as the CPU for the low-cost model of the Amiga 4000, on a number of CPU accelerator cards for the Commodore Amiga line of computers, it was used in the Cisco Systems 2500 Series router, a small-to-medium enterprise computer internetworking appliance. The 50 MHz speed is exclusive to the plastic' 030 stopped at 40 MHz.
This article is based on material taken from the Free On-line Dictionary of Computing prior to 1 November 2008 and incorporated under the "relicensing" terms of the GFDL, version 1.3 or later. 68030 images and descriptions at cpu-collection.de Official information about the Freescale MC68030 microcontroller Motorola 68k family data sheets at bitsavers.org
The 6309 is Hitachi's CMOS version of the Motorola 6809 microprocessor. While in "Emulation Mode" it is compatible with the 6809. To the 6809 specifications it adds higher clock rates, enhanced features, new instructions, additional registers. Most new instructions were added to support the additional registers, as well as up to 32-bit math, hardware division, bit manipulations, block transfers; the 6309 is 30% faster in native mode than the 6809. This information was never published by Hitachi; the April 1988 issue of Oh! FM, a Japanese magazine for Fujitsu personal computer users, contained the first description of the 6309's additional capabilities. Hirotsugu Kakugawa posted details of the 6309's new features and instructions to comp.sys.m6809. This led to the development of NitrOS9 for the Tandy Color Computer 3; the 6309 differs from the 6809 in several key areas. The 6309 is fabricated in CMOS technology; as a result, the 6309 requires less power to operate than the 6809. It is a static device, which will not lose internal state information.
This means it can be used with external DMA without needing refresh every 14 cycles as the 6809 does. The 6309 has B versions. However, a "C" speed rating was produced with either a 3.0 or 3.5 MHz maximum clock rate, depending on which datasheet is referenced.. Anecdotal and individual reports indicate that the 63C09 variant can be clocked at 5 MHz with no ill effects. Like the 6809, the Hitachi CPU comes in both internal and external clock versions When switched into 6309 Native Mode many key instructions will complete in fewer clock cycles; this improves execution speeds by up to 30%. Two 8-bit accumulators:'E' and'F'; these can be concatenated to form 16-bit accumulator'W'. The existing 6809 16-bit accumulator D can be concatenated with W to form 32-bit accumulator'Q', it is that D is short for'Double' and Q for'Quad', the number of bytes they hold. Transfer register'V' for inter-register instructions, its value is unaffected by a hardware reset so it can retain a constant Value, hence'V'. 8/16-bit Zero register' 0' using a zero constant.
This register always writes to it are ignored. Mode register ` MD', a secondary Condition Code register. Only 4 bits of this register are defined. Most of the new instructions are modifications of existing instructions to handle the existence of the additional registers, such as load, store and the like. Genuine 6309 additions include inter-register arithmetic, block transfers, hardware division, bit-level manipulations. Despite the user-friendliness of the additional instructions, analysis by 6809 programming gurus indicates that many of the new instructions are slower than the equivalent 6809 code in tight loops. Careful analysis should be done to ensure that the programmer uses the most efficient code for the particular application, it is possible to change the mode of operation for the FIRQ interrupt. Instead of stacking the PC and CC registers the FIRQ interrupt can be set to stack the entire register set, as the IRQ interrupt does. In addition, the 6309 has two possible trap modes, one for an illegal instruction fetch and one for division by zero.
The illegal instruction fetch is not maskable, many TRS-80 Color Computer users reported that their 6309's were "buggy" when in reality it was an indicator of enhanced and unknown features. Article in the April 1988 issue of Oh! FM Hirotsugu Kakugawa's original "Secret 6309 features memo" and thread on Google's Usenet archive HD63B09EP Technical Reference Guide 6x09 Microprocessor Instruction Sets Instruction set reference for 6809/6309 By Chris Lomont Comparison of 6809 and 6309 instruction listThis article is based on material taken from the Free On-line Dictionary of Computing prior to 1 November 2008 and incorporated under the "relicensing" terms of the GFDL, version 1.3 or later
In computing, floating-point arithmetic is arithmetic using formulaic representation of real numbers as an approximation so as to support a trade-off between range and precision. For this reason, floating-point computation is found in systems which include small and large real numbers, which require fast processing times. A number is, in general, represented to a fixed number of significant digits and scaled using an exponent in some fixed base. A number that can be represented is of the following form: significand × base exponent, where significand is an integer, base is an integer greater than or equal to two, exponent is an integer. For example: 1.2345 = 12345 ⏟ significand × 10 ⏟ base − 4 ⏞ exponent. The term floating point refers to the fact that a number's radix point can "float"; this position is indicated as the exponent component, thus the floating-point representation can be thought of as a kind of scientific notation. A floating-point system can be used to represent, with a fixed number of digits, numbers of different orders of magnitude: e.g. the distance between galaxies or the diameter of an atomic nucleus can be expressed with the same unit of length.
The result of this dynamic range is that the numbers that can be represented are not uniformly spaced. Over the years, a variety of floating-point representations have been used in computers. In 1985, the IEEE 754 Standard for Floating-Point Arithmetic was established, since the 1990s, the most encountered representations are those defined by the IEEE; the speed of floating-point operations measured in terms of FLOPS, is an important characteristic of a computer system for applications that involve intensive mathematical calculations. A floating-point unit is a part of a computer system specially designed to carry out operations on floating-point numbers. A number representation specifies some way of encoding a number as a string of digits. There are several mechanisms. In common mathematical notation, the digit string can be of any length, the location of the radix point is indicated by placing an explicit "point" character there. If the radix point is not specified the string implicitly represents an integer and the unstated radix point would be off the right-hand end of the string, next to the least significant digit.
In fixed-point systems, a position in the string is specified for the radix point. So a fixed-point scheme might be to use a string of 8 decimal digits with the decimal point in the middle, whereby "00012345" would represent 0001.2345. In scientific notation, the given number is scaled by a power of 10, so that it lies within a certain range—typically between 1 and 10, with the radix point appearing after the first digit; the scaling factor, as a power of ten, is indicated separately at the end of the number. For example, the orbital period of Jupiter's moon Io is 152,853.5047 seconds, a value that would be represented in standard-form scientific notation as 1.528535047×105 seconds. Floating-point representation is similar in concept to scientific notation. Logically, a floating-point number consists of: A signed digit string of a given length in a given base; this digit string is referred to mantissa, or coefficient. The length of the significand determines the precision; the radix point position is assumed always to be somewhere within the significand—often just after or just before the most significant digit, or to the right of the rightmost digit.
This article follows the convention that the radix point is set just after the most significant digit. A signed integer exponent. To derive the value of the floating-point number, the significand is multiplied by the base raised to the power of the exponent, equivalent to shifting the radix point from its implied position by a number of places equal to the value of the exponent—to the right if the exponent is positive or to the left if the exponent is negative. Using base-10 as an example, the number 152,853.5047, which has ten decimal digits of precision, is represented as the significand 1,528,535,047 together with 5 as the exponent. To determine the actual value, a decimal point is placed after the first digit of the significand and the result is multiplied by 105 to give 1.528535047×105, or 152,853.5047. In storing such a number, the base need not be stored, since it will be the same for the entire range of supported numbers, can thus be inferred. Symbolically, this final value is: s b p − 1 × b e, where s is the