1.
Central processing unit
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The computer industry has used the term central processing unit at least since the early 1960s. The form, design and implementation of CPUs have changed over the course of their history, most modern CPUs are microprocessors, meaning they are contained on a single integrated circuit chip. An IC that contains a CPU may also contain memory, peripheral interfaces, some computers employ a multi-core processor, which is a single chip containing two or more CPUs called cores, in that context, one can speak of such single chips as sockets. Array processors or vector processors have multiple processors that operate in parallel, there also exists the concept of virtual CPUs which are an abstraction of dynamical aggregated computational resources. Early computers such as the ENIAC had to be rewired to perform different tasks. Since the term CPU is generally defined as a device for software execution, the idea of a stored-program computer was already present in the design of J. Presper Eckert and John William Mauchlys ENIAC, but was initially omitted so that it could be finished sooner. On June 30,1945, before ENIAC was made, mathematician John von Neumann distributed the paper entitled First Draft of a Report on the EDVAC and it was the outline of a stored-program computer that would eventually be completed in August 1949. EDVAC was designed to perform a number of instructions of various types. Significantly, the programs written for EDVAC were to be stored in high-speed computer memory rather than specified by the wiring of the computer. This overcame a severe limitation of ENIAC, which was the considerable time, with von Neumanns design, the program that EDVAC ran could be changed simply by changing the contents of the memory. Early CPUs were custom designs used as part of a larger, however, this method of designing custom CPUs for a particular application has largely given way to the development of multi-purpose processors produced in large quantities. This standardization began in the era of discrete transistor mainframes and minicomputers and has accelerated with the popularization of the integrated circuit. The IC has allowed increasingly complex CPUs to be designed and manufactured to tolerances on the order of nanometers, both the miniaturization and standardization of CPUs have increased the presence of digital devices in modern life far beyond the limited application of dedicated computing machines. Modern microprocessors appear in electronic devices ranging from automobiles to cellphones, the so-called Harvard architecture of the Harvard Mark I, which was completed before EDVAC, also utilized a stored-program design using punched paper tape rather than electronic memory. Relays and vacuum tubes were used as switching elements, a useful computer requires thousands or tens of thousands of switching devices. The overall speed of a system is dependent on the speed of the switches, tube computers like EDVAC tended to average eight hours between failures, whereas relay computers like the Harvard Mark I failed very rarely. In the end, tube-based CPUs became dominant because the significant speed advantages afforded generally outweighed the reliability problems, most of these early synchronous CPUs ran at low clock rates compared to modern microelectronic designs. Clock signal frequencies ranging from 100 kHz to 4 MHz were very common at this time, the design complexity of CPUs increased as various technologies facilitated building smaller and more reliable electronic devices
2.
Front-side bus
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A front-side bus was a computer communication interface often used in Intel-chip-based computers during the 1990s and 2000s. The competing EV6 bus served the function for AMD CPUs. Both typically carry data between the processing unit and a memory controller hub, known as the northbridge. Depending on the implementation, some computers may also have a bus that connects the CPU to the cache. This bus and the connected to it are faster than accessing the system memory via the front-side bus. The speed of the front side bus is used as an important measure of the performance of a computer. The original front-side bus architecture has replaced by HyperTransport, Intel QuickPath Interconnect or Direct Media Interface in modern volume CPUs. The term came into use by Intel Corporation about the time the Pentium Pro and Pentium II products were announced, in the 1990s. Front side refers to the interface from the processor to the rest of the computer system, as opposed to the back side. An FSB is mostly used on PC-related motherboards, seldom with the data and address used in embedded systems. This design represented an improvement over the single system bus designs of the previous decades. Front-side buses usually connect the CPU and the rest of the hardware via a chipset, which Intel implemented as a northbridge and a southbridge. Other buses like the Peripheral Component Interconnect, Accelerated Graphics Port and these secondary system buses usually run at speeds derived from the front-side bus clock, but are not necessarily synchronized to it. In response to AMDs Torrenza initiative, Intel opened its FSB CPU socket to third party devices. Prior to this announcement, made in Spring 2007 at Intel Developer Forum in Beijing, Intel had very closely guarded who had access to the FSB, the first example was Field-programmable gate array co-processors, a result of collaboration between Intel-Xilinx-Nallatech and Intel-Altera-XtremeData. The frequency at which a processor operates is determined by applying a clock multiplier to the bus speed in some cases. For example, a running at 3200 MHz might be using a 400 MHz FSB. This means there is a clock multiplier setting of 8
3.
Instruction set architecture
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An ISA includes a specification of the set of opcodes, and the native commands implemented by a particular processor. An instruction set architecture is distinguished from a microarchitecture, which is the set of design techniques used, in a particular processor. Processors with different microarchitectures can share a common instruction set, for example, the Intel Pentium and the AMD Athlon implement nearly identical versions of the x86 instruction set, but have radically different internal designs. The concept of an architecture, distinct from the design of a machine, was developed by Fred Brooks at IBM during the design phase of System/360. Prior to NPL, the companys computer designers had been free to honor cost objectives not only by selecting technologies, the SPREAD compatibility objective, in contrast, postulated a single architecture for a series of five processors spanning a wide range of cost and performance. In addition, these virtual machines execute less frequently used code paths by interpretation, transmeta implemented the x86 instruction set atop VLIW processors in this fashion. A complex instruction set computer has many specialized instructions, some of which may only be used in practical programs. Theoretically important types are the instruction set computer and the one instruction set computer. Another variation is the very long instruction word where the processor receives many instructions encoded and retrieved in one instruction word, machine language is built up from discrete statements or instructions. Examples of operations common to many instruction sets include, Set a register to a constant value. Copy data from a location to a register, or vice versa. Used to store the contents of a register, result of a computation, often called load and store operations. Read and write data from hardware devices, add, subtract, multiply, or divide the values of two registers, placing the result in a register, possibly setting one or more condition codes in a status register. Increment, decrement in some ISAs, saving operand fetch in trivial cases, perform bitwise operations, e. g. taking the conjunction and disjunction of corresponding bits in a pair of registers, taking the negation of each bit in a register. Floating-point instructions for arithmetic on floating-point numbers, branch to another location in the program and execute instructions there. Conditionally branch to another if a certain condition holds. Call another block of code, while saving the location of the instruction as a point to return to. Load/store data to and from a coprocessor, or exchanging with CPU registers, processors may include complex instructions in their instruction set
4.
Microarchitecture
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A given ISA may be implemented with different microarchitectures, implementations may vary due to different goals of a given design or due to shifts in technology. Computer architecture is the combination of microarchitecture and instruction set, the ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address, the microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. These diagrams generally separate the datapath and the control path, the person designing a system usually draws the specific microarchitecture as a kind of data flow diagram. Like a block diagram, the diagram shows microarchitectural elements such as the arithmetic and logic unit. Typically, the diagram connects those elements with arrows, thick lines, very simple computers have a single data bus organization – they have a single three-state bus. The diagram of more complex computers usually shows multiple three-state buses, each microarchitectural element is in turn represented by a schematic describing the interconnections of logic gates used to implement it. Each logic gate is in turn represented by a circuit diagram describing the connections of the used to implement it in some particular logic family. Machines with different microarchitectures may have the instruction set architecture. In principle, a single microarchitecture could execute several different ISAs with only changes to the microcode. The pipelined datapath is the most commonly used design in microarchitecture today. This technique is used in most modern microprocessors, microcontrollers, the pipelined architecture allows multiple instructions to overlap in execution, much like an assembly line. The pipeline includes several different stages which are fundamental in microarchitecture designs, some of these stages include instruction fetch, instruction decode, execute, and write back. Some architectures include other stages such as memory access, the design of pipelines is one of the central microarchitectural tasks. Execution units are essential to microarchitecture. Execution units include arithmetic logic units, floating point units, load/store units, branch prediction and these units perform the operations or calculations of the processor. The choice of the number of units, their latency. The size, latency, throughput and connectivity of memories within the system are also microarchitectural decisions, system-level design decisions such as whether or not to include peripherals, such as memory controllers, can be considered part of the microarchitectural design process
5.
P6 (microarchitecture)
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The P6 microarchitecture is the sixth-generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is sometimes referred to as i686 and it was succeeded by the NetBurst microarchitecture in 2000, but eventually revived in the Pentium M line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the Core microarchitecture which in turn is derived from the P6 microarchitecture. The P6 core was the sixth generation Intel microprocessor in the x86 line, the first implementation of the P6 core was the Pentium Pro CPU in 1995, the immediate successor to the original Pentium design. Some techniques first used in the x86 space in the P6 core include, Speculative execution and out-of-order completion and this lessened pipeline stalls, and in part enabled greater speed-scaling of the Pentium Pro and successive generations of CPUs. PAE and a wider 36-bit address bus to support 64 GB of physical memory, register renaming, which enabled more efficient execution of multiple instructions in the pipeline. CMOV instructions heavily used in compiler optimization, other new instructions, FCMOV, FCOMI/FCOMIP/FUCOMI/FUCOMIP, RDPMC, UD2. New instructions in Pentium II Deschutes core, FXSAVE, FXRSTOR, new instructions in Pentium III, SSE. The P6 line of processing cores was succeeded with the NetBurst architecture which appeared with the introduction of Pentium 4 and this was a completely different design based on the use of very long pipelines that favoured high clock speed at the cost of lower IPC, and higher power consumption. The Netburst-based processors were not as efficient per clock or per watt compared to their P6 predecessors. Mobile Pentium 4 processors ran much hotter than Pentium III-M processors and its inefficiency affected not only the cooling system complexity, but also the all-important battery life. Realizing their new microarchitecture wasnt the best choice for the mobile space, the result was a modernized P6 design called the Pentium M, Design Overview Quad-pumped Front Side Bus. With the initial Banias core, Intel adopted the 400 MT/s FSB first used in Pentium 4, the Dothan core moved to the 533 MT/s FSB, following Pentium 4s evolution. Initially 1 MB in the Banias core, then 2 MB in the Dothan core, Dynamic cache activation by quadrant selector from sleep states. SSE2 Streaming SIMD Extensions 2 support, a 12- or 14-stage instruction pipeline that allows for higher clock speeds. Addition of global history, indirect prediction, and loop prediction to branch prediction table, micro-ops Fusion of certain sub-instructions mediated by decoding units. X86 commands can result in fewer RISC micro-operations and thus require fewer processor cycles to complete, the Pentium M was the most power efficient x86 processor for notebooks for several years, consuming a maximum of 27 watts at maximum load and 4-5 watts while idle. The processing efficiency gains brought about by its modernization allowed it to rival the Mobile Pentium 4 clocked over 1 GHz higher and equipped with more memory
6.
Multi-core processor
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A multi-core processor is a single computing component with two or more independent actual processing units, which are units that read and execute program instructions. The instructions are ordinary CPU instructions, but the multiple cores can run multiple instructions at the same time, manufacturers typically integrate the cores onto a single integrated circuit die, or onto multiple dies in a single chip package. A multi-core processor implements multiprocessing in a physical package. Designers may couple cores in a multi-core device tightly or loosely, for example, cores may or may not share caches, and they may implement message passing or shared-memory inter-core communication methods. Common network topologies to interconnect cores include bus, ring, two-dimensional mesh, homogeneous multi-core systems include only identical cores, heterogeneous multi-core systems have cores that are not identical. Just as with single-processor systems, cores in multi-core systems may implement architectures such as VLIW, superscalar, Multi-core processors are widely used across many application domains, including general-purpose, embedded, network, digital signal processing, and graphics. The improvement in performance gained by the use of a multi-core processor depends very much on the algorithms used. In particular, possible gains are limited by the fraction of the software that can run in parallel simultaneously on multiple cores, most applications, however, are not accelerated so much unless programmers invest a prohibitive amount of effort in re-factoring the whole problem. The parallelization of software is a significant ongoing topic of research, the terms multi-core and dual-core most commonly refer to some sort of central processing unit, but are sometimes also applied to digital signal processors and system on a chip. This article uses the terms multi-core and dual-core for CPUs manufactured on the integrated circuit. In contrast to systems, the term multi-CPU refers to multiple physically separate processing-units. The terms many-core and massively multi-core are sometimes used to describe multi-core architectures with a high number of cores. Some systems use many soft microprocessor cores placed on a single FPGA, each core can be considered a semiconductor intellectual property core as well as a CPU core. While manufacturing technology improves, reducing the size of individual gates and these physical limitations can cause significant heat dissipation and data synchronization problems. Various other methods are used to improve CPU performance, some instruction-level parallelism methods such as superscalar pipelining are suitable for many applications, but are inefficient for others that contain difficult-to-predict code. Many applications are better suited to thread-level parallelism methods, and multiple independent CPUs are commonly used to increase a systems overall TLP, a combination of increased available space and the demand for increased TLP led to the development of multi-core CPUs. Several business motives drive the development of multi-core architectures, for decades, it was possible to improve performance of a CPU by shrinking the area of the integrated circuit, which reduced the cost per device on the IC. Alternatively, for the circuit area, more transistors could be used in the design
7.
Socket 479
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Socket 479 is the CPU socket for the Intel Pentium M and Celeron M, mobile processors. Normally used in laptops, but has also used with Tualatin-M Pentium III processors. The official naming by Intel is µFCPGA and µPGA479M, even the Intels CPU specifications seem to be not clear enough on the distinction and instead use the package/socket designations PGA478 or PPGA478 for more than 1 of the above sockets. Perhaps adding yet more confusion, some of the PGA-based CPUs above are available in a BGA package which has all of the 479 contacts populated. For these CPU variants, the Intels CPU specifications use the designations BGA479, PBGA479 or H-PBGA479 and it should be however pointed out that these designations denote rather the CPU package itself and not the socket, which the BGA variants do not use at all. The non-BGA counterparts of these CPUs use any one of the above mentioned sockets, Socket 479 has 479 pin holes. Pentium M processors in PGA package have 479 pins that plug into this zero insertion force socket, only 478 pins are electrically connected. Although electrically and mechanically similar, Socket 478 has one pin less, for this reason manufacturers like Asus have made drop-in boards which allow use of Socket 479 processors. Chipsets which employ this socket for the Pentium M are the Intel 855GM/GME/PM, while the Intel 855GME chipset supports all Pentium M CPUs, the Intel 855GM chipset does not officially support 90 nm 2MB L2 cache models. The other difference is the 855GM chipset graphics core runs at 200 MHz while the 855GME runs at 250 MHz. In 2006, Intel released the successor to Socket 479 with a revised pinout for its Core processor, List of Intel microprocessors List of Intel Pentium M microprocessors List of Intel Celeron microprocessors
8.
Pentium III
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The Pentium III brand refers to Intels 32-bit x86 desktop and mobile microprocessors based on the sixth-generation P6 microarchitecture introduced on February 26,1999. The brands initial processors were very similar to the earlier Pentium II-branded microprocessors, the most notable differences were the addition of the SSE instruction set, and the introduction of a controversial serial number embedded in the chip during the manufacturing process. Similarly to the Pentium II it superseded, the Pentium III was also accompanied by the Celeron brand for lower-end versions, and the Xeon for high-end derivatives. The Pentium III was eventually superseded by the Pentium 4, but its Tualatin core also served as the basis for the Pentium M CPUs, the first Pentium III variant was the Katmai. It was a development of the Deschutes Pentium II. The Pentium III saw an increase of 2 million transistors over the Pentium II and it was first released at speeds of 450 and 500 MHz in February 1999. Two more versions were released,550 MHz on May 17,1999 and 600 MHz on August 2,1999, on September 27,1999 Intel released the 533B and 600B running at 533 &600 MHz respectively. The B suffix indicated that it featured a 133 MHz FSB, the Katmai contains 9.5 million transistors, not including the 512 Kbytes L2 cache, and has dimensions of 12.3 mm by 10.4 mm. It is fabricated in Intels P856.5 process, a 0.25 micrometre CMOS process with five levels of aluminum interconnect, the Katmai used the same slot-based design as the Pentium II but with the newer SECC2 cartridge that allowed direct CPU core contact with the heat sink. There have been some early models of the Pentium III with 450 and 500 MHz packaged in an older SECC cartridge intended for OEMs, a notable stepping for enthusiasts was SL35D. This version of Katmai was officially rated for 450 MHz, but often contained cache chips for the 600 MHz model and thus usually was capable of running at 600 MHz. The second version, codenamed Coppermine, was released on October 25,1999, running at 500,533,550,600,650,667,700, and 733 MHz. From December 1999 to May 2000, Intel released Pentium IIIs running at speeds of 750,800,850,866,900,933 and 1000 MHz, both 100 MHz FSB and 133 MHz FSB models were made. An E was appended to the name to indicate cores using the new 0.18 μm fabrication process. An additional B was later appended to designate 133 MHz FSB models, however, AMD were able to clock the Athlon higher, reaching speeds of 1.2 GHz before the launch of the Pentium 4. The Coppermine core was unable to reach the 1.13 GHz speed without various tweaks to the processors microcode, effective cooling, additional voltage. Intel only officially supported the processor on its own VC820 i820-based motherboard, in benchmarks that were stable, performance was shown to be sub-par, with the 1.13 GHz CPU equalling a 1.0 GHz model. Toms Hardware attributed this performance deficit to relaxed tuning of the CPU, Intel needed at least six months to resolve the problems using a new cD0 stepping and re-released 1.1 GHz and 1.13 GHz versions in 2001
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