1.
Power Architecture
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The governing body is Power. org, comprising over 40 companies and organizations. Power Architecture is a broad term including all products based on newer POWER, PowerPC, Power Architecture is a family name describing processor architecture, software, toolchain, community and end-user appliances and not a strict term describing specific products or technologies. There can be misunderstanding of the meaning of the terms, POWER, PowerPC, the following glossary gives brief descriptions of each term, along with links to articles with details. Power Architecture originated at IBM in the late 1980s when that company wanted a high-performance RISC architecture for their mid-range workstations, the result was the POWER architecture. Its first implementation featured in the RS/6000 computers introduced in 1990 and this was the 10-chip RIOS-1 processor, later called POWER1. The RISC Single Chip processor was developed from RIOS-1, in 1992 Apple, IBM and Motorola formed the AIM alliance to develop a mass-market version of the POWER processor. This resulted in the PowerPC architecture, a version of the POWER architecture. The first PowerPC implementation was the PowerPC601 of 1993, based heavily on RSC, it found its way into Apples Power Mac computers as well as into IBM RS/6000 systems. The differences between the POWER instruction set and PowerPC is outlined in Appendix E of the manual for PowerPC ISA v.2.02. IBM expanded their POWER architecture for their RS/6000 systems, which resulted in the eight-chip POWER2 processor in 1993 and in a version called P2SC, POWER2 Super Chip. In the early 1990s IBM sought to replace its CISC-based AS/400 minicomputers with a RISC architecture and this new architecture, developed under the code name Amazon, came to be referred to as the PowerPC-AS amongst engineers working on the project. PowerPC-AS was to be a server platform based on RSC. It all ended up with the 64-bit A10 and A30 processors introduced in 1995 and with the later RS64 line in 1997, the 602 and 620 never found widespread use, but the 603,604 and their successors became very popular in their respective fields. Motorola and IBM also made the Book E extension of PowerPC, used in embedded implementations, Motorolas PowerQUICC processors, the last effort of the AIM Alliance was the third generation PowerPC750 in 1997. Motorola and IBM went their ways in developing the PowerPC architecture after that. The PowerPC750 processors found widespread use in computer and embedded markets and IBM kept evolving the 750 family in the years to come. Motorola, however, chose to focus on the market with PowerPC SoC designs and the PowerPC7400. This processor incorporated AltiVec, a SIMD unit, the PowerPC7400 came in 1999 and was used by Apple in workstations and laptops and by various companies in the telecom market
2.
PowerPC e600
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The e600 is the continuation of the PowerPC 74xx design. The core is designed to work in multiprocessing and multi core designs, in 2004 Freescale renamed the PowerPC 74xx core e600 and changed focus from general CPUs to high end embedded SoC devices, and introduced a new naming scheme, MPC86xx. The 7448 was to be the last pure 74xx and it formed the base of the new e600 core, the product also features four on-chip Gigabit ethernet controllers with TCP/UDP offloading features. The dual core MPC8641D has support for multiprocessing, which enables two operating systems to run on the same device simultaneously, sharing resources but largely unaware of each other. The MPC8641 and MPC8641D are manufactured on a 90 nm SOI based process,8641 draws less than 16W at 1.33 GHz and 8641D less than 25W at 1.5 GHz. Freescales MPC8641D page Introduced in summer of 2008, the MPC8640 and MPC8640D are low power, clocked at 1-1.25 GHz they draw 14-21W power while being identical to their older brethren in other respects. Freescales MPC8640D page Introduced in 2007 the MPC8610 is a host processor with integrated graphics processor supporting 24-bit screens sizes up to 1280x1024 pixels and it is a single core CPU with 256 kB on die L2 cache. Manufactured on a 90 nm process, it reaches speeds from 667 to 1333 MHz, press release regarding MPC8610 This list is a complete list of known core e600 based designs. The pictures are illustrations and not to scale, power Architecture PowerPC Freescales e600 SoC Platform Products
3.
QorIQ
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QorIQ /ˈkɔːr. aɪ. kjuː/ is a brand of Power Architecture-based communications microprocessors from NXP Semiconductors. The platform keeps software compatibility with older PowerPC products such as the PowerQUICC platform, in 2012 Freescale announced ARM based QorIQ offerings beginning in 2013. The QorIQ brand and the P1, P2 and P4 product families were announced in June 2008, details of P3 and P5 products were announced in 2010. QorIQ P Series processors will be manufactured on a 45 nm fabrication process and was available in the end of 2008, QorIQ T Series is based on a 28 nm process and is pushing a very aggressive power envelope target, capping at 30 W. These are using the core with AltiVec and are expected to be shipping in 2013. QorIQ LS-1 and LS-2 families are ARM based processors using the Cortex A7 and they will be available in 2013 and will target low end wireless infrastructure applications. The QorIQ P Series processors are based on Power Architecture e500 or e5500 cores, the P10xx series, P2010 and P2020 are based on the e500v2 core, P204x, P30xx and P40xx on the e500mc core, and P50xx on the e5500 core. The dual and multi-core devices supports both symmetric and asymmetric multiprocessing, and can run operating systems in parallel. The P1 series is tailored for gateways, Ethernet switches, wireless LAN access points and it is the entry level platform, ranging from 400 to 800 MHz devices. It is designed to replace the PowerQUICC II Pro and PowerQUICC III platforms, the chips include among other integrated functionality, Gigabit Ethernet controllers, two USB2. The chip is packaged in 689-pin packages which are pin compatible with the P2 family processors, p1011 – Includes one 800 MHz e500 core,256 kB L2 cache, four SerDes lanes, three Gbit Ethernet controllers and a TDM engine for legacy phone applications. P1020 – includes two 800 MHz e500 cores,256 kB shared L2 cache, four SerDes lanes, three Gbit Ethernet controllers and a TDM engine, the P2 series is designed for a wide variety of applications in the networking, telecom, military and industrial markets. It will be available in high quality parts, with junction tolerances from -40 to 125 °C. It is the platform, with devices ranging from 800 MHz up to 1.2 GHz. It is designed to replace the PowerQUICC II Pro and PowerQUICC III platforms, the chips include, among other integrated functionality, a 512 kB L2 cache, a security engine, three Gigabit Ethernet controllers, a USB2. The chips are packaged in 689-pin packages which are pin compatible with the P1 family processors. P2010 – Includes one 1.2 GHz core P2020 – Includes two 1.2 GHz cores, with shared L2 cache The P3 series is a mid performance networking platform, designed for switching and routing. The P3 family offers a platform, with support for up to four Power Architecture e500mc cores at frequencies up to 1.5 GHz on the same chip
4.
IBM POWER Instruction Set Architecture
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POWER is a reduced instruction set computer instruction set architecture developed by IBM. The name is an acronym for Performance Optimization With Enhanced RISC, the ISA is used as base for high end microprocessors from IBM during the 1990s and were used in many of IBMs servers, minicomputers, workstations, and supercomputers. These processors are called POWER1 and POWER2, the POWER ISA was then abandoned. In 1974, IBM started a project with an objective of creating a large telephone-switching network with a potential capacity to deal with at least 300 calls per second. It was projected that 20,000 machine instructions would be required to each call while maintaining a real-time response. By 1975 the telephone switch project was canceled without a prototype, watson Research Center building #801, on the 801 project. To increase performance, Cheetah had separate branch, fixed-point, many changes were made to the 801 design to allow for multiple-execution-units. In February 1990, the first computers from IBM to incorporate the POWER instruction set were called the RISC System/6000 or RS/6000 and these RS/6000 computers were divided into two classes, workstations and servers, and hence introduced as the POWERstation and POWERserver. The RS/6000 CPU had 2 configurations, called the RIOS-1 and RIOS.9, a single-chip implementation of RIOS, RSC, was developed for lower-end RS/6000s, the first machines using RSC were released in 1992. IBM started the POWER2 processor effort as a successor to the POWER1 two years before the creation of the 1991 Apple/IBM/Motorola alliance in Austin, Texas, despite being impacted by diversion of resources to jump start the Apple/IBM/Motorola effort, the POWER2 took five years from start to system shipment. By adding a second fixed-point unit, a floating point unit, and other performance enhancements to the design. New instructions were added to the instruction set, Quad-word storage instructions. The quad-word load instruction moves two adjacent double-precision values into two adjacent floating-point registers, P2SC combined all of the separate POWER2 instruction cache, fixed point, floating point, storage control, and data cache chips onto one huge die. At the time of its introduction, P2SC was the largest and highest transistor count processor in the industry, P2SC was the processor used in the 1997 IBM Deep Blue chess playing supercomputer which beat chess grandmaster Garry Kasparov. With its twin sophisticated MAF floating point units and huge wide and low latency memory interfaces, P2SC was primarily targeted at engineering and scientific applications. P2SC was eventually succeeded by the POWER3, which included 64-bit, SMP capability, the POWER design is descended directly from the earlier 801 CPU, widely considered to be the first true RISC processor design. The 801 was used in a number of applications inside IBM hardware, at about the same time the PC/RT was being released, IBM started the America Project, to design the most powerful CPU on the market. They were interested primarily in fixing two problems in the 801 design, The 801 required all instructions to complete in one clock cycle, although the decoder was pipelined as a side effect of these single-cycle operations, they didnt use superscalar effects
5.
IBM POWER microprocessors
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IBM has a series of high performance microprocessors called POWER followed by a number designating generation, i. e. POWER1, POWER2, POWER3 and so forth up to the latest POWER9. These processors have used by IBM in their RS/6000, AS/400, pSeries, iSeries, System p, System i. They have also used in data storage devices by IBM and by other server manufacturers like Bull. The POWERn family of processors were developed in the late 1980s and are still in active development nearly 30 years later, in the beginning, they utilized the POWER instruction set architecture, but that evolved into PowerPC in later generations and then to Power Architecture. Today, only the naming scheme remains the same, modern POWER processors do not use the POWER ISA, in 1974 IBM started a project to build a telephone switching computer with, for the time, immense computational power. When the telephone switch project was cancelled IBM kept the design for the general purpose processor, many changes were made to the 801 design to allow for multiple execution units and the Cheetah processor had separate branch prediction, fixed-point, and floating-point execution units. By 1984 CMOS was chosen since it allowed an increase in the level of integration while improving transistor-logic performance. This was to become the first POWER processors using the first POWER ISA, in February 1990, the first computers from IBM to incorporate the POWER ISA were called the RISC System/6000 or RS/6000. These RS/6000 computers were divided into two classes, workstations and servers, and hence introduced as the POWERstation and POWERserver, the RS/6000 CPU had 2 configurations, called the RIOS-1 and RIOS.9. The POWER1 is the first microprocessor that used register renaming and out-of-order execution, a simplified and less powerful version of the 10 chip RIOS-1 was made in 1992 was developed for lower-end RS/6000s. It used only one chip and was called RISC Single Chip or RSC, RIOS-1 – the original 10-chip version RIOS. The POWER2 was a design, but IBM also made a single chip design of it. At the time of its introduction in 1996, the P2SC was the largest processor with the highest transistor count in the industry and was a leader in floating point operations. IBM joined the discussion and the three founded the AIM alliance to build the PowerPC ISA, heavily based on the POWER ISA, but with additions from both Apple and Motorola. It was to be a complete 32/64 bit RISC architecture, with a promise to range from low end embedded microcontrollers to the very high end supercomputer and server applications. After two years of development, the resulting PowerPC ISA was introduced in 1993 and it also added a 64-bit version of the ISA and support for SMP. The POWER3 began its life as PowerPC630, a successor of the commercially unsuccessful PowerPC620 and it used a combination of the POWER2 ISA and the 32/64-bit PowerPC ISA set with support for SMP and single-chip implementation. It was used to great extent in IBMs RS/6000 computers, while the second generation version, the POWER3 was the last processor to use a POWER instruction set, all subsequent models used some version of the PowerPC instruction set
6.
POWER1
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The POWER1 is a multi-chip CPU developed and fabricated by IBM that implemented the POWER instruction set architecture. The POWER1 was introduced in 1990, with the introduction of the IBM RS/6000 POWERserver servers and POWERstation workstations, the POWER1 received two upgrades, one in 1991, with the introduction of the POWER1+ and in 1992, with the introduction of POWER1++. These upgraded versions were clocked higher than the original POWER1, made possible by improved semiconductor processes, in September 1993, the POWER1 and its variants was succeeded by the POWER2, an evolution of the POWER1 microarchitecture. An indirect derivative of the POWER1 is the PowerPC601, a variant of the RSC intended for consumer applications. The POWER1 is notable as it represented a number firsts for IBM and it was IBMs first RISC processor intended for high-end applications, it was the first to implement the then new POWER instruction set architecture and it was IBMs first successful RISC processor. The POWER1 was also the origin for the highly successful families of POWER, PowerPC and Power Architecture processors that followed it, the open source GCC compiler removed support for POWER1 and POWER2 in the 4.5 release. The POWER1 is a 32-bit two-way superscalar CPU and it contains three major execution units, a fixed-point unit, a branch unit and a floating point unit. Although the POWER1 is a 32-bit CPU with a 32-bit physical address, the larger virtual address space was chosen because it was beneficial for the performance of applications, allowing each one to have a large 4 GB address range. The POWER1 is a big-endian CPU that uses a Harvard style cache hierarchy with separate instruction, the instruction cache, referred to as the I-cache by IBM, is 8 KB in size and is two-way set associative with a line size of 64 bytes. The I-cache is located on the ICU chip, the data cache, referred to as the D-cache by IBM, is 32 KB in size for RIOS.9 configurations and 64 KB in size for RIOS-1 configurations. The D-cache is four-way set associative with a size of 128 bytes. The D-cache employs a scheme, where data that is to be stored is written to the cache instead of the memory in order to reduce the number of writes destined for the memory. The store-back scheme is used to prevent the CPU from monopolizing access to the memory, as the POWER1 was the basis of the POWER2 and P2SC microprocessors, the lack of multiprocessing was passed on to these later POWER processors. Multiprocessing was not supported until the introduction of the POWER3 in 1998, the POWER1 is a multi-chip CPU built from separate chips that are connected to each other by buses. The POWER1 consists of a unit, a fixed-point unit, a floating point unit, a number of data-cache units, a storage-control unit. Due to its design, IBM was able to create two configurations by simply varying the number of DCUs, RIOS-1 and a RIOS.9. The RIOS-1 configuration has four DCUs, the amount, and was clocked at up to 40 MHz. The chips are mounted on the “CPU planar”, a circuit board
7.
POWER2
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The POWER2, originally named RIOS2, is a processor designed by IBM that implemented the POWER instruction set architecture. The POWER2 was the successor of the POWER1, debuting in September 1993 within IBMs RS/6000 systems, when introduced, the POWER2 was the fastest microprocessor, surpassing the Alpha 21064. When the Alpha 21064A was introduced in 1993, the POWER2 lost the lead, IBM claimed that the performance for a 62.5 MHz POWER2 was 73.3 SPECint92 and 134.6 SPECfp92. The open source GCC compiler removed support for POWER1 and POWER2 in the 4.5 release, the POWER2 was a multi-chip design consisting of six or eight semi-custom integrated circuits, depending on the amount of data cache. The eight-chip configuration contains a total of 23 million transistors and a die area of 1,215 mm2. The chips are manufactured by IBM in its 0.72 μm CMOS process, which features a 0.45 μm effective channel length, the chips are packaged in a ceramic multi-chip module that measures 64 mm by 64 mm. An improved version of the POWER2 optimized for processing was introduced in May 1994 as the POWER2+. Transaction processing workloads benefited from the addition of a L2 cache with capacities of 512 KB,1 MB and 2 MB and this cache was implemented off-package with industry-standard burst SRAMs. The cache was connected to the POWER2+ via a 64- or 128-bit bus, the cache was direct-mapped, had a 128-byte line size, and was write-through. The cache tags were contained on the control unit chip. The POWER2+ has a narrower 64- or 128-bit memory bus and a smaller 64 or 128 KB data cache, as there is less cache, the data cache unit chips are smaller as a result, and the revised storage control unit chip is also smaller. A goal for the configuration was to reduce cost. The P2SC, for POWER2 Super Chip, was released in October 1996 as the successor of the POWER2 and it was a single-chip implementation of the eight-chip POWER2, integrating 15 million transistors on a 335 mm2 die manufactured in IBMs 0.29 μm five-layer metal CMOS-6S process. The first version ran at 120 or 135 MHz, nearly twice as fast as the POWER2 at 71.5 MHz, with the memory, IBM claimed that the performance of this version was 5.5 SPECint95_base and 14.5 SPECfp95_base. A faster 160 MHz part fabricated in the 0.25 μm CMOS-6S2 process was announced at the Microprocessor Forum in October 1997, the P2SC was succeeded by the POWER3 as IBMs flagship microprocessor on the RS/6000 line in 1998. A notable use of the P2SC was the 30-node IBM Deep Blue supercomputer that beat world champion Garry Kasparov at chess in 1997, however, the computers chess-playing capabilities were due to its custom integrated circuits, rather than the P2SCs. IBM POWER Instruction Set Architecture IBM POWER microprocessors POWER1 POWER3 Barreh, golla, R. T. Arimilli, L. B. Jordan, P. J. POWER2 instruction cache unit, IBM Journal of Research and Development
8.
POWER3
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It was introduced on 5 October 1998, debuting in the RS/6000 43P Model 260, a high-end graphics workstation. The POWER3 was the successor of the P2SC derivative of the POWER2 and completed IBMs long-delayed transition from POWER to PowerPC, the POWER3 was used in IBM RS/6000 servers and workstations at 200 MHz. It competed with the Digital Equipment Corporation Alpha 21264 and the Hewlett-Packard PA-8500, the POWER3 was based on the PowerPC620, an earlier 64-bit PowerPC implementation that was late, under-performing and commercially unsuccessful. The POWER3 is a design that executed instructions out of order. It has a seven-stage integer pipeline, a minimal eight-stage load/store pipeline, the front end consists of two stages, fetch and decode. During the first stage, eight instructions were fetched from a 32 KB instruction cache, during the second stage, four instructions were taken from the instruction buffer, decoded, and issued to instruction queues. Restrictions on instruction issue are few, of the two integer instruction queues, only one can accept one instruction, the other can accept up to four, if the queues do not have enough unused entries, instructions cannot be issued. The front end has a pipeline, resulting in a small three-cycle branch misprediction penalty. In stage three, instructions in the queues that are ready for execution have their operands read from the register files. The general-purpose register file contains 48 registers, of which 32 are general-purpose registers and 16 are rename registers for register renaming, the floating-point register file contains 56 registers, of which 32 are floating-point registers and 24 rename registers. Compared to the PowerPC620, there were more rename registers, the instruction queues dispatch up to eight instructions to the execution units. Integer instructions are executed in three integer execution units, two of the units are identical and execute all integer instructions except for multiply and divide. All instructions executed by them have a one-cycle latency, the third unit executes multiply and divide instructions. These instructions are not pipelined and have multi-cycle latencies, 64-bit multiply has a nine-cycle latency and 64-bit divide has a 37-cycle latency. Floating-point instructions are executed in two floating-point units, the FPUs are capable of fused multiply–add, where multiplication and addition is performed simultaneously. Such instructions, along with individual add and multiply, have a four-cycle latency, divide and square-root instructions are executed in the same FPUs, but are assisted by specialized hardware. Single-precision divide and square-root instructions have a 14-cycle latency, whereas double-precision divide and square-root instructions have an 18-cycle, after execution is completed, the instructions are held in buffers before being committed and made visible to software. Execution finishes in five for integer instructions and stage eight for floating-point
9.
POWER4
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The POWER4 is a microprocessor developed by International Business Machines that implemented the 64-bit PowerPC and PowerPC AS instruction set architectures. Released in 2001, the POWER4 succeeded the POWER3 and RS64 microprocessors, the POWER4 was a multicore microprocessor, with two cores on a single die, the first non-embedded microprocessor to do so. POWER4 Chip was first commercially available multiprocessor chip, the original POWER4 had a clock speed of 1.1 and 1.3 GHz, while an enhanced version, the POWER4+, reached a clock speed of 1.9 GHz. The PowerPC970 is a derivative of the POWER4, the POWER4 has a unified L2 cache, divided into three equal parts. Each has its own independent L2 controller which can feed 32 bytes of data per cycle, the Core Interface Unit connects each L2 controller to either the data cache or instruction cache in either of the two processors. The Non-Cacheable Unit is responsible for handling instruction serializing functions and performing any noncacheable operations in the storage topology, there is an L3 cache controller, but the actual memory is off-chip. The GX bus controller controls I/O device communications, and there are two 4-byte wide GX buses, one incoming and the other outgoing. The Fabric Controller is the controller for the network of buses. Trace-and-Debug, used for First Failure Data Capture, is provided, there is also a Built In Self Test function and Performance Monitoring Unit. The POWER4 implements a superscalar microarchitecture through high-frequency speculative out-of-order execution using eight independent execution units and they are, two floating-point units, two load-store units, two fixed-point units, a branch unit, and a conditional-register unit. The POWER4+ was a version of the POWER4 that ran at up to 1.9 GHz. It contained 184 million transistors, measured 267 mm2, and was fabricated in a 0.13 µm SOI CMOS process with eight layers of copper interconnect, J. M. Tendler, J. S. Dodson, J. S. Fields, Jr. H. IBM Journal of Research and Development. J. D. Warnock, J. M. Keaty, J. Petrovick, J. G. Clabes, C. J. Kircher, B. L. Krauter, P. J. Restle, the circuit and physical design of the POWER4 microprocessor. IBM Journal of Research and Development
10.
POWER5
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The POWER5 is a microprocessor developed and fabricated by IBM. It is a version of the POWER4. The principal improvements are support for simultaneous multithreading and a memory controller. The POWER5 is a microprocessor, with each core supporting one physical thread. Technical details of the microprocessor were first presented at the 2003 Hot Chips conference, a more complete description was given at Microprocessor Forum 2003 on 14 October 2003. The POWER5 was not sold openly and was used exclusively by IBM, systems using the microprocessor were introduced in 2004. The POWER5 competed in the enterprise server market, mostly against the Intel Itanium 2 and to a lesser extent, the Sun Microsystems UltraSPARC IV. It was superseded in 2005 by an iteration, the POWER5+. The POWER5 is a development of the POWER4. The addition of two-way multithreading required the duplication of the stack, program counter, instruction buffer, group completion unit. Most resources, such as the files and execution units, are shared. The POWER5 implements simultaneous multithreading, where two threads are executed simultaneously, the POWER5 can disable SMT to optimize for the current workload. As many resources such as the files are shared by two threads, they are increased in capacity in many cases to compensate for the loss of performance. The number of integer and floating-point registers is increased to 120 each, the floating-point instruction cache is also increased in capacity to 24 entries from 20. The capacity of the L2 unified cache was increased to 1.875 MB, the unified L3 cache was brought on-package instead of located externally in separate chips. Its capacity was increased to 36 MB, like the POWER4, the cache is shared by the two cores. The cache is accessed via two unidirectional 128-bit buses operating at half the core frequency, the on-die memory controller supports up to 64 GB of DDR and DDR2 memory. It uses high-frequency serial buses to communicate with external buffers that interface the dual inline memory modules to the microprocessor, the POWER5 contains 276 million transistors and has an area of 389 mm2
11.
POWER8
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POWER8 is a family of superscalar symmetric multiprocessors based on the Power Architecture, announced in August 2013 at the Hot Chips conference. The designs are available for licensing under the OpenPOWER Foundation, which is the first time for availability of IBMs highest-end processors. Systems based on POWER8 became available from IBM in June 2014, Systems and POWER8 processor designs made by other OpenPOWER members was available in early 2015, but Tyan seems to be ready to ship earlier than that, in October 2014. The processor makes use of large amounts of on- and off-chip eDRAM caches. For most workloads, the chip is said to perform two to three times as fast as its predecessor, the POWER7. POWER8 comes in 4-, 6-, 8-, 10- and 12-core variants, the 12-core version consists of 4.2 billion transistors and is 650 mm2 large while the 6-core version is only 362 mm2 large. Where previous POWER processors use the GX++ bus for communication, POWER8 removes this from the design. The CAPI port is used to connect auxiliary specialized processors such as GPUs, ASICs, units attached to the CAPI bus can use the same memory address space as the CPU, thereby reducing the computing path length. On October 14th,2016, IBM announced the formation of OpenCAPI, initial members are Google, AMD, Xilinx, Micron and Mellanox. POWER8 also contains a so-called on-chip controller, which is a power and it has two general-purpose offload engines and 512 KB of embedded static RAM, together with the possibility to access the main memory directly, while running an open-source firmware. Also, the OCC can be programmed to overclock the POWER8 processor, or to lower its power consumption by reducing the operating frequency. The current Centaur chip is using DDR3 memory, but a future version can use DDR4 or some other memory technology without the need to modify the design of the POWER8 chip itself. Every Centaur is connected to the POWER8 by means of three high-speed links, each running at 9.6 GB/s, for a bandwidth of 28.8 GB/s. Centaur contains 16 MB of eDRAM which can be used as L4 cache by the processor, Centaur chips are mounted onto DRAM DIMM modules. The Centaur chips are fabricated with a similar to that of the POWER8. The POWER8 core has 64 KB L1 data cache contained in the unit and 32 KB L1 instruction cache contained in the instruction fetch unit. In a single cycle each core can fetch up to eight instructions, decode and dispatch up to eight instructions, issue and execute up to ten instructions and commit up to eight instructions. Each core is eight-way hardware multithreaded and can be dynamically and automatically partitioned to have either one, POWER8 also added support for hardware transactional memory
12.
POWER9
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POWER9 is a family of superscalar symmetric multiprocessors based on the Power Architecture announced in August 2016 at the Hot Chips conference. Systems using POWER9 are scheduled to be available in 2017, the SMT4- and SMT8-cores are quite similar, in that they consist of a number of so-called slices fed by common schedulers. A slice is a rudimentary 64-bit single threaded processing core with load store unit, integer unit, a super-slice is the combination of two slices. An SMT4-core consists of a 32 KB L1 cache, a 32 KB L1 data cache, an instruction fetch unit, an SMT8-core has two sets of L1 caches and, IFUs and ISUs to feed four super-slices. The result is that the 12-core and 24-core versions of POWER9 each consist of the amount of slices, i. e.96 each. A POWER9 core, whether SMT4 and SMT8, has a 12-stage pipeline and it will be the first to incorporate elements of the Power ISA v.3. On chip are co-processors for compression and cryptography, as well as a large low-latency eDRAM L3 cache, the Blueink facility running NVLink v.2 interconnects for close attachment of graphics co-processors from Nvidia and Open CAPI accelerators. General purpose PCIe v.4 connections for attaching regular ASICs, FPGAs and other peripherals as well as CAPI2.0, multiprocessor links to connect other POWER9 processors in on the same motherboard, or in other closely attached enclosures. These systems are slated to go online in 2017, IBM POWER microprocessors OpenPOWER Foundation POWER8 Power Architecture
13.
PowerPC
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PowerPC is a RISC instruction set architecture created by the 1991 Apple–IBM–Motorola alliance, known as AIM. PowerPC was the cornerstone of AIMs PReP and Common Hardware Reference Platform initiatives in the 1990s and it has since become niche in personal computers, but remain popular as embedded and high-performance processors. Its use in game consoles and embedded applications provided an array of uses. In addition, PowerPC CPUs are still used in AmigaOne and third party AmigaOS4 personal computers, the history of RISC began with IBMs 801 research project, on which John Cocke was the lead developer, where he developed the concepts of RISC in 1975–78. 801-based microprocessors were used in a number of IBM embedded products, the RT was a rapid design implementing the RISC architecture. The result was the POWER instruction set architecture, introduced with the RISC System/6000 in early 1990, the original POWER microprocessor, one of the first superscalar RISC implementations, was a high performance, multi-chip design. IBM soon realized that a microprocessor was needed in order to scale its RS/6000 line from lower-end to high-end machines. Work on a one-chip POWER microprocessor, designated the RSC began, in early 1991, IBM realized its design could potentially become a high-volume microprocessor used across the industry. IBM approached Apple with the goal of collaborating on the development of a family of single-chip microprocessors based on the POWER architecture and this three-way collaboration became known as AIM alliance, for Apple, IBM, Motorola. In 1991, the PowerPC was just one facet of an alliance among these three companies. The PowerPC chip was one of joint ventures involving the three, in their efforts to counter the growing Microsoft-Intel dominance of personal computing. For Motorola, POWER looked like an unbelievable deal and it allowed them to sell a widely tested and powerful RISC CPU for little design cash on their own part. It also maintained ties with an important customer, Apple, and seemed to offer the possibility of adding IBM too, at this point Motorola already had its own RISC design in the form of the 88000 which was doing poorly in the market. Motorola was doing well with their 68000 family and the majority of the funding was focused on this, the 88000 effort was somewhat starved for resources. However, the 88000 was already in production, Data General was shipping 88000 machines, the 88000 had also achieved a number of embedded design wins in telecom applications. The result of various requirements was the PowerPC specification. The differences between the earlier POWER instruction set and PowerPC is outlined in Appendix E of the manual for PowerPC ISA v.2.02, when the first PowerPC products reached the market, they were met with enthusiasm. In addition to Apple, both IBM and the Motorola Computer Group offered systems built around the processors, Microsoft released Windows NT3.51 for the architecture, which was used in Motorolas PowerPC servers, and Sun Microsystems offered a version of its Solaris OS
14.
PowerPC 600
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The PowerPC600 family was the first family of PowerPC processors built. They were designed at the Somerset facility in Austin, Texas, jointly funded and staffed by engineers from IBM, Somerset was opened in 1992 and its goal was to make the first PowerPC processor and then keep designing general purpose PowerPC processors for personal computers. The first incarnation became the PowerPC601 in 1993, and the second soon followed with the PowerPC603, PowerPC604. The PowerPC601 was the first generation of microprocessors to support the basic 32-bit PowerPC instruction set, the design effort started in earnest in mid-1991 and the first prototype chips were available in October 1992. The first 601 processors were introduced in an IBM RS/6000 workstation in October 1993, the 601 was the first advanced single-chip implementation of the POWER/PowerPC architecture designed on a crash schedule to establish PowerPC in the marketplace and cement the AIM alliance. In order to achieve an aggressive schedule while including substantially new function the design leveraged a number of key technologies. New PowerPC changes, leveraging the basic RSC structure was very beneficial to reducing the uncertainty in chip area/floorplanning and timing analysis/tuning, from start of design to tape-out of the first 601 prototype was just 12 months in order to push hard to establish PowerPC on the market early. The bus was renamed the 60x bus once implemented on the 601 and these Motorola joined over 120 IBM designers in creating the 601. Using the 88110 bus as the basis for the 60x bus helped schedules in a number of ways and this 60x bus later became a fairly long lived basic interface for the many variants of the 601,603,604, G3, G4 and Motorola/Freescale PowerQUICC processors. The chip was designed to suit a wide variety applications and had support for external L2 cache and it had four functional units, including a floating point unit, an integer unit, a branch unit and a sequencer unit. The processor also included a management unit. The integer pipeline was four stages long, the branch pipeline two stages long, the pipeline five stages long, and the floating-point pipeline six stages long. First launched in IBM systems in the fall of 1993, it was marketed by IBM as the PPC601 and it operated at speeds ranging from 50 to 80 MHz. It was fabricated using a 0.6 µm CMOS process with four levels of aluminum interconnect, the die was 121 mm² large and contained 2.8 million transistors. The 601 has a 32 kB unified L1 cache, a capacity that was considered large at the time for an on-chip cache, thanks partly to the large cache it was considered a high performance processor in its segment, outperforming the competing Intel Pentium. The PowerPC601 was used in the first Power Macintosh computers from Apple, IBM was the sole manufacturer of the 601 and 601+ microprocessors in its Burlington, Vermont and East Fishkill, New York production facilities. The 601 used the IBM CMOS-4s process and the 601+ used the IBM CMOS-5x process, an extremely small number of these 601 and 601+ processors were relabeled with Motorola logos and part numbers and distributed through Motorola. An updated version, the PowerPC 601v or PowerPC 601+, operating at 90 to 120 MHz was introduced in 1994 and it was fabricated in a newer 0.5 µm CMOS process with four levels of interconnect, resulting in a die measuring 74 mm²
15.
PowerPC 400
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The PowerPC400 family is a line of 32-bit embedded RISC processor cores built using Power Architecture technology. Applied Micro Circuits Corporation bought assets concerning the 400 family cores from IBM in April 2004 for $227 million, IBM continues evolving the cores while supplying design and foundry services around the cores. Several cores are available for licensing by OEMs from IBM. Introduced in 1994, the PowerPC403 was one of the first PowerPC processors and it was the first one targeted strictly to the embedded market. Compared to the other PowerPC processors of the era, it was at the low end, lacking a memory management unit or floating point unit. The core was offered for custom chips and in pre packaged versions, including versions with MMU, the PowerPC403 is used in, among other appliances, thin clients, set-top boxes, RAID-controllers, network switches and printers. The first TiVo used a 54 MHz PowerPC 403GCX, AMCC acquired the design of 403 from IBM in 2004, but have chosen not to market it, instead focusing on the 405 and 440 cores. While the 403 was popular, it was too high performance and too costly for some applications, so in 1996 IBM released a bare bones PowerPC core. It has an issue, three-stage pipeline, with no MMU or DMA. The design contained just 85,000 transistors in all and operated at up to 100 MHz, applications using the 401 core range from set-top boxes and telecom switches to printers and fax machines. The PowerPC405 was released in 1998 and was designed for price or performance sensitive low-end embedded system-on-a-chip designs. It has a pipeline, separate 16 KB instruction and data L1 caches, a CoreConnect bus. The 405 core adheres to the current Power ISA v.2.03 using the Book III-E specification, both AMCC and IBM are developing and marketing processors using 405 cores. IBM and Synopsys also offers a fully synthesizable core, IBM has announced plans to make the specifications of the PowerPC405 core freely available to the academic and research community. Up to two 405 cores are used in Xilinx Virtex-II Pro and Virtex-4 FPGAs, in 2004 Hifn bought IBMs PowerNP network processors that uses 405 cores. V-Dragon The Chinese company Culturecom uses a 405 core for its V-Dragon processor which powers Linux terminals, the V-Dragon processor includes the Multilingual Character Generation Engine that processes and generates Chinese characters directly in the CPU. APM801xx AppliedMicro has a series of system on a chip based on PowerPC405 core, under a new name. These are the most energy efficient Power Architecture products to date, made to support a wide range of applications from networking, to storage and media devices
16.
PowerPC 7xx
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The PowerPC 7xx is a family of third generation 32-bit PowerPC microprocessors designed and manufactured by IBM and Motorola. This family is called the PowerPC G3 by its well-known customer Apple Inc. which introduced it on November 10,1997, the term PowerPC G3 is often, and incorrectly, imagined to be a microprocessor when in fact a number of microprocessors from different vendors have been used. Such designations were applied to Macintosh computers such as the PowerBook G3, the low power requirements and small size made the processors ideal for laptops and the name lived out its last days at Apple in the iBook. The 7xx family is widely used in embedded devices like printers, routers, storage devices, spacecraft. The 7xx family had its shortcomings, namely lack of SMP support and SIMD capabilities, motorolas 74xx range of processors picked up where the 7xx left off. The PowerPC740 and 750 were introduced in late 1997 as a replacement for the PowerPC 603e. Enhancements included a faster 60x system bus, larger L1 caches, an integer unit, an enhanced floating point unit. The 750 had support for an optional 256,512 or 1024 KB external unified L2 cache, the cache controller and cache tags are on-die. The cache was accessed via a dedicated 64-bit bus, the 740 and 750 added dynamic branch prediction and a 64-entry branch target instruction cache. Dynamic branch prediction uses the recorded outcome of a branch stored in a 512-entry by 2-bit branch history table to predict its outcome, the BTIC caches the first two instructions at a branch target. The 740/750 models had 6.35 million transistors and was manufactured by IBM. The die measured 67 mm2 at 0.26 μm and it reached speeds of up to 366 MHz while consuming 7.3 W. In 1999, IBM fabricated versions in a 0.20 μm process with copper interconnects, which increased the frequency up to 500 MHz and decreased power consumption to 6 W, the 740 slightly outperformed the Pentium II while consuming far less power and with a smaller die. The off-die L2 cache of the 750 increased performance by approximately 30% in most situations, the design was so successful that it quickly surpassed the PowerPC 604e in integer performance, causing a planned 604 successor to be scrapped. The PowerPC740 is completely pin compatible with the older 603, allowing upgrades to the PowerBook 1400,2400, the 750 with its L2 cache bus required more pins and thus a different package, a 360-pin ball grid array. The PowerPC750 was used in computers from Apple, including the original iMac. RAD750 is a processor, based on the PowerPC750. It is intended for use in radiation environments such as experienced on board satellites
17.
PowerPC 970
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The PowerPC970, PowerPC 970FX, PowerPC 970GX, and PowerPC 970MP, are 64-bit Power Architecture processors from IBM introduced in 2002. When used in Apple Inc. machines, they were dubbed the PowerPC G5, the 970 family was created through a collaboration between IBM and Apple. The project went under the codename GP-UL or Giga Processor Ultra Light, when Apple introduced the Power Mac G5, they stated that this was a five-year collaborative effort, with multiple future generations, but it was short-lived. Apple only used three variants of the processor, iBM’s JS20/JS21 blade modules and some low-end workstations and System p servers are based on PowerPC970. It is also used in high end embedded systems like Mercury’s Momentum XSA-200. IBM is also licensing the PowerPC970 core for use in custom applications, the PowerPC970 is a single core derivative of the POWER4 and can process both 32-bit and 64-bit PowerPC instructions natively. It has a hardware unit and a three way branch prediction unit. Like the POWER4, the front-end is nine stages long, the PowerPC970 can fetch and decode up to eight instructions, dispatch up to five to reserve stations, issue up to eight to the execution units and retire up to five per cycle. The execution pipelines were lengthened compared to the POWER4 to achieve higher clock frequencies and it has eight execution units, two arithmetic logic units, two double precision floating-point units, two load/store units and two AltiVec units. One of the AltiVec units executes integer and floating-point instructions, the latter has three subunits for simple integer, complex integer and floating-point instructions. These units have pipelines of varying lengths,10 stages for simple integer, the processor has two unidirectional 32-bit double data rate buses to the system controller chip running at one quarter of the processor core speed. The buses also carry addresses and control signals in addition to data so only a percentage of the bandwidth can be realized. As the buses are unidirectional, each direction can realize only half the aggregate bandwidth, the PowerPC970 was announced by IBM in October 2002. It was released in Apple Computers Power Mac G5 in June 2003, IBM released its first PowerPC970 blade servers, the BladeCenter JS20, in November 2003. The PowerPC970 had 512 KB of full-speed L2 cache and clock speeds from 1.6 to 2.0 GHz, the front side bus ran at half the processors clock speed. The PowerPC 970FX used a 90 nm manufacturing process and has a power rating of 11 watts at 149 degrees Fahrenheit while clocked at 1 GHz. The PowerPC 970s pipeline was lengthened from 9 stages to 16 -21 stages for the PowerPC970 FX. It has 10 functional units -2 Fixed-Point Units,2 Load/Store Units,2 Floating Point Units,1 Branch Unit,1 SIMD ALU unit,1 SIMD Permute unit, and 1 Condition Register
18.
IBM RAD6000
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The RAD6000 radiation-hardened single board computer, based on the IBM RISC Single Chip CPU, was manufactured by IBM Federal Systems. RAD6000 is mainly known as the computer of numerous NASA spacecraft. The radiation-hardening of the original RSC1.1 million-transistor processor to make the RAD6000s CPU was done by IBM Federal Systems Division working with the Air Force Research Laboratory, in addition to the CPU itself, the RAD6000 has 128 MB of ECC RAM. A typical real-time operating system running on NASAs RAD6000 installations is VxWorks, the Flight boards in the above systems have switchable clock rates of 2.5,5,10, or 20 MHz. Reported to have a unit cost somewhere between US$200,000 and US$300,000, RAD6000 computers were released for sale in the commercial market in 1996. The RAD6000s successor is the RAD750 processor, based on IBMs PowerPC750
19.
RAD750
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The RAD750 is a radiation-hardened single board computer manufactured by BAE Systems Electronics, Intelligence & Support. The successor of the RAD6000, the RAD750 is for use in radiation environments experienced on board satellites. The RAD750 was released in 2001, with the first units launched into space in 2005, the CPU has 10.4 million transistors, nearly an order of magnitude more than the RAD6000. It is manufactured using either 250 or 150 nm photolithography and has a die area of 130 mm2 and it has a core clock of 110 to 200 MHz and can process at 266 MIPS or more. The CPU can include an extended L2 cache to improve performance, the CPU itself can withstand 200,000 to 1,000,000 rads, temperature ranges between –55 °C and 125 °C and requires 5 watts of power. The standard RAD750 single-board system can withstand 100,000 rads, the RAD750 system has a price that is comparable to the RAD6000 which is US$200,000 per board. However customer program requirements and quantities will greatly affect the unit costs. The RAD750 is based on the PowerPC750 and its packaging and logic functions are completely compatible with the PowerPC 7xx family. The term RAD750 is a trademark of BAE Systems Information. In 2010 it was reported there were over 150 RAD750s used in a variety of spacecraft. Notable examples, in order of date, include, Deep Impact comet chasing spacecraft
20.
Gekko (microprocessor)
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The project was announced in 1999 when IBM and Nintendo agreed to a one billion dollar contract for a CPU running at approximately 400 MHz. IBM chose to modify their existing PowerPC 750CXe processor to suit Nintendos needs, such as tight, the customization was to the bus architecture, DMA, compression and floating point unit which support a special set of SIMD instructions. The CPU made ground work for custom lighting and geometry effects, iBMs customization led to performance that exceeded Nintendos specifications. The SIMD is often found under the denomination paired singles.3 GB/s peak bandwidth On-chip Cache -64 kB 8-way associative L1 cache,256 KB on-die, 2-way associative L2 cache DMIPS -1125180 nm IBM six-layer, copper-wire process. 43 mm² die 1.8 V for logic and I/O.4.9 W dissipation 27×27 mm PBGA package with 256 contacts 6.35 million logic transistors and 18
21.
Broadway (microprocessor)
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Broadway is the codename of the 32-bit Central Processing Unit used in Nintendos Wii video game console. It was designed by IBM, and is currently being produced using a 65 nm SOI process, according to IBM, the processor consumes 20% less power than its predecessor, the 180 nm Gekko used in the Nintendo GameCube video game console. Broadway is being produced by IBM at their 300 mm semiconductor development and manufacturing facility in East Fishkill, the bond, assembly, and test operation for the Broadway module is performed at the IBM facility in Bromont, Quebec. Very few official details have been released to the public by Nintendo or IBM, unofficial reports claim it is derived from the 486 MHz Gekko architecture used in the GameCube and runs 50% faster at 729 MHz. The PowerPC 750CL, released in 2006, is a stock CPU offered by IBM and virtually identical to Broadway
22.
Espresso (microprocessor)
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Espresso is the codename of the 32-bit central processing unit used in Nintendos Wii U video game console. It was designed by IBM, and is currently being produced using a 45 nm Silicon on insulator process, the Espresso chip resides together with a GPU from AMD on a MCM manufactured by Renesas. It was revealed at E32011 in June 2011 and released in November 2012, IBM and Nintendo have revealed that the Espresso processor is a Power Architecture based microprocessor with three cores on a single chip to reduce power consumption and increase speed. The two chips were assembled to the complete MCM by Renesas in Japan, Espresso itself is manufactured by IBM in its 300 mm plant in East Fishkill, New York, using 45 nm SOI-technology and embedded DRAM for caches. While unverified by Nintendo, hackers, teardowns, and unofficial informants have since revealed more information about the Espresso, such as its name, size and speed. The microarchitecture seems to be similar to its predecessors the Broadway and Gekko, i. e. PowerPC750 based. Rumors that the Wii U CPU was derived from IBMs high end POWER7 server processor proved false, Espresso shares some technology with POWER7, such as eDRAM and Power Architecture, but those are superficial similarities. They have been obtained by reverse engineering by hacker Hector Martin, broadway-based core architecture Three cores at 1.243125 GHz Symmetric multiprocessing with MESI/MERSI support Each core can output up to 4 instructions per clock using superscalar parallelism
23.
PWRficient
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PWRficient is the name of a series of microprocessors designed by P. A. Semi where the PA6T-1682M was the one that became an actual product. PWRficient processors comply with the 64-bit Power Architecture, and are designed for high performance, the processors are highly modular and can be combined to multi-core system-on-a-chip designs, combining CPU, northbridge, and southbridge functionality on a single processor die. The PA6T was the first and only processor core from P. A, Semi, and it was offered in two distinct lines of products, 16xxM dual core processors and 13xxM/E single core processors. The PA6T lines differed in their L2 cache size, their memory controllers, their communication functionality, Semi had plans to offer parts with up to 16 cores. The PA6T core is the first Power Architecture core to be designed from scratch outside the AIM alliance in ten years, since Texas Instruments was one of the investors in P. A. Semi, it was suggested that their fabrication plants would have used to manufacture the PWRficient processors. PWRficient processors were initially shipped to customers in February 2007 and were released for worldwide sale in Q42007. Semi was bought by Apple Inc. in April 2008, six execution units including a double precision FPU and Altivec unit Hypervisor and virtualization support Maximum 7 W at 2 GHz 11 million transistors,10 mm² large @65 nm. CONEXIUM scalable cross-bar interconnect 1–8 SMP cores 1–2 L2 caches,512 KB –8 MB large, 1–41067 MHz DDR2 memory controllers. Mercury Computer Systems will use the 1682M processor in its signal, NEC will use the 1682M processor in its storage array systems. AmigaOne X1000 uses the 1682M processor as CPU, start-up plans new energy-efficient processor at Archive. is PA Semi attacks performance/Watt FPF2005, P. A. Semis PA6T-1682M System on a Chip – Real World Technologies Judicious Clocking Subdues Power-Architecture Cooling Needs – Electronic Design
24.
Cell (microprocessor)
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It was developed by Sony, Toshiba, and IBM, an alliance known as STI. Cell is shorthand for Cell Broadband Engine Architecture, commonly abbreviated CBEA in full or Cell BE in part, the first major commercial application of Cell was in Sonys PlayStation 3 game console. Mercury Computer Systems has a dual Cell server, a dual Cell blade configuration, a computer. Toshiba had announced plans to incorporate Cell in high definition television sets, for these reasons, Cell is widely regarded as a challenging environment for software development. IBM provides a Linux-based development platform to help developers program for Cell chips, the architecture will not be widely used unless it is adopted by the software development community. However, Cells strengths may make it useful for scientific computing regardless of its mainstream success, in mid-2000, Sony Computer Entertainment, Toshiba Corporation, and IBM formed an alliance known as STI to design and manufacture the processor. The STI Design Center opened in March 2001, the Cell was designed over a period of four years, using enhanced versions of the design tools for the POWER4 processor. Over 400 engineers from the three worked together in Austin, with critical support from eleven of IBMs design centers. During this period, IBM filed many patents pertaining to the Cell architecture, manufacturing process, Each Processing Element contained 8 APUs, which are now referred to as SPEs on the current Broadband Engine chip. This chip package was widely regarded to run at a speed of 4 GHz and with 32 APUs providing 32 gigaFLOPS each. This design was fabricated using a 90 nm SOI process, in March 2007, IBM announced that the 65 nm version of Cell BE is in production at its plant in East Fishkill, New York. Bandai Namco Entertainment used the processor for their 357 arcade board as well as the subsequent 369. In February 2008, IBM announced that it begin to fabricate Cell processors with the 45 nm process. In May 2008, IBM introduced the high-performance double-precision floating-point version of the Cell processor, the worlds three most energy efficient supercomputers, as represented by the Green500 list, are similarly based on the PowerXCell 8i. The 45 nm Cell processor was introduced in concert with Sonys PlayStation 3 Slim in August 2009, by November 2009, IBM had discontinued the development of a Cell processor with 32 APUs but was still developing other Cell products. On May 17,2005, Sony Computer Entertainment confirmed some specifications of the Cell processor that would be shipping in the then-forthcoming PlayStation 3 console and this Cell configuration has one PPE on the core, with eight physical SPEs in silicon. The target clock-frequency at introduction is 3.2 GHz, the introductory design is fabricated using a 90 nm SOI process, with initial volume production slated for IBMs facility in East Fishkill, New York. The relationship between cores and threads is a source of confusion
25.
Xenon (processor)
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Microsoft XCPU, codenamed Xenon, is a CPU used in the Xbox 360 game console, to be used with ATIs Xenos graphics chip. The processor was developed by Microsoft and IBM under the IBM chip program codenamed Waternoose, the development program was originally announced on 2003-11-03. The processor is based on IBM PowerPC instruction set architecture and it consists of three independent processor cores on a single die. These cores are slightly modified versions of the PPE in the Cell processor used on the PlayStation 3, each core has two symmetric hardware threads, for a total of six hardware threads available to games. Each individual core also includes 32 KiB of L1 instruction cache and 32 KiB of L1 data cache, the XCPU processors are manufactured at IBMs East Fishkill, New York fabrication plant and Chartered Semiconductor Manufacturing in Singapore. Chartered reduced the process in 2007 to 65 nm from 90 nm. The XCGPU follows the trend started with the integrated EE+GS in PlayStation 2 Slimline, combining CPU, GPU, memory controllers, XCGPU contains 372 million transistors and is manufactured by GlobalFoundries on a 45 nm process. Compared to the chipset in the Xbox 360 the combined power requirements are reduced by 60%
26.
OpenPOWER Foundation
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The OpenPOWER Foundation is a collaboration around Power Architecture products initiated by IBM and announced as the OpenPOWER Consortium on August 6,2013. The goal stated is to enable the server vendor ecosystem to build their own customized server, networking and storage hardware for data centers. Power. org is still the governing body around the Power Architecture instruction set, processors based on IBMs IP can now be fabricated on any foundry and mixed with other hardware products of the integrators choice. IBM is using the open to describe this project in three ways. They are licensing the microprocessor technology openly to its partners and they are sharing the blueprints to their hardware and software to their partners, so they can hire IBM or other companies to manufacture processors or other related chips. They will collaborate openly in a business model where participants share technologies. Advantages via open source such as the Linux operating system. IBM is looking to offer the POWER8 chip technology and other future iterations under the OpenPOWER initiative, partners are required to contribute intellectual property to the OpenPOWER Foundation to be able to gain high level status. The POWER8 processor architecture incorporates facilities to integrate it more easily into custom designs, the generic memory controllers are designed to evolve with future technologies, and the new CAPI expansion bus is built to integrate easily with external coprocessors like GPUs, ASICs and FPGAs. The CAPI technology has spawned an open technology group all of itself in October 2016, the OpenCAPI Consortium was founded by several OpenPOWER members together with Dell EMC, AMD and Hewlett Packard Enterprise. Nvidia is contributing their fast interconnect technology, NVLink, that will enable tight coupling of Nvidias Pascal based graphics processors into future POWER processors, the OpenPOWER initiative will include firmware, the KVM hypervisor and little endian Linux operating system. The foundation has a site on GitHub for the software they are releasing as open source, as of July 2014, they have released firmware to boot Linux. Canonical Ltd. has working firmware and general Linux support via their Ubuntu Server version 16.04 LTS, Google, Tyan, Nvidia and Mellanox are all founding members of the OpenPOWER Foundation. Nvidia is looking to merge their graphics cores and Mellanox to integrate their high performance interconnects with Power cores, Tyan is said to be working on servers using POWER8 and Google sees using POWER processors in its data centers as a future possibility. Altera announced support for OpenPOWER in November 2013 with their FPGA offerings, on February 12,2014, Samsung Electronics joined. As of March 2014, members also include Altera, Fusion-io, Hynix, Micron, Servergy, at the first annual OpenPOWER Summit 2015, the organization announced that there were 113 members, including Wistron, Cirrascale and PMC-Sierra. As of Fall 2016 the OpenPOWER foundation has over 250 members
27.
Reduced instruction set computer
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A computer based on this strategy is a reduced instruction set computer, also called RISC. The opposing architecture is called complex instruction set computing, although a number of systems from the 1960s and 70s have been identified as being forerunners of RISC, the modern version of the design dates to the 1980s. In particular, two projects at Stanford University and University of California, Berkeley are most associated with the popularization of this concept. Stanfords design would go on to be commercialized as the successful MIPS architecture, while Berkeleys RISC gave its name to the entire concept, another success from this era were IBMs efforts that eventually led to the Power Architecture. RISC families include DEC Alpha, AMD Am29000, ARC, ARM, Atmel AVR, Blackfin, Intel i860 and i960, MIPS, Motorola 88000, PA-RISC, Power, RISC-V, SuperH, and SPARC. In the 21st century, the use of ARM architecture processors in smart phones and tablet computers such as the iPad, a number of systems, going back to the 1960s, have been credited as the first RISC architecture, partly based on their use of load/store approach. The term RISC was coined by David Patterson of the Berkeley RISC project, michael J. Flynn views the first RISC system as the IBM801 design which began in 1975 by John Cocke, and completed in 1980. The 801 was eventually produced in a form as the ROMP in 1981. As the name implies, this CPU was designed for tasks, and was also used in the IBM RT-PC in 1986. But the 801 inspired several research projects, including new ones at IBM that would lead to the IBM POWER instruction set architecture. The most public RISC designs, however, were the results of university research programs run with funding from the DARPA VLSI Program, the VLSI Program, practically unknown today, led to a huge number of advances in chip design, fabrication, and even computer graphics. The Berkeley RISC project started in 1980 under the direction of David Patterson, Berkeley RISC was based on gaining performance through the use of pipelining and an aggressive use of a technique known as register windowing. In a traditional CPU, one has a number of registers. In a CPU with register windows, there are a number of registers, e. g.128. The Berkeley RISC project delivered the RISC-I processor in 1982, consisting of only 44,420 transistors RISC-I had only 32 instructions, and yet completely outperformed any other single-chip design. They followed this up with the 40,760 transistor,39 instruction RISC-II in 1983, which ran over three times as fast as RISC-I. The MIPS architecture grew out of a course by John L. Hennessy at Stanford University in 1981, resulted in a functioning system in 1983. The MIPS approach emphasized an aggressive clock cycle and the use of the pipeline, the MIPS system was followed by the MIPS-X and in 1984 Hennessy and his colleagues formed MIPS Computer Systems
28.
Blue Gene
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Blue Gene is an IBM project aimed at designing supercomputers that can reach operating speeds in the PFLOPS range, with low power consumption. The project created three generations of supercomputers, Blue Gene/L, Blue Gene/P, and Blue Gene/Q, Blue Gene systems have often led the TOP500 and Green500 rankings of the most powerful and most power efficient supercomputers, respectively. Blue Gene systems have consistently scored top positions in the Graph500 list. The project was awarded the 2009 National Medal of Technology and Innovation, as of 2015, IBM seems to have ended the development of the Blue Gene family though no public announcement has been made. IBMs continuing efforts of the scene seems to be concentrated around OpenPower, using accelerators such as FPGAs. The initial design for Blue Gene was based on a version of the Cyclops64 architecture. The initial research and development work was pursued at IBM T. J, watson Research Center and led by William R. Pulleyblank. DOE started funding the development of system and it became known as Blue Gene/L, development of the original Blue Gene system continued under the name Blue Gene/C and, later. In November 2004 a 16-rack system, with each rack holding 1,024 compute nodes, achieved first place in the TOP500 list and it thereby overtook NECs Earth Simulator, which had held the title of the fastest computer in the world since 2002. From 2004 through 2007 the Blue Gene/L installation at LLNL gradually expanded to 104 racks, the system was built in Rochester, MN IBM plant. While the LLNL installation was the largest Blue Gene/L installation, many smaller installations followed, in November 2006, there were 27 computers on the TOP500 list using the Blue Gene/L architecture. All these computers were listed as having an architecture of eServer Blue Gene Solution, for example, three racks of Blue Gene/L were housed at the San Diego Supercomputer Center. While the TOP500 measures performance on a single application, Linpack. This achievement won the 2005 Gordon Bell Prize, in June 2006, NNSA and IBM announced that Blue Gene/L achieved 207.3 TFLOPS on a quantum chemical application. At Supercomputing 2006, Blue Gene/L was awarded the prize in all HPC Challenge Classes of awards. In 2007, a team from the IBM Almaden Research Center, the name Blue Gene comes from that it was originally designed to do, help biologists understand the processes of protein folding and gene development. Blue is a moniker that IBM uses for many of its products. The original Blue Gene design was renamed Blue Gene/C and eventually Cyclops64, the L in Blue Gene/L comes from Light as that designs original name was Blue Light
29.
Apple Inc.
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Apple is an American multinational technology company headquartered in Cupertino, California that designs, develops, and sells consumer electronics, computer software, and online services. Apples consumer software includes the macOS and iOS operating systems, the media player, the Safari web browser. Its online services include the iTunes Store, the iOS App Store and Mac App Store, Apple Music, Apple was founded by Steve Jobs, Steve Wozniak, and Ronald Wayne in April 1976 to develop and sell personal computers. It was incorporated as Apple Computer, Inc. in January 1977, Apple joined the Dow Jones Industrial Average in March 2015. In November 2014, Apple became the first U. S. company to be valued at over US$700 billion in addition to being the largest publicly traded corporation in the world by market capitalization. The company employs 115,000 full-time employees as of July 2015 and it operates the online Apple Store and iTunes Store, the latter of which is the worlds largest music retailer. Consumers use more than one billion Apple products worldwide as of March 2016, Apples worldwide annual revenue totaled $233 billion for the fiscal year ending in September 2015. This revenue accounts for approximately 1. 25% of the total United States GDP.1 billion, the corporation receives significant criticism regarding the labor practices of its contractors and its environmental and business practices, including the origins of source materials. Apple was founded on April 1,1976, by Steve Jobs, Steve Wozniak, the Apple I kits were computers single-handedly designed and hand-built by Wozniak and first shown to the public at the Homebrew Computer Club. The Apple I was sold as a motherboard, which was less than what is now considered a personal computer. The Apple I went on sale in July 1976 and was market-priced at $666.66, Apple was incorporated January 3,1977, without Wayne, who sold his share of the company back to Jobs and Wozniak for $800. Multimillionaire Mike Markkula provided essential business expertise and funding of $250,000 during the incorporation of Apple, during the first five years of operations revenues grew exponentially, doubling about every four months. Between September 1977 and September 1980 yearly sales grew from $775,000 to $118m, the Apple II, also invented by Wozniak, was introduced on April 16,1977, at the first West Coast Computer Faire. It differed from its rivals, the TRS-80 and Commodore PET, because of its character cell-based color graphics. While early Apple II models used ordinary cassette tapes as storage devices, they were superseded by the introduction of a 5 1/4 inch floppy disk drive and interface called the Disk II. The Apple II was chosen to be the platform for the first killer app of the business world, VisiCalc. VisiCalc created a market for the Apple II and gave home users an additional reason to buy an Apple II. Before VisiCalc, Apple had been a distant third place competitor to Commodore, by the end of the 1970s, Apple had a staff of computer designers and a production line
30.
Microprocessor
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A microprocessor is a computer processor which incorporates the functions of a computers central processing unit on a single integrated circuit, or at most a few integrated circuits. Microprocessors contain both combinational logic and sequential digital logic, Microprocessors operate on numbers and symbols represented in the binary numeral system. The integration of a whole CPU onto a chip or on a few chips greatly reduced the cost of processing power. Integrated circuit processors are produced in numbers by highly automated processes resulting in a low per unit cost. Single-chip processors increase reliability as there are many electrical connections to fail. As microprocessor designs get better, the cost of manufacturing a chip generally stays the same, before microprocessors, small computers had been built using racks of circuit boards with many medium- and small-scale integrated circuits. Microprocessors combined this into one or a few large-scale ICs, the internal arrangement of a microprocessor varies depending on the age of the design and the intended purposes of the microprocessor. Advancing technology makes more complex and powerful chips feasible to manufacture, a minimal hypothetical microprocessor might only include an arithmetic logic unit and a control logic section. The ALU performs operations such as addition, subtraction, and operations such as AND or OR, each operation of the ALU sets one or more flags in a status register, which indicate the results of the last operation. The control logic retrieves instruction codes from memory and initiates the sequence of operations required for the ALU to carry out the instruction, a single operation code might affect many individual data paths, registers, and other elements of the processor. As integrated circuit technology advanced, it was feasible to manufacture more and more complex processors on a single chip, the size of data objects became larger, allowing more transistors on a chip allowed word sizes to increase from 4- and 8-bit words up to todays 64-bit words. Additional features were added to the architecture, more on-chip registers sped up programs. Floating-point arithmetic, for example, was not available on 8-bit microprocessors. Integration of the point unit first as a separate integrated circuit and then as part of the same microprocessor chip. Occasionally, physical limitations of integrated circuits made such practices as a bit slice approach necessary, instead of processing all of a long word on one integrated circuit, multiple circuits in parallel processed subsets of each data word. With the ability to put large numbers of transistors on one chip and this CPU cache has the advantage of faster access than off-chip memory, and increases the processing speed of the system for many applications. Processor clock frequency has increased more rapidly than external memory speed, except in the recent past, a microprocessor is a general purpose system. Several specialized processing devices have followed from the technology, A digital signal processor is specialized for signal processing, graphics processing units are processors designed primarily for realtime rendering of 3D images
