Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, in the Silicon Valley. It is the world's second largest and second highest valued semiconductor chip manufacturer based on revenue after being overtaken by Samsung, is the inventor of the x86 series of microprocessors, the processors found in most personal computers. Intel ranked No. 46 in the 2018 Fortune 500 list of the largest United States corporations by total revenue. Intel supplies processors for computer system manufacturers such as Apple, Lenovo, HP, Dell. Intel manufactures motherboard chipsets, network interface controllers and integrated circuits, flash memory, graphics chips, embedded processors and other devices related to communications and computing. Intel Corporation was founded on July 18, 1968, by semiconductor pioneers Robert Noyce and Gordon Moore, associated with the executive leadership and vision of Andrew Grove; the company's name was conceived as portmanteau of the words integrated and electronics, with co-founder Noyce having been a key inventor of the integrated circuit.
The fact that "intel" is the term for intelligence information made the name appropriate. Intel was an early developer of SRAM and DRAM memory chips, which represented the majority of its business until 1981. Although Intel created the world's first commercial microprocessor chip in 1971, it was not until the success of the personal computer that this became its primary business. During the 1990s, Intel invested in new microprocessor designs fostering the rapid growth of the computer industry. During this period Intel became the dominant supplier of microprocessors for PCs and was known for aggressive and anti-competitive tactics in defense of its market position against Advanced Micro Devices, as well as a struggle with Microsoft for control over the direction of the PC industry; the Open Source Technology Center at Intel hosts PowerTOP and LatencyTOP, supports other open-source projects such as Wayland, Mesa3D, Intel Array Building Blocks, Threading Building Blocks, Xen. Client Computing Group – 55% of 2016 revenues – produces hardware components used in desktop and notebook computers.
Data Center Group – 29% of 2016 revenues – produces hardware components used in server and storage platforms. Internet of Things Group – 5% of 2016 revenues – offers platforms designed for retail, industrial and home use. Non-Volatile Memory Solutions Group – 4% of 2016 revenues – manufactures NAND flash memory and 3D XPoint, branded as Optane, products used in solid-state drives. Intel Security Group – 4% of 2016 revenues – produces software security, antivirus software. Programmable Solutions Group – 3% of 2016 revenues – manufactures programmable semiconductors. In 2017, Dell accounted for about 16% of Intel's total revenues, Lenovo accounted for 13% of total revenues, HP Inc. accounted for 11% of total revenues. According to IDC, while Intel enjoyed the biggest market share in both the overall worldwide PC microprocessor market and the mobile PC microprocessor in the second quarter of 2011, the numbers decreased by 1.5% and 1.9% compared to the first quarter of 2011. In the 1980s, Intel was among the top ten sellers of semiconductors in the world.
In 1992, Intel became the biggest chip maker by revenue and has held the position since. Other top semiconductor companies include TSMC, Advanced Micro Devices, Texas Instruments, Toshiba and STMicroelectronics. Competitors in PC chipsets include Advanced Micro Devices, VIA Technologies, Silicon Integrated Systems, Nvidia. Intel's competitors in networking include NXP Semiconductors, Broadcom Limited, Marvell Technology Group and Applied Micro Circuits Corporation, competitors in flash memory include Spansion, Qimonda, Toshiba, STMicroelectronics, SK Hynix; the only major competitor in the x86 processor market is Advanced Micro Devices, with which Intel has had full cross-licensing agreements since 1976: each partner can use the other's patented technological innovations without charge after a certain time. However, the cross-licensing agreement is canceled in the event of takeover; some smaller competitors such as VIA Technologies produce low-power x86 processors for small factor computers and portable equipment.
However, the advent of such mobile computing devices, in particular, has in recent years led to a decline in PC sales. Since over 95% of the world's smartphones use processors designed by ARM Holdings, ARM has become a major competitor for Intel's processor market. ARM is planning to make inroads into the PC and server market. Intel has been involved in several disputes regarding violation of antitrust laws, which are noted below. Intel was founded in Mountain View, California, in 1968 by Gordon E. Moore, a chemist, Robert Noyce, a physicist and co-inventor of the integrated circuit. Arthur Rock helped. Moore and Noyce had left Fairchild Semiconductor to found Intel. Rock was not an employee; the total initial investment in Intel was $10,000 from Rock. Just 2 years Intel became a public company via an initial public offering, raising $6.8 million. Intel's third employee was Andy Grove, a chemical engineer, who ran the company through much of the 1980s and the high-growth 1990s. In dec
Instruction-level parallelism is a measure of how many of the instructions in a computer program can be executed simultaneously. There are two approaches to instruction level parallelism: Hardware SoftwareHardware level works upon dynamic parallelism, whereas the software level works on static parallelism. Dynamic parallelism means the processor decides at run time which instructions to execute in parallel, whereas static parallelism means the compiler decides which instructions to execute in parallel; the Pentium processor works on the dynamic sequence of parallel execution, but the Itanium processor works on the static level parallelism. Consider the following program: Operation 3 depends on the results of operations 1 and 2, so it cannot be calculated until both of them are completed. However, operations 1 and 2 do not depend on any other operation, so they can be calculated simultaneously. If we assume that each operation can be completed in one unit of time these three instructions can be completed in a total of two units of time, giving an ILP of 3/2.
A goal of compiler and processor designers is to identify and take advantage of as much ILP as possible. Ordinary programs are written under a sequential execution model where instructions execute one after the other and in the order specified by the programmer. ILP allows the compiler and the processor to overlap the execution of multiple instructions or to change the order in which instructions are executed. How much ILP exists in programs is application specific. In certain fields, such as graphics and scientific computing the amount can be large. However, workloads such as cryptography may exhibit much less parallelism. Micro-architectural techniques that are used to exploit ILP include: Instruction pipelining where the execution of multiple instructions can be overlapped. Superscalar execution, VLIW, the related explicitly parallel instruction computing concepts, in which multiple execution units are used to execute multiple instructions in parallel. Out-of-order execution where instructions execute in any order that does not violate data dependencies.
Note that this technique is independent of both pipelining and superscalar execution. Current implementations of out-of-order execution dynamically extract ILP from ordinary programs. An alternative is to extract this parallelism at compile time and somehow convey this information to the hardware. Due to the complexity of scaling the out-of-order execution technique, the industry has re-examined instruction sets which explicitly encode multiple independent operations per instruction. Register renaming which refers to a technique used to avoid unnecessary serialization of program operations imposed by the reuse of registers by those operations, used to enable out-of-order execution. Speculative execution which allows the execution of complete instructions or parts of instructions before being certain whether this execution should take place. A used form of speculative execution is control flow speculation where instructions past a control flow instruction are executed before the target of the control flow instruction is determined.
Several other forms of speculative execution have been proposed and are in use including speculative execution driven by value prediction, memory dependence prediction and cache latency prediction. Branch prediction, used to avoid stalling for control dependencies to be resolved. Branch prediction is used with speculative execution, it is known that the ILP is exploited by both the compiler and hardware support but the compiler provides inherent and implicit ILP in programs to hardware by compilation optimization. Some optimization techniques for extracting available ILP in programs would include scheduling, register allocation/renaming, memory access optimization. Dataflow architectures are another class of architectures where ILP is explicitly specified, for a recent example see the TRIPS architecture. In recent years, ILP techniques have been used to provide performance improvements in spite of the growing disparity between processor operating frequencies and memory access times. Presently, a cache miss.
While in principle it is possible to use ILP to tolerate such memory latencies, the associated resource and power dissipation costs are disproportionate. Moreover, the complexity and the latency of the underlying hardware structures results in reduced operating frequency further reducing any benefits. Hence, the aforementioned techniques prove inadequate to keep the CPU from stalling for the off-chip data. Instead, the industry is heading towards exploiting higher levels of parallelism that can be exploited through techniques such as multiprocessing and multithreading. Data dependency Memory-level parallelism Approaches to addressing the Memory Wall Wired magazine article that refers to the above paper https://www.scribd.com/doc/33700101/Instruction-Level-Parallelism#scribd http://www.hpl.hp.com/techreports/92/HPL-92-132.pdf
Central processing unit
A central processing unit called a central processor or main processor, is the electronic circuitry within a computer that carries out the instructions of a computer program by performing the basic arithmetic, logic and input/output operations specified by the instructions. The computer industry has used the term "central processing unit" at least since the early 1960s. Traditionally, the term "CPU" refers to a processor, more to its processing unit and control unit, distinguishing these core elements of a computer from external components such as main memory and I/O circuitry; the form and implementation of CPUs have changed over the course of their history, but their fundamental operation remains unchanged. Principal components of a CPU include the arithmetic logic unit that performs arithmetic and logic operations, processor registers that supply operands to the ALU and store the results of ALU operations and a control unit that orchestrates the fetching and execution of instructions by directing the coordinated operations of the ALU, registers and other components.
Most modern CPUs are microprocessors, meaning they are contained on a single integrated circuit chip. An IC that contains a CPU may contain memory, peripheral interfaces, other components of a computer; some computers employ a multi-core processor, a single chip containing two or more CPUs called "cores". Array processors or vector processors have multiple processors that operate in parallel, with no unit considered central. There exists the concept of virtual CPUs which are an abstraction of dynamical aggregated computational resources. Early computers such as the ENIAC had to be physically rewired to perform different tasks, which caused these machines to be called "fixed-program computers". Since the term "CPU" is defined as a device for software execution, the earliest devices that could rightly be called CPUs came with the advent of the stored-program computer; the idea of a stored-program computer had been present in the design of J. Presper Eckert and John William Mauchly's ENIAC, but was omitted so that it could be finished sooner.
On June 30, 1945, before ENIAC was made, mathematician John von Neumann distributed the paper entitled First Draft of a Report on the EDVAC. It was the outline of a stored-program computer that would be completed in August 1949. EDVAC was designed to perform a certain number of instructions of various types; the programs written for EDVAC were to be stored in high-speed computer memory rather than specified by the physical wiring of the computer. This overcame a severe limitation of ENIAC, the considerable time and effort required to reconfigure the computer to perform a new task. With von Neumann's design, the program that EDVAC ran could be changed by changing the contents of the memory. EDVAC, was not the first stored-program computer. Early CPUs were custom designs used as part of a sometimes distinctive computer. However, this method of designing custom CPUs for a particular application has given way to the development of multi-purpose processors produced in large quantities; this standardization began in the era of discrete transistor mainframes and minicomputers and has accelerated with the popularization of the integrated circuit.
The IC has allowed complex CPUs to be designed and manufactured to tolerances on the order of nanometers. Both the miniaturization and standardization of CPUs have increased the presence of digital devices in modern life far beyond the limited application of dedicated computing machines. Modern microprocessors appear in electronic devices ranging from automobiles to cellphones, sometimes in toys. While von Neumann is most credited with the design of the stored-program computer because of his design of EDVAC, the design became known as the von Neumann architecture, others before him, such as Konrad Zuse, had suggested and implemented similar ideas; the so-called Harvard architecture of the Harvard Mark I, completed before EDVAC used a stored-program design using punched paper tape rather than electronic memory. The key difference between the von Neumann and Harvard architectures is that the latter separates the storage and treatment of CPU instructions and data, while the former uses the same memory space for both.
Most modern CPUs are von Neumann in design, but CPUs with the Harvard architecture are seen as well in embedded applications. Relays and vacuum tubes were used as switching elements; the overall speed of a system is dependent on the speed of the switches. Tube computers like EDVAC tended to average eight hours between failures, whereas relay computers like the Harvard Mark I failed rarely. In the end, tube-based CPUs became dominant because the significant speed advantages afforded outweighed the reliability problems. Most of these early synchronous CPUs ran at low clock rates compared to modern microelectronic designs. Clock signal frequencies ranging from 100 kHz to 4 MHz were common at this time, limited by the speed of the switching de
John L. Hennessy
John Leroy Hennessy is an American computer scientist, academician and Chair of Alphabet Inc. Hennessy is one of the founders of MIPS Computer Systems Inc. as well as Atheros and served as the tenth President of Stanford University. Hennessy announced that he would step down in the summer of 2016, he was succeeded as President by Marc Tessier-Lavigne. Marc Andreessen called him "the godfather of Silicon Valley."Along with David Patterson, Hennessy won the 2017 Turing Award for their work in developing the reduced instruction set computer architecture, now used in 99% of new computer chips. Hennessy was raised in New York, as one of six children, his father was an aerospace engineer and his mother was a teacher before raising her children. He earned his bachelor's degree in electrical engineering from Villanova University, his master's degree and Ph. D. in computer science from Stony Brook University. He is married to Andrea Berti. Hennessy became a Stanford faculty member in 1977. In 1981, he began the MIPS project to investigate RISC processors, in 1984, he used his sabbatical year to found MIPS Computer Systems Inc. to commercialize the technology developed by his research.
In 1987, he became the Willard and Inez Kerr Bell Endowed Professor of Electrical Engineering and Computer Science. Hennessy served as director of Stanford's Computer System Laboratory, a research center run by Stanford's Electrical Engineering and Computer Science departments, he was chair of the Department of Computer Dean of the School of Engineering. In 1999, Stanford President Gerhard Casper appointed Hennessy to succeed Condoleezza Rice as Provost of Stanford University; when Casper stepped down to focus on teaching in 2000, the Stanford Board of Trustees named Hennessy to succeed Casper as president. In 2008, Hennessy earned a salary of $1,091,589, the 23rd highest among all American university presidents. In 1997, he was inducted as a Fellow of the Association for Computing Machinery. Hennessy is a board member of Google, Cisco Systems, Atheros Communications, the Gordon and Betty Moore Foundation. In 2007, he was made a Fellow of the Computer History Museum "for fundamental contributions to engineering education, advances in computer architecture, the integration of leading-edge research with education".
On October 14, 2010, Hennessy was presented a khata by the 14th Dalai Lama before His Holiness addressed Maples Pavilion. In December 2010, Hennessy coauthored an editorial with Harvard University President Drew Gilpin Faust urging the passage of the DREAM Act. In 2012, Hennessy was awarded the IEEE Medal of Honor; the IEEE awarded Hennessy their highest recognition "for pioneering the RISC processor architecture and for leadership in computer engineering and higher education". In 2012, Hennessy received an honorary doctor of mathematics degree from the University of Waterloo, in celebration of his profound contributions to modern computer architecture and to post-secondary education. In 2013, Hennessy became a judge for the inaugural Queen Elizabeth Prize for Engineering, he has remained on the judging panel for the subsequent awards in 2015 and 2017. In June 2015, Hennessy announced that he would step down as Stanford president in summer 2016. In 2016, Hennessy co-founded the Knight-Hennessy Scholars program.
The program has a $750 million endowment to fund graduate students at Stanford for up to three years. The inaugural class of 51 scholars from 21 countries arrived at Stanford in the fall of 2018. In 2017, he was elected to International Fellow of the Royal Academy of Engineering, UK. In February 2018, Hennessy was announced as the new Chairman of Alphabet Inc. Google's parent company. On March 21, 2018, together with David Patterson, he was awarded the 2017 ACM A. M. Turing Award for the development of the reduced instruction set computer architecture in the 1980s.. The award praised them for "pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry". Hennessy has a history of strong involvement in college-level computer education, he co-authored, with David A. Patterson, two well-known books on computer architecture, Computer Organization and Design: the Hardware/Software Interface and Computer Architecture: A Quantitative Approach, which introduced the DLX RISC architecture.
They have been used as textbooks for graduate and undergraduate courses since 1990. Hennessy contributed to updating Donald Knuth's MIX processor to the MMIX. Both are model computers used in The Art of Computer Programming. MMIX is Knuth's DLX equivalent. In 2004, he was awarded the Association for Computing Machinery SIGARCH ISCA Influential Paper Award for his 1989 co-authored paper on high performing cache hierarchies, he received the award again in 2009 for his 1994 co-authored paper on the Stanford FLASH multiprocessor. Computer Architecture: A Quantitative Approach Patterson, David A.. Computer Organization and Design: The Hardware/Software Interface. Morgan Kaufmann. ISBN 978-0-12-370606-5. Gharachorloo, Kourosh. "Memory consistency and event ordering in scalable shared-memory multiprocessors". Proceedings of the 17th annual international symposium on Computer Architecture. International Symposium on Computer Architecture. Pp. 15–26. Lenoski, Daniel. "The directory-b
A microprocessor is a computer processor that incorporates the functions of a central processing unit on a single integrated circuit, or at most a few integrated circuits. The microprocessor is a multipurpose, clock driven, register based, digital integrated circuit that accepts binary data as input, processes it according to instructions stored in its memory, provides results as output. Microprocessors contain sequential digital logic. Microprocessors operate on symbols represented in the binary number system; the integration of a whole CPU onto a single or a few integrated circuits reduced the cost of processing power. Integrated circuit processors are produced in large numbers by automated processes, resulting in a low unit price. Single-chip processors increase reliability because there are many fewer electrical connections that could fail; as microprocessor designs improve, the cost of manufacturing a chip stays the same according to Rock's law. Before microprocessors, small computers had been built using racks of circuit boards with many medium- and small-scale integrated circuits.
Microprocessors combined this into a few large-scale ICs. Continued increases in microprocessor capacity have since rendered other forms of computers completely obsolete, with one or more microprocessors used in everything from the smallest embedded systems and handheld devices to the largest mainframes and supercomputers; the complexity of an integrated circuit is bounded by physical limitations on the number of transistors that can be put onto one chip, the number of package terminations that can connect the processor to other parts of the system, the number of interconnections it is possible to make on the chip, the heat that the chip can dissipate. Advancing technology makes more powerful chips feasible to manufacture. A minimal hypothetical microprocessor might include only an arithmetic logic unit, a control logic section; the ALU performs addition and operations such as AND or OR. Each operation of the ALU sets one or more flags in a status register, which indicate the results of the last operation.
The control logic retrieves instruction codes from memory and initiates the sequence of operations required for the ALU to carry out the instruction. A single operation code might affect many individual data paths and other elements of the processor; as integrated circuit technology advanced, it was feasible to manufacture more and more complex processors on a single chip. The size of data objects became larger. Additional features were added to the processor architecture. Floating-point arithmetic, for example, was not available on 8-bit microprocessors, but had to be carried out in software. Integration of the floating point unit first as a separate integrated circuit and as part of the same microprocessor chip sped up floating point calculations. Physical limitations of integrated circuits made such practices as a bit slice approach necessary. Instead of processing all of a long word on one integrated circuit, multiple circuits in parallel processed subsets of each data word. While this required extra logic to handle, for example and overflow within each slice, the result was a system that could handle, for example, 32-bit words using integrated circuits with a capacity for only four bits each.
The ability to put large numbers of transistors on one chip makes it feasible to integrate memory on the same die as the processor. This CPU cache has the advantage of faster access than off-chip memory and increases the processing speed of the system for many applications. Processor clock frequency has increased more than external memory speed, so cache memory is necessary if the processor is not delayed by slower external memory. A microprocessor is a general-purpose entity. Several specialized processing devices have followed: A digital signal processor is specialized for signal processing. Graphics processing units are processors designed for realtime rendering of images. Other specialized units exist for video machine vision. Microcontrollers integrate a microprocessor with peripheral devices in embedded systems. Systems on chip integrate one or more microprocessor or microcontroller cores. Microprocessors can be selected for differing applications based on their word size, a measure of their complexity.
Longer word sizes allow each clock cycle of a processor to carry out more computation, but correspond to physically larger integrated circuit dies with higher standby and operating power consumption. 4, 8 or 12 bit processors are integrated into microcontrollers operating embedded systems. Where a system is expected to handle larger volumes of data or require a more flexible user interface, 16, 32 or 64 bit processors are used. An 8- or 16-bit processor may be selected over a 32-bit processor for system on a chip or microcontroller applications that require low-power electronics, or are part of a mixed-signal integrated circuit with noise-sensitive on-chip analog electronics such as high-resolution analog to digital converters, or both. Running 32-bit arithmetic on an 8-bit chip could end up using more power, as the chip must execute software with multiple instructions. Thousands of items that were traditionally not computer-related inc
Lynn Ann Conway is an American computer scientist, electrical engineer and transgender activist. Conway is notable for a number of pioneering achievements, including the Mead & Conway revolution in VLSI design, which incubated an emerging electronic design automation industry, she worked at IBM in the 1960s and is credited with the invention of generalized dynamic instruction handling, a key advance used in out-of-order execution, used by most modern computer processors to improve performance. Conway grew up in New York. Conway was experienced gender dysphoria as a child, she did well in math and science in high school. Conway entered MIT in 1955, earning high grades but leaving in despair after an attempted gender transition in 1957–58 failed due to the medical climate at the time. After working as an electronics technician for several years, Conway resumed education at Columbia University's School of Engineering and Applied Science, earning B. S. and M. S. E. E. Degrees in 1962 and 1963. Conway was recruited by IBM Research in Yorktown Heights, New York in 1964, was soon selected to join the architecture team designing an advanced supercomputer, working alongside John Cocke, Herbert Schorr, Ed Sussenguth, Fran Allen and other IBM researchers on the Advanced Computing Systems project, inventing multiple-issue out-of-order dynamic instruction scheduling while working there.
The Computer History Museum has stated that "the ACS machines appears to have been the first superscalar design, a computer architectural paradigm exploited in modern high-performance microprocessors." After learning of the pioneering research of Harry Benjamin in treating transsexuals and realising that genital affirmation surgery was now possible, Conway sought his help and became his patient. After suffering from severe depression from gender dysphoria, Conway contacted Benjamin, who agreed to providing counseling and prescribe hormones. Under Benjamin's care, Conway began her gender transition. While struggling with life in a male role, Conway had two children. Under the legal constraints in place, after transitioning she was denied access to their children. Although she had hoped to be allowed to transition on the job, IBM fired Conway in 1968 after she revealed her intention to transition to a female gender role. Upon completing her transition in 1968, Conway took a new name and identity, restarted her career in what she called "stealth-mode" as a contract programmer at Computer Applications, Inc.
She went on to work at Memorex during 1969 -- 1972 as a digital system computer architect. Conway joined Xerox PARC in 1973. Collaborating with Carver Mead of Caltech on VLSI design methodology, she co-authored Introduction to VLSI Systems, a groundbreaking work that would soon become a standard textbook in chip design, used in over 100 universities by 1983; the book and early courses were the beginning of the Conway revolution in VLSI system design. In 1978, Conway served as visiting associate professor of EECS at MIT, teaching a now famous VLSI design course based on a draft of the Mead–Conway text; the course validated the new design methods and textbook, established the syllabus and instructor's guidebook used in courses all around the world. Among Conway's contributions were invention of dimensionless, scalable design rules that simplified chip design and design tools, invention of a new form of internet-based infrastructure for rapid-prototyping and short-run fabrication of large numbers of chip designs.
The new infrastructure was institutionalized as the MOSIS system in 1981. Since MOSIS has fabricated more than 50,000 circuit designs for commercial firms, government agencies, research and educational institutions around the world. Prominent VLSI researcher Charles Seitz commented that "MOSIS represented the first period since the pioneering work of Eckert and Mauchley on the ENIAC in the late 1940s that universities and small companies had access to state-of-the-art digital technology."The research methods used to develop the Mead–Conway VLSI design methodology and the MOSIS prototype are documented in a 1981 Xerox report and the Euromicro Journal. The impact of the Mead–Conway work is described and time-lined in a number of historical overviews of computing. Conway and her colleagues have compiled an online archive of original papers that documents much of that work. In the early 1980s, Conway left Xerox to join DARPA, where she was a key architect of the Defense Department's Strategic Computing Initiative, a research program studying high-performance computing, autonomous systems technology, intelligent weapons technology.
In a USA Today article about Conway's joining DARPA, Mark Stefik, a Xerox scientist who worked with her, said "Lynn would like to live five lives in the course of one life" and that she's "charismatic and energetic". Douglas Fairbairn, a former Xerox associate, said "She figures out a way so that everybody wins."As sociologist Thomas Streeter discusses in The Net Effect: "By taking this job, Conway was demonstrating that she was no antiwar liberal.". But Conway carried a sense of computers as tools for horizontal communications that she had absorbed at PARC right into DARPA - at one of the hottest moments of the cold war." Conway joined the University of Michigan in 1985 as professor of electrical engineering and computer science, associate dean of engineering