The SiS 630 and SiS 730 are a family of integrated chipsets for Intel and AMD respectively. At the time of release they were unique in that they not only provided VGA, Audio, LAN, IDE and USB functionality on board, but were in a single-chip solution. At the time of release most chipsets were composed of physically separate north-bridge and south-bridge chips. Only have single-chip solutions become popular in the mainstream, with chipsets such as the nVidia nForce4. VGA Core Hardware Acceleration for DVD Playback. Ultra-AGP Architecture. DirectX 7.0 Compliant Graphics Engine. Resolution Up to 1920x1200 8bpp/16bpp 60 Hz NI. Optional Extended Graphics Memory On board for 128-bit Memory Accessing. Supports VESA DDC1, DDC2B & DDC 3.0. Driver Support for OS/2, Windows 95/98/ME, Windows NT 4.0, Windows 2000/XP. Supports SiS 301 Video Bridge Interface for Dual Display. NTSC/PAL TV or Secondary CRT TFT Digital LCD Monitor; the video core in the SiS 630/730 is based on the 128-bit SiS 305. The VGA core is capable of using either its own dedicated local memory or taking a chunk out of system memory.
In the majority of systems it is configured to use system memory since to get local memory support it was necessary to use a special card which fitted into the AGP slot, impossible in laptops, for desktop systems didn't make any sense once cheap AGP graphics cards became available offering superior performance. The onboard adapter competed well against the Intel i810 on Intel platforms and the VIA Twister on AMD both in terms of features and performance. Unlike the Intel i810, the SiS 630 renders 3D in 32-bit colour. There was support for full hardware decoding of MPEG2 which gave CPU usage of around 5-10% when watching DVDs with suitable software. Access to the acceleration is provided via DXVA under Windows 2000/XP. Another interesting feature is that the SiS 30x core supports two independent overlay surfaces, one for each output; this means that it is possible to view videos on both the primary monitor and on a TV-Out or secondary monitor output. Most other graphics cards only have one overlay surface or in some cases will clone the same overlay.
The memory bandwidth is shared between the rest of the system. Therefore, the system performance is dependent on the resolution and colour depth, in use. Whilst this would give comparatively poor scores in pure memory throughput benchmarks the real-world performance in office applications was good with systems based around the chipset walking away with "best buy" awards; as of 2003 it seems that SiS have chosen to abandon the SiS 630/730 with no newer drivers being offered and the last two sets being unusable on a large number of systems. Audio 64-voice Polyphony'Wavetable' sample-based Synthesizer. DirectSound 3D Accelerator for IID, IAD and Doppler Effects. Full-duplex, Independent Sample Rate Converter for Audio Recording and Playback. Supports 2/4/6 Speakers Output with Optional VirtualFX, VirtualAC3. AC'97 V2.1 Interface for External Audio Codec. SoundBlaster Pro/16 Compliant. Full Duplex VirtualPhone Speaker Phone with Modem Capable AC'97. V.90 Software Modem Compliant. Driver Support for Windows 95/98/ME, NT 4.0, Windows 2000/XP.
Unlike the SiS 735 chipset which used the host-processed SiS 7012, the SiS 630/730 featured the hardware accelerated SiS 7018 core which itself is a design licensed from Trident, sold as the Trident 4DWave. The Windows 95 VxD drivers take advantage of the hardware acceleration, there is SoundBlaster 16 emulation for MS-DOS based games. SiS chose to drop all of the hardware features from Windows 2000 onwards, treating it as a simpler AC97 host processed solution, as the SiS 7012. At the time of writing there is still no support for the hardware DirectSound, mixing or MIDI features that this chip provides in the WDM driver. 10/100 Fast Ethernet IEEE802.3/IEEE802.3u Compatible, 10BASE-T/100BASE-TX Standards Support. Supports On-Now, Wake-On-LAN, PCI Power Management 1.1. Driver Support for Windows 95/98/ME, NT 4.0, Windows 2000/XP, OS/2, Netware, ODI, SCO Unix, Netware & Linux. Onboard Ethernet functionality is provided by an SiS 900 compatible controller providing both 10 Mbit/s and 100 Mbit/s with auto-sensing.
USB The SiS 630/730 provides two USB 1.1 controllers called the SiS 7001, theoretically allowing 2 12 Mbit/s shared amongst up to 6 physical USB ports. On some boards or notebook systems only one of the controllers with the other one going unused. IDE The IDE controller on the SiS 630/730 provides support for up to UDMA/100 depending on the specific variant; the IDE controller connects to the "north-bridge" via a dedicated 133 MB/s link, separate from the second 133 MB/s link between the north bridge and other PCI devices. This is beneficial in two ways. Other Hardware Features In addition to the features listed above, the SiS 630/730 has support for legacy ports including SPP/ECP/EPP parallel port, 2 serial ports and F
Socket 478 is a 478-contact CPU socket used for Intel's Pentium 4 and Celeron series CPUs. Socket 478 was launched with the Northwood core to compete with AMD's 462-pin Socket A and their Athlon XP processors. Socket 478 was intended to be the replacement for Socket 423, a Willamette-based processor socket, on the market for only a short time. Socket 478 was phased out with the launch of LGA 775 in 2004. Socket 478 was used for Celeron processors, it supported the first Prescott Pentium 4 processors and all Willamette Celerons, along with several of the Willamette-series Pentium 4s. Socket 478 supported the newer Prescott-based Celeron D processors, early Pentium 4 Extreme Edition processors with 2 MiB of L3 CPU cache. Celeron D processors were available for Socket 478 and were the last CPUs made for the socket. While the Intel mobile CPUs are available in 478-pin packages, they in fact only operate in a range of differing sockets, Socket 479, Socket M, Socket P, each incompatible with the other two.
Socket 478 is used in combination with DDR SDRAM. All socket have the following mechanical maximum load limits which should not be exceeded during heatsink assembly, shipping conditions, or standard use. Load above those limits will crack the processor make it unusable. See List of Intel chipsets#Pentium 4 chipsets List of Intel microprocessors Socket information at the Wayback Machine
The Xbox 360 is a home video game console developed by Microsoft. As the successor to the original Xbox, it is the second console in the Xbox series, it competed with Sony's PlayStation 3 and Nintendo's Wii as part of the seventh generation of video game consoles. It was unveiled on MTV on May 12, 2005, with detailed launch and game information announced that month at the 2005 Electronic Entertainment Expo; the Xbox 360 features an online service, Xbox Live, expanded from its previous iteration on the original Xbox and received regular updates during the console's lifetime. Available in free and subscription-based varieties, Xbox Live allows users to: play games online. In addition to online multimedia features, it allows users to stream media from local PCs. Several peripherals have been released, including wireless controllers, expanded hard drive storage, the Kinect motion sensing camera; the release of these additional services and peripherals helped the Xbox brand grow from gaming-only to encompassing all multimedia, turning it into a hub for living-room computing entertainment.
Launched worldwide across 2005–2006, the Xbox 360 was in short supply in many regions, including North America and Europe. The earliest versions of the console suffered from a high failure rate, indicated by the so-called "Red Ring of Death", necessitating an extension of the device's warranty period. Microsoft released two redesigned models of the console: the Xbox 360 S in 2010, the Xbox 360 E in 2013; as of June 2014, 84 million Xbox 360 consoles have been sold worldwide, making it the seventh-highest-selling video game console in history, the highest-selling console made by an American company. Although not the best-selling console of its generation, the Xbox 360 was deemed by TechRadar to be the most influential through its emphasis on digital media distribution and multiplayer gaming on Xbox Live; the Xbox 360's successor, the Xbox One, was released on November 22, 2013. On April 20, 2016, Microsoft announced that it would end the production of new Xbox 360 hardware, although the company will continue to support the platform.
Known during development as Xbox Next, Xbox 2, Xbox FS or NextBox, the Xbox 360 was conceived in early 2003. In February 2003, planning for the Xenon software platform began, was headed by Microsoft's Vice President J Allard; that month, Microsoft held an event for 400 developers in Bellevue, Washington to recruit support for the system. That month, Peter Moore, former president of Sega of America, joined Microsoft. On August 12, 2003, ATI signed on to produce the graphic processing unit for the new console, a deal, publicly announced two days later. Before the launch of the Xbox 360, several Alpha development kits were spotted using Apple's Power Mac G5 hardware; this was because the system's PowerPC 970 processor running the same PowerPC architecture that the Xbox 360 would run under IBM's Xenon processor. The cores of the Xenon processor were developed using a modified version of the PlayStation 3's Cell Processor PPE architecture. According to David Shippy and Mickie Phipps, the IBM employees were "hiding" their work from Sony and Toshiba, IBM's partners in developing the Cell Processor.
Jeff Minter created the music visualization program Neon, included with the Xbox 360. The Xbox 360 was released on November 2005, in the United States and Canada, it was launched in Mexico, Chile, Hong Kong, South Korea, Australia, New Zealand, South Africa and Russia. In its first year on the market, the system launched in 36 countries, more countries than any other console has launched in a single year. In 2009, IGN named the Xbox 360 the sixth-greatest video game console of all time, out of a field of 25. Although not the best-selling console of the seventh-generation, the Xbox 360 was deemed by TechRadar to be the most influential, by emphasizing digital media distribution and online gaming through Xbox Live, by popularizing game achievement awards. PC Magazine considered the Xbox 360 the prototype for online gaming as it "proved that online gaming communities could thrive in the console space". Five years after the Xbox 360's original debut, the well-received Kinect motion capture camera was released, which set the record of being the fastest selling consumer electronic device in history, extended the life of the console.
Edge ranked Xbox 360 the second-best console of the 1993–2013 period, stating "It had its own social network, cross-game chat, new indie games every week, the best version of just about every multiformat game... Killzone is no Halo and nowadays Gran Turismo is no Forza, but it's not about the exclusives—there's nothing to trump Naughty Dog's PS3 output, after all. Rather, it's about the choices Microsoft made back in the original Xbox's lifetime; the PC-like architecture meant the early EA Sports games ran at 60fps compared to only 30 on PS3, Xbox Live meant every dedicated player had an existing friends list, Halo meant Microsoft had the killer next-generation exclusive. And when developers demo games on PC now they do it with a 360 pad—another industry benchmark, a critical one." The Xbox 360 began production only 69 days before launch, Microsoft was not able to supply enough systems to meet initial consumer demand in Europe or North America, selling out upon release in all regions except in Japan.
Forty thousand units were offered for sale on auction site eBay during the initial week of
Serial ATA is a computer bus interface that connects host bus adapters to mass storage devices such as hard disk drives, optical drives, solid-state drives. Serial ATA succeeded the earlier Parallel ATA standard to become the predominant interface for storage devices. Serial ATA industry compatibility specifications originate from the Serial ATA International Organization which are promulgated by the INCITS T13 subcommittee ATA Attachment SATA was announced in 2000 in order to provide several advantages over the earlier PATA interface such as reduced cable size and cost, native hot swapping, faster data transfer through higher signaling rates, more efficient transfer through an I/O queuing protocol. Serial ATA industry compatibility specifications originate from the Serial ATA International Organization; the SATA-IO group collaboratively creates, reviews and publishes the interoperability specifications, the test cases and plugfests. As with many other industry compatibility standards, the SATA content ownership is transferred to other industry bodies: the INCITS T13 subcommittee AT Attachment, the INCITS T10 subcommittee, a subgroup of T10 responsible for Serial Attached SCSI.
The remainder of this article strives to use specifications. Before SATA's introduction in 2000, PATA was known as ATA; the "AT Attachment" name originated after the 1984 release of the IBM Personal Computer AT, more known as the IBM AT. The IBM AT’s controller interface became a de facto industry interface for the inclusion of hard disks. "AT" was IBM's abbreviation for "Advanced Technology". However, the ATA specifications use the name "AT Attachment", to avoid possible trademark issues with IBM. SATA host adapters and devices communicate via a high-speed serial cable over two pairs of conductors. In contrast, parallel ATA uses a 16-bit wide data bus with many additional support and control signals, all operating at a much lower frequency. To ensure backward compatibility with legacy ATA software and applications, SATA uses the same basic ATA and ATAPI command sets as legacy ATA devices. SATA has replaced parallel ATA in consumer laptop computers. PATA has been replaced by SATA for any use. A 2008 standard, CFast to replace CompactFlash is based on SATA.
The Serial ATA Spec requires SATA device hot plugging. After insertion, the device initializes and operates normally. Depending upon the operating system the host may initialize resulting in a hot swap; the powered host or device are not in a quiescent state. Unlike PATA, both SATA and eSATA support hotplugging by design. However, this feature requires proper support at the host and operating-system levels. In general, all SATA devices support hotplugging most SATA host adapters support this function. For eSATA function, Hot Plug function is supported in AHCI mode only. IDE mode does not support Hot Plug function. Advanced Host Controller Interface is an open host controller interface published and used by Intel, which has become a de facto standard, it allows the use of advanced features of SATA such as native command queuing. If AHCI is not enabled by the motherboard and chipset, SATA controllers operate in "IDE emulation" mode, which does not allow access to device features not supported by the ATA standard.
Windows device drivers that are labeled as SATA are running in IDE emulation mode unless they explicitly state that they are AHCI mode, in RAID mode, or a mode provided by a proprietary driver and command set that allowed access to SATA's advanced features before AHCI became popular. Modern versions of Microsoft Windows, Mac OS X, FreeBSD, Linux with version 2.6.19 onward, as well as Solaris and OpenSolaris, include support for AHCI, but earlier operating systems such as Windows XP do not. In those instances, a proprietary driver may have been created for a specific chipset, such as Intel's. SATA revisions are designated with a dash followed by roman numerals, e.g. "SATA-III", to avoid confusion with the speed, always displayed in Arabic numerals, e.g. "SATA 6 Gbit/s". Revision 1.0a was released on January 7, 2003. First-generation SATA interfaces, now known as SATA 1.5 Gbit/s, communicate at a rate of 1.5 Gbit/s, do not support Native Command Queuing. Taking 8b/10b encoding overhead into account, they have an actual uncoded transfer rate of 1.2 Gbit/s.
The theoretical burst throughput of SATA 1.5 Gbit/s is similar to that of PATA/133, but newer SATA devices offer enhancements such as NCQ, which improve performance in a multitasking environment. During the initial period after SATA 1.5 Gbit/s finalization and drive manufacturers used a "bridge chip" to convert existing PATA designs for use with the SATA interface. Bridged drives have a SATA connector, may include either or both kinds of power connectors, and, in general, perform identically to their native-SATA equivalents. However, most bridged drives lack support for some SATA-specific features such as NCQ
Released in August 1995, four months before the more famous Cyrix 6x86, the Cyrix 5x86 was one of the fastest CPUs produced for Socket 3 computer systems. With better performance in most applications than an Intel Pentium processor at 75 MHz, the Cyrix Cx5x86 filled a gap by providing a medium-performance processor option for 486 Socket 3 motherboards; the Cyrix 5x86 processor, codename "M1sc", was based on a scaled-down version of the "M1" core used in the Cyrix 6x86, which provided 80% of the performance for a 50% decrease in transistors over the 6x86 design. It had the 32-bit memory bus of an ordinary 486 processor, but internally had much more in common with fifth-generation processors such as the Cyrix 6x86, the AMD K5, the Intel Pentium, the sixth-generation Intel Pentium Pro; the chip featured near-complete support for i486 instructions, but limited support for Pentium instructions. Some performance-enhancing features of the CPU were intentionally disabled due to stability-threatening bugs which were not fixed before release time.
The named SGS-Thomson ST5x86 and IBM IBM5x86C were licensed rebrandings of the Cyrix design, marketed separately but identical for practical purposes, apart from the availability of a 75 MHz edition which Cyrix did not bring to market, slight differences in voltage requirements. The Cyrix 5x86 design, should not be confused with the named AMD Am5x86, a fast 486 but which had broadly similar performance, used the same Socket 3, was introduced at the end of the same year. Cyrix's 5x86 was a short-lived chip, having a market life of only six months, it is Cyrix could have continued to sell processors based on Socket 3, but canned the 5x86 so that it would not compete with its new 6x86 offerings. The official Cyrix 5x86 website boasted about several features of the chip that were disabled by default in the final versions; the most controversial of these features was the "branch-prediction" feature, enabled in the benchmarks results on the company website when comparing the chip to Intel's Pentium processor.
While it was possible to enable the extra features using a special software utility, it resulted in an unstable system on earlier steppings of the chip when running 32-bit code. There are many rumours surrounding a 133 MHz, clock-quadrupled version of the Cyrix 5x86; the 133 MHz version is rare and producers of upgrade kits were given preferential access to it, notably Gainbery. Some of the 100 and 120 MHz parts contain support for the 4X multiplier setting, some of these chips may work at 133 MHz. However, the 5x86 is not known to overclock well. An 80 MHz 5x86 exists, but is unclear as to whether or not it was officially released. IBM's 5x86C was considered to be more conservatively rated than the Cyrix branded parts, operated at a lower voltage. For example: what Cyrix would rate as a 100 MHz part, IBM would mark as 75 MHz. IBM 5x86C was available as 100 MHz parts. A few examples of 120MHz parts exist, but they have early production dates indicating that they may have been produced prior to IBM's decision to scale back clock speeds.
5x86C had a much longer production run than the Cyrix branded parts. IBM continued to produce 5x86C at least until late 1998, whereas Cyrix's own part was discontinued in 1996. Parts which implement the 4X multiplier or Stepping 1 Rev 3 cores are not known to exist. IDX4WB pinout, 168 pins Socket 3 2.0 million transistors on 0.65 micrometre process 144mm² die 3.45 volts 16 kilobytes unified level-one cache100 MHz capable edition for 33 MHz, 50 MHz front side bus100 MHz capable edition for 33 MHz, 25 MHz front side bus120/133 MHz capable edition for 40 MHz and 33 MHz front side bus. Comparative performance benchmarks Cyrix 5x86 Cyrix 5x86 Processor Brief Entry in 486 processors chart Performance-enhancing utility to enable 5x86 "register bits" Information on write-back cache performance-enhancing utility from Evergreen Tech
Graphics processing unit
A graphics processing unit is a specialized electronic circuit designed to manipulate and alter memory to accelerate the creation of images in a frame buffer intended for output to a display device. GPUs are used in embedded systems, mobile phones, personal computers and game consoles. Modern GPUs are efficient at manipulating computer graphics and image processing, their parallel structure makes them more efficient than general-purpose CPUs for algorithms that process large blocks of data in parallel. In a personal computer, a GPU can be present on a video card or embedded on the motherboard. In certain CPUs, they are embedded on the CPU die; the term GPU has been used from at least the 1980s. It was popularized by Nvidia in 1999, who marketed the GeForce 256 as "the world's first GPU", it was presented as a "single-chip processor with integrated transform, triangle setup/clipping, rendering engines". Rival ATI Technologies coined the term "visual processing unit" or VPU with the release of the Radeon 9700 in 2002.
Arcade system boards have been using specialized graphics chips since the 1970s. In early video game hardware, the RAM for frame buffers was expensive, so video chips composited data together as the display was being scanned out on the monitor. Fujitsu's MB14241 video shifter was used to accelerate the drawing of sprite graphics for various 1970s arcade games from Taito and Midway, such as Gun Fight, Sea Wolf and Space Invaders; the Namco Galaxian arcade system in 1979 used specialized graphics hardware supporting RGB color, multi-colored sprites and tilemap backgrounds. The Galaxian hardware was used during the golden age of arcade video games, by game companies such as Namco, Gremlin, Konami, Nichibutsu and Taito. In the home market, the Atari 2600 in 1977 used a video shifter called the Television Interface Adaptor; the Atari 8-bit computers had ANTIC, a video processor which interpreted instructions describing a "display list"—the way the scan lines map to specific bitmapped or character modes and where the memory is stored.
6502 machine code subroutines could be triggered on scan lines by setting a bit on a display list instruction. ANTIC supported smooth vertical and horizontal scrolling independent of the CPU; the NEC µPD7220 was one of the first implementations of a graphics display controller as a single Large Scale Integration integrated circuit chip, enabling the design of low-cost, high-performance video graphics cards such as those from Number Nine Visual Technology. It became one of the best known of; the Williams Electronics arcade games Robotron 2084, Joust and Bubbles, all released in 1982, contain custom blitter chips for operating on 16-color bitmaps. In 1985, the Commodore Amiga featured a custom graphics chip, with a blitter unit accelerating bitmap manipulation, line draw, area fill functions. Included is a coprocessor with its own primitive instruction set, capable of manipulating graphics hardware registers in sync with the video beam, or driving the blitter. In 1986, Texas Instruments released the TMS34010, the first microprocessor with on-chip graphics capabilities.
It could run general-purpose code, but it had a graphics-oriented instruction set. In 1990-1992, this chip would become the basis of the Texas Instruments Graphics Architecture Windows accelerator cards. In 1987, the IBM 8514 graphics system was released as one of the first video cards for IBM PC compatibles to implement fixed-function 2D primitives in electronic hardware; the same year, Sharp released the X68000, which used a custom graphics chipset, powerful for a home computer at the time, with a 65,536 color palette and hardware support for sprites and multiple playfields serving as a development machine for Capcom's CP System arcade board. Fujitsu competed with the FM Towns computer, released in 1989 with support for a full 16,777,216 color palette. In 1988, the first dedicated polygonal 3D graphics boards were introduced in arcades with the Namco System 21 and Taito Air System. In 1991, S3 Graphics introduced the S3 86C911, which its designers named after the Porsche 911 as an indication of the performance increase it promised.
The 86C911 spawned a host of imitators: by 1995, all major PC graphics chip makers had added 2D acceleration support to their chips. By this time, fixed-function Windows accelerators had surpassed expensive general-purpose graphics coprocessors in Windows performance, these coprocessors faded away from the PC market. Throughout the 1990s, 2D GUI acceleration continued to evolve; as manufacturing capabilities improved, so did the level of integration of graphics chips. Additional application programming interfaces arrived for a variety of tasks, such as Microsoft's WinG graphics library for Windows 3.x, their DirectDraw interface for hardware acceleration of 2D games within Windows 95 and later. In the early- and mid-1990s, real-time 3D graphics were becoming common in arcade and console games, which led to an increasing public demand for hardware-accelerated 3D graphics. Early examples of mass-market 3D graphics hardware can be found in arcade system boards such as the Sega Model 1, Namco System 22, Sega Model 2, the fifth-generation video game consoles such as the Saturn, PlayStation and Nintendo 64.
Arcade systems such as the Sega Model 2 and Namco Magic Edge Hornet Simulator in 1993 were capable of hardware T&L years before appearing in consu
The first Pentium microprocessor was introduced by Intel on March 22, 1993. Dubbed P5, its microarchitecture was the fifth generation for Intel, the first superscalar IA-32 microarchitecture; as a direct extension of the 80486 architecture, it included dual integer pipelines, a faster floating-point unit, wider data bus, separate code and data caches and features for further reduced address calculation latency. In 1996, the Pentium with MMX Technology was introduced with the same basic microarchitecture complemented with an MMX instruction set, larger caches, some other enhancements; the P5 Pentium competitors included the Motorola 68060 and the PowerPC 601 as well as the SPARC, MIPS, Alpha microprocessor families, most of which used a superscalar in-order dual instruction pipeline configuration at some time. Intel's Larrabee multicore architecture project uses a processor core derived from a P5 core, augmented by multithreading, 64-bit instructions, a 16-wide vector processing unit. Intel's low-powered Bonnell microarchitecture employed in early Atom processor cores uses an in-order dual pipeline similar to P5.
Intel discontinued the P5 Pentium processors in 1999 in favor of the Celeron processor which replaced the 80486 brand. The P5 microarchitecture was designed by the same Santa Clara team which designed the 386 and 486. Design work started in 1989; the preliminary design was first simulated in 1990, followed by the laying-out of the design. By this time, the team had several dozen engineers; the design was taped out, or transferred to silicon, in April 1992, at which point beta-testing began. By mid-1992, the P5 team had 200 engineers. Intel at first planned to demonstrate the P5 in June 1992 at the trade show PC Expo, to formally announce the processor in September 1992, but design problems forced the demo to be cancelled, the official introduction of the chip was delayed until the spring of 1993. John H. Crawford, chief architect of the original 386, co-managed the design of the P5, along with Donald Alpert, who managed the architectural team. Dror Avnon managed the design of the FPU. Vinod K. Dham was general manager of the P5 group.
The P5 microarchitecture brings several important advancements over the preceding i486 architecture. Performance: Superscalar architecture — The Pentium has two datapaths that allow it to complete two instructions per clock cycle in many cases; the main pipe can handle any instruction, while the other can handle the most common simple instructions. Some RISC proponents had argued that the "complicated" x86 instruction set would never be implemented by a pipelined microarchitecture, much less by a dual-pipeline design; the 486 and the Pentium demonstrated that this was indeed feasible. 64-bit external databus doubles the amount of information possible to read or write on each memory access and therefore allows the Pentium to load its code cache faster than the 80486. Separation of code and data caches lessens the fetch and operand read/write conflicts compared to the 486. To reduce access time and implementation cost, both of them are 2-way associative, instead of the single 4-way cache of the 486.
A related enhancement in the Pentium is the ability to read a contiguous block from the code cache when it is split between two cache lines. Much faster floating-point unit; some instructions showed an enormous improvement, most notably FMUL, with up to 15 times higher throughput than in the 80486 FPU. The Pentium is able to execute a FXCH ST instruction in parallel with an ordinary FPU instruction. Four-input address adders enables the Pentium to further reduce the address calculation latency compared to the 80486; the Pentium can calculate full addressing modes with segment-base + base-register + scaled register + immediate offset in a single cycle. The microcode can employ both pipelines to enable auto-repeating instructions such as REP MOVSW perform one iteration every clock cycle, while the 80486 needed three clocks per iteration. Optimization of the access to the first microcode words during the decode stages helps in making several frequent instructions execute more especially in their most common forms and in typical cases.
Some examples are: CALL, RET, shifts/rotates. A faster hardware-based multiplier makes instructions such as MUL and IMUL several times faster than in the 80486. Virtualized interrupt to speed up virtual 8086 mode. Other features: Enhanced debug features with the introduction of the Processor-based debug port. Enhanced self-test features like the L1 cache parity check. New instructions: CPUID, CMPXCHG8B, RDTSC, RDMSR, WRMSR, RSM. Test registers TR0–TR7 and MOV instructions for access to them were eliminated; the Pentium MMX added the MMX instruction set, a basic integer SIMD instruction set extension marketed for use in multimedia applications. MMX could not be used with the x87 FPU instructions because the registers were