In computer engineering, microarchitecture called computer organization and sometimes abbreviated as µarch or uarch, is the way a given instruction set architecture is implemented in a particular processor. A given ISA may be implemented with different microarchitectures. Computer architecture is the combination of instruction set architecture; the ISA is the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers and data formats among other things; the microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is represented as diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be anything from single gates and registers, to complete arithmetic logic units and larger elements; these diagrams separate the datapath and the control path.
The person designing a system draws the specific microarchitecture as a kind of data flow diagram. Like a block diagram, the microarchitecture diagram shows microarchitectural elements such as the arithmetic and logic unit and the register file as a single schematic symbol; the diagram connects those elements with arrows, thick lines and thin lines to distinguish between three-state buses, unidirectional buses, individual control lines. Simple computers have a single data bus organization – they have a single three-state bus; the diagram of more complex computers shows multiple three-state buses, which help the machine do more operations simultaneously. Each microarchitectural element is in turn represented by a schematic describing the interconnections of logic gates used to implement it; each logic gate is in turn represented by a circuit diagram describing the connections of the transistors used to implement it in some particular logic family. Machines with different microarchitectures may have the same instruction set architecture, thus be capable of executing the same programs.
New microarchitectures and/or circuitry solutions, along with advances in semiconductor manufacturing, are what allows newer generations of processors to achieve higher performance while using the same ISA. In principle, a single microarchitecture could execute several different ISAs with only minor changes to the microcode; the pipelined datapath is the most used datapath design in microarchitecture today. This technique is used in most modern microprocessors, DSPs; the pipelined architecture allows multiple instructions to overlap in execution, much like an assembly line. The pipeline includes several different stages; some of these stages include instruction fetch, instruction decode and write back. Some architectures include other stages such as memory access; the design of pipelines is one of the central microarchitectural tasks. Execution units are essential to microarchitecture. Execution units include arithmetic logic units, floating point units, load/store units, branch prediction, SIMD.
These units perform the calculations of the processor. The choice of the number of execution units, their latency and throughput is a central microarchitectural design task; the size, latency and connectivity of memories within the system are microarchitectural decisions. System-level design decisions such as whether or not to include peripherals, such as memory controllers, can be considered part of the microarchitectural design process; this includes decisions on the connectivity of these peripherals. Unlike architectural design, where achieving a specific performance level is the main goal, microarchitectural design pays closer attention to other constraints. Since microarchitecture design decisions directly affect what goes into a system, attention must be paid to issues such as chip area/cost, power consumption, logic complexity, ease of connectivity, manufacturability, ease of debugging, testability. In general, all CPUs, single-chip microprocessors or multi-chip implementations run programs by performing the following steps: Read an instruction and decode it Find any associated data, needed to process the instruction Process the instruction Write the results outThe instruction cycle is repeated continuously until the power is turned off.
Complicating this simple-looking series of steps is the fact that the memory hierarchy, which includes caching, main memory and non-volatile storage like hard disks, has always been slower than the processor itself. Step introduces a lengthy delay while the data arrives over the computer bus. A considerable amount of research has been put into designs that avoid these delays as much as possible. Over the years, a central goal was to execute more instructions in parallel, thus increasing the effective execution speed of a program; these efforts introduced complicated circuit structures. These techniques could only be implemented on expensive mainframes or supercomputers due to the amount of circuitry needed for these techniques; as semiconductor manufacturing progressed and more of these techniq
A semiconductor material has an electrical conductivity value falling between that of a metal, like copper, etc. and an insulator, such as glass. Their resistance decreases as their temperature increases, behaviour opposite to that of a metal, their conducting properties may be altered in useful ways by the deliberate, controlled introduction of impurities into the crystal structure. Where two differently-doped regions exist in the same crystal, a semiconductor junction is created; the behavior of charge carriers which include electrons and electron holes at these junctions is the basis of diodes and all modern electronics. Some examples of semiconductors are silicon and gallium arsenide. After silicon, gallium arsenide is the second most common semiconductor used in laser diodes, solar cells, microwave frequency integrated circuits, others. Silicon is a critical element for fabricating most electronic circuits. Semiconductor devices can display a range of useful properties such as passing current more in one direction than the other, showing variable resistance, sensitivity to light or heat.
Because the electrical properties of a semiconductor material can be modified by doping, or by the application of electrical fields or light, devices made from semiconductors can be used for amplification and energy conversion. The conductivity of silicon is increased by adding a small amount of trivalent atoms; this process is known as doping and resulting semiconductors are known as doped or extrinsic semiconductors. Apart from doping, the conductivity of a semiconductor can be improved by increasing its temperature; this is contrary to the behaviour of a metal in which conductivity decreases with increase in temperature. The modern understanding of the properties of a semiconductor relies on quantum physics to explain the movement of charge carriers in a crystal lattice. Doping increases the number of charge carriers within the crystal; when a doped semiconductor contains free holes it is called "p-type", when it contains free electrons it is known as "n-type". The semiconductor materials used in electronic devices are doped under precise conditions to control the concentration and regions of p- and n-type dopants.
A single semiconductor crystal can have many p- and n-type regions. Although some pure elements and many compounds display semiconductor properties, silicon and compounds of gallium are the most used in electronic devices. Elements near the so-called "metalloid staircase", where the metalloids are located on the periodic table, are used as semiconductors; some of the properties of semiconductor materials were observed throughout the mid 19th and first decades of the 20th century. The first practical application of semiconductors in electronics was the 1904 development of the cat's-whisker detector, a primitive semiconductor diode used in early radio receivers. Developments in quantum physics in turn allowed the development of the transistor in 1947 and the integrated circuit in 1958. Variable electrical conductivity Semiconductors in their natural state are poor conductors because a current requires the flow of electrons, semiconductors have their valence bands filled, preventing the entry flow of new electrons.
There are several developed techniques that allow semiconducting materials to behave like conducting materials, such as doping or gating. These modifications have two outcomes: p-type; these refer to the shortage of electrons, respectively. An unbalanced number of electrons would cause a current to flow through the material. Heterojunctions Heterojunctions occur when two differently doped semiconducting materials are joined together. For example, a configuration could consist of n-doped germanium; this results in an exchange of electrons and holes between the differently doped semiconducting materials. The n-doped germanium would have an excess of electrons, the p-doped germanium would have an excess of holes; the transfer occurs until equilibrium is reached by a process called recombination, which causes the migrating electrons from the n-type to come in contact with the migrating holes from the p-type. A product of this process is charged ions. Excited electrons A difference in electric potential on a semiconducting material would cause it to leave thermal equilibrium and create a non-equilibrium situation.
This introduces electrons and holes to the system, which interact via a process called ambipolar diffusion. Whenever thermal equilibrium is disturbed in a semiconducting material, the number of holes and electrons changes; such disruptions can occur as a result of a temperature difference or photons, which can enter the system and create electrons and holes. The process that creates and annihilates electrons and holes are called generation and recombination. Light emission In certain semiconductors, excited electrons can relax by emitting light instead of producing heat; these semiconductors are used in the construction of light-emitting diodes and fluorescent quantum dots. High thermal conductivitySemiconductors with high thermal conductivity can be used for heat dissipation and improving thermal management of electronics. Thermal energy conversion Semiconductors have large thermoelectric power factors making them useful in thermoelectric generators, as well as high thermoelectric figures of merit making them useful in thermoelectric coolers.
A large number of elements and compounds have semiconducting properties, including: Certain pure elements are found in Group 14 of the p
Arm Holdings is a British multinational semiconductor and software design company, owned by SoftBank Group and its Vision Fund. With its headquarters in Cambridgeshire, within the United Kingdom, its primary business is in the design of ARM processors, although it designs software development tools under the DS-5, RealView and Keil brands, as well as systems and platforms, system-on-a-chip infrastructure and software; as a "Holding" company, it holds shares of other companies. It is considered to be market dominant for processors in mobile phones and tablet computers; the company is one of the best-known "Silicon Fen" companies. Processors based on designs licensed from Arm, or designed by licensees of one of the Arm instruction set architectures, are used in all classes of computing devices. Examples of those processors range from the world's smallest computer to the processors in some supercomputers on the TOP500 list. Processors designed by Arm or by Arm licensees are used as microcontrollers in embedded systems, including real-time safety systems, biometrics systems, smart TVs, all modern smartwatches, are used as general-purpose processors in smartphones, laptops, desktops and supercomputers/HPC, e.g. a CPU "option" in Cray's supercomputers.
Arm's Mali line of graphics processing units are used in laptops, in over 50% of Android tablets by market share, some versions of Samsung's smartphones and smartwatches. It is the third most popular GPU in mobile devices. Systems, including iPhone smartphones include many chips, from many different providers, that include one or more licensed Arm cores, in addition to those in the main Arm-based processor. Arm's core designs are used in chips that support many common network related technologies in smartphones: Bluetooth, WiFi and broadband, in addition to corresponding equipment such as Bluetooth headsets, 802.11ac routers, network providers' cellular LTE. Arm's main CPU competitors in servers include Intel and AMD. In mobile applications, Intel's x86 Atom is a competitor. AMD sells Arm-based chips as well as x86. Arm's main GPU competitors include mobile GPUs from Imagination Technologies and Nvidia and Intel. Despite competing within GPUs, Qualcomm and Nvidia have combined their GPUs with an Arm licensed CPU.
Arm was a constituent of the FTSE 100 Index. It had a secondary listing on NASDAQ; however Japanese telecommunications company SoftBank Group made an agreed offer for Arm on 18 July 2016, subject to approval by Arm's shareholders, valuing the company at £23.4 billion. The transaction was completed on 5 September 2016; the acronym ARM was first used in 1983 and stood for "Acorn RISC Machine". Acorn Computers' first RISC processor was used in the original Acorn Archimedes and was one of the first RISC processors used in small computers. However, when the company was incorporated in 1990, the acronym was changed to "Advanced RISC Machines", in light of the company's name "Advanced RISC Machines Ltd." - and according to an interview with Steve Furber the name change was at the behest of Apple who did not wish to have the name of a former competitor - namely Acorn - in the name of the company. At the time of the IPO in 1998, the company name was changed to "ARM Holdings" just called ARM like the processors.
On 1 August 2017, the logo were changed. The logo is now all lowercase and other uses of'ARM' are in sentence case except where the whole sentence is upper case, so, for instance, it is now'Arm Holdings'; the company was founded in November 1990 as Advanced RISC Machines Ltd and structured as a joint venture between Acorn Computers, Apple Computer and VLSI Technology. The new company intended to further the development of the Acorn RISC Machine processor, used in the Acorn Archimedes and had been selected by Apple for their Newton project, its first profitable year was 1993. The company's Silicon Valley and Tokyo offices were opened in 1994. Arm invested in Palmchip Corporation in 1997 to provide system on chip platforms and to enter into the disk drive market. In 1998, the company changed its name from Advanced RISC Machines Ltd to ARM Ltd; the company was first listed on the London Stock Exchange and NASDAQ in 1998 and by February 1999, Apple's shareholding had fallen to 14.8%. In 2010, Arm joined with IBM, Texas Instruments, Samsung, ST-Ericsson and Freescale Semiconductor in forming a non-profit open source engineering company, Linaro.
Micrologic Solutions, a software consulting company based in Cambridge Allant Software, a developer of debugging software Infinite Designs, a design company based in Sheffield EuroMIPS a smart card design house in Sophia Antipolis, France The engineering team of Noral Micrologics, a debug hardware and software company based in Blackburn, England Adelante Technologies of Belgium, creating its OptimoDE data engines business, a form of lightweight DSP engine Axys Design Automation, a developer of ESL design tools and Artisan Components, a designer of Physical IP, the building blocks of integrated circuits KEIL Software, a leading developer of software development tools for the microcontroller market, including 8051 and C16x platforms. Arm acquired the engineering team of PowerEscape. Falanx, a developer of 3D graphics accelerators a
Intel's i960 was a RISC-based microprocessor design that became popular during the early 1990s as an embedded microcontroller. It became a best-selling CPU in that segment, along with the competing AMD 29000. In spite of its success, Intel stopped marketing the i960 in the late 1990s, as a result of a settlement with DEC whereby Intel received the rights to produce the StrongARM CPU; the processor continues to be used for a few military applications. The i960 design was begun in response to the failure of Intel's iAPX 432 design of the early 1980s; the iAPX 432 was intended to directly support high-level languages that supported tagged, garbage-collected memory—such as Ada and Lisp—in hardware. Because of its instruction-set complexity, its multi-chip implementation, design flaws, the iAPX 432 was slow in comparison to other processors of its time. In 1984, Intel and Siemens started a joint project called BiiN, to create a high-end, fault-tolerant, object-oriented computer system programmed in Ada.
Many of the original i432 team members joined this project, although a new lead architect, Glenford Myers, was brought in from IBM. The intended market for the BiiN systems was high-reliability-computer users such as banks, industrial systems, nuclear power plants. Intel's major contribution to the BiiN system was a new processor design, influenced by the protected-memory concepts from the i432; the new design was to include a number of features to improve performance and avoid problems that had led to the i432's downfall. The first 960 processors entered the final stages of design, known as taping-out, in October 1985 and were sent to manufacturing that month, with the first working chips arriving in late 1985 and early 1986; the BiiN effort failed, due to market forces, the 960MX was left without a use. Myers attempted to save the design by extracting several subsets of the full capability architecture created for the BiiN system, he tried to convince Intel management to market the i960 as a general-purpose processor, both in place of the Intel 80286 and i386, as well as the emerging RISC market for Unix systems, including a pitch to Steve Jobs for use in the NeXT system.
Competition within and outside of Intel came not only from the i386 camp but from the i860 processor, yet another RISC processor design emerging within Intel at the time. Myers was unsuccessful at convincing Intel management to support the i960 as a general-purpose or Unix processor, but the chip found a ready market in early high-performance 32-bit embedded systems; the lead architect of i960 was superscalarity specialist Fred Pollack, the lead engineer of the Intel iAPX 432 and the lead architect of the i686 chip, the Pentium Pro. To avoid the performance issues that plagued the i432, the central i960 instruction-set architecture was a RISC design, only implemented in full in the i960MX; the memory subsystem was 33-bits wide—to accommodate a 32-bit word and a "tag" bit to implement memory protection in hardware. In many ways, the i960 followed the original Berkeley RISC design, notably in its use of register windows, an implementation-specific number of caches for the per-subroutine registers that allowed for fast subroutine calls.
The competing Stanford University design, MIPS, did not use this system, instead relying on the compiler to generate optimal subroutine call and return code. In common with most 32-bit designs, the i960 has a flat 32-bit memory space, with no memory segmentation; the i960 architecture anticipated a superscalar implementation, with instructions being dispatched to more than one unit within the processor. The "full" i960MX was never released for the non-military market, but the otherwise identical i960MC was used in high-end embedded applications; the i960MC included all of the features of the original BiiN system. A version of the RISC core without memory management or an FPU became the i960KA, the RISC core with an FPU became the i960KB; the versions were, identical internally—only the labeling was different. This meant the CPUs were much larger than necessary for the "actually supported" feature sets, as a result, more expensive to manufacture than they needed to be; the i960KA became successful as a low-cost 32-bit processor for the laser-printer market, as well as for early graphics terminals and other embedded applications.
Its success paid for future generations. The i960CA, first announced in July 1989, was the first pure RISC implementation of the i960 architecture, it featured a newly designed superscalar RISC core and added an unusual addressable on-chip cache, but lacked an FPU and MMU, as it was intended for high-performance embedded applications. The i960CA is considered to have been the first single-chip superscalar RISC implementation; the C-series included only one ALU, but could dispatch and execute an arithmetic instruction, a memory reference, a branch instruction at the same time, sustain two instructions per cycle under certain circumstances. The first versions released ran at 33 MHz, Intel promoted the chip as capable of 66 MIPS; the i960CA microarchitecture was designed in 1987–1988 and formally announced on September 12, 1989. In May 1992, came the i960CF, which included a larger instruction cache and added 1 KB of data cache, but was still without an FPU or MMU; the 80960Jx is a processor for embedded applications.
It features a 32-bit multiplexed address/data bus and data cache, 1K on-chip RAM
A set-top box or set-top unit is an information appliance device that contains a TV-tuner input and displays output to a television set and an external source of signal, turning the source signal into content in a form that be displayed on the television screen or other display device. They are used in cable television, satellite television, over-the-air television systems, as well as other uses. According to the Los Angeles Times, the cost to a cable provider for a set-top box is between $150 for a basic box to $250 for a more sophisticated box in the United States. In 2016, the average pay-TV subscriber paid $231 per year to lease their set-top box from a cable service provider; the signal source might be an Ethernet cable, a satellite dish, a coaxial cable, a telephone line, broadband over power lines, or an ordinary VHF or UHF antenna. Content, in this context, could mean any or all of video, Internet web pages, interactive video games, or other possibilities. Satellite and microwave-based services require specific external receiver hardware, so the use of set-top boxes of various formats has never disappeared.
Set-top boxes can enhance source signal quality. Before the All-Channel Receiver Act of 1962 required US television receivers to be able to tune the entire VHF and UHF range, a set-top box known as a UHF converter would be installed at the receiver to shift a portion of the UHF-TV spectrum onto low-VHF channels for viewing; as some 1960s-era 12-channel TV sets remained in use for many years, Canada and Mexico were slower than the US to require UHF tuners to be factory-installed in new TVs, a market for these converters continued to exist for much of the 1970s. Cable television represented a possible alternative to deployment of UHF converters as broadcasts could be frequency-shifted to VHF channels at the cable head-end instead of the final viewing location. However, most cable systems could not accommodate the full 54-890 MHz VHF/UHF frequency range and the twelve channels of VHF space were exhausted on most systems. Adding any additional channels therefore needed to be done by inserting the extra signals into cable systems on nonstandard frequencies either below VHF channel 7 or directly above VHF channel 13.
These frequencies corresponded to non-television services over-the-air and were therefore not on standard TV receivers. Before cable-ready TV sets became common in the late 1980s, an electronic tuning device called a cable converter box was needed to receive the additional analog cable TV channels and transpose or convert the selected channel to analog radio frequency for viewing on a regular TV set on a single channel VHF channel 3 or 4; the box allowed an analog non-cable-ready television set to receive analog encrypted cable channels and was a prototype topology for date digital encryption devices. Newer televisions were converted to be analog cypher cable-ready, with the standard converter built-in for selling premium television. Several years and marketed, the advent of digital cable continued and increased the need for various forms of these devices. Block conversion of the entire affected frequency band onto UHF, while less common, was used by some models to provide full VCR compatibility and the ability to drive multiple TV sets, albeit with a somewhat nonstandard channel numbering scheme.
Newer television receivers reduced the need for external set-top boxes, although cable converter boxes continue to be used to descramble premium cable channels according to carrier-controlled access restrictions, to receive digital cable channels, along with using interactive services like video on demand, pay per view, home shopping through television. Set-top boxes were made to enable closed captioning on older sets in North America, before this became a mandated inclusion in new TV sets; some have been produced to mute the audio when profanity is detected in the captioning, where the offensive word is blocked. Some include a V-chip that allows only programs of some television content ratings. A function that limits children's time watching TV or playing video games may be built in, though some of these work on main electricity rather than the video signal; the transition to digital terrestrial television after the turn of the millennium left many existing television receivers unable to tune and display the new signal directly.
In the United States, where analog shutdown was completed in 2009 for full-service broadcasters, a federal subsidy was offered for coupon-eligible converter boxes with deliberately limited capability which would restore signals lost to digital transition. Professional set-top boxes are referred to as IRDs or integrated receiver/decoders in the professional broadcast audio/video industry, they are designed for rack mounting environments. IRDs are capable of outputting uncompressed serial digital interface signals, unlike consumer STBs which don't because of copyright reasons. Hybrid set-top boxes, such as those used for Smart TV programming, enable viewers to access multiple TV delivery methods. By integrating varying delivery streams, hybrids enable pay-TV operators more flexible application depl
The program counter called the instruction pointer in Intel x86 and Itanium microprocessors, sometimes called the instruction address register, the instruction counter, or just part of the instruction sequencer, is a processor register that indicates where a computer is in its program sequence. In most processors, the PC is incremented after fetching an instruction, holds the memory address of the next instruction that would be executed. Processors fetch instructions sequentially from memory, but control transfer instructions change the sequence by placing a new value in the PC; these include branches, subroutine calls, returns. A transfer, conditional on the truth of some assertion lets the computer follow a different sequence under different conditions. A branch provides. A subroutine saves the preceding contents of the PC somewhere. A return retrieves the saved contents of the PC and places it back in the PC, resuming sequential execution with the instruction following the subroutine call.
In a typical central processing unit, the PC is a digital counter that may be one of many registers in the CPU hardware. The instruction cycle begins with a fetch, in which the CPU places the value of the PC on the address bus to send it to the memory; the memory responds by sending the contents of that memory location on the data bus.. Following the fetch, the CPU proceeds to execution, taking some action based on the memory contents that it obtained. At some point in this cycle, the PC will be modified so that the next instruction executed is a different one. Like other processor registers, the PC may be a bank of binary latches, each one representing one bit of the value of the PC; the number of bits relates to the processor architecture. For instance, a “32-bit” CPU may use 32 bits to be able to address 232 units of memory. If the PC is a binary counter, it may increment when a pulse is applied to its COUNT UP input, or the CPU may compute some other value and load it into the PC by a pulse to its LOAD input.
To identify the current instruction, the PC may be combined with other registers that identify a segment or page. This approach permits a PC with fewer bits by assuming that most memory units of interest are within the current vicinity. Use of a PC that increments assumes that what a computer does is execute a linear sequence of instructions; such a PC is central to the von Neumann architecture. Thus programmers write a sequential control flow for algorithms that do not have to be sequential; the resulting “von Neumann bottleneck” led to research into parallel computing, including non-von Neumann or dataflow models that did not use a PC. This research led to ways to making conventional, PC-based, CPUs run faster, including: Pipelining, in which different hardware in the CPU executes different phases of multiple instructions simultaneously; the long instruction word architecture, where a single instruction can achieve multiple effects. Techniques to predict out-of-order execution and prepare subsequent instructions for execution outside the regular sequence.
Modern high-level programming languages still follow the sequential-execution model and, indeed, a common way of identifying programming errors is with a “procedure execution” in which the programmer's finger identifies the point of execution as a PC would. The high-level language is the machine language of a virtual machine, too complex to be built as hardware but instead emulated or interpreted by software. However, new programming models transcend sequential-execution programming: When writing a multi-threaded program, the programmer may write each thread as a sequence of instructions without specifying the timing of any instruction relative to instructions in other threads. In event-driven programming, the programmer may write sequences of instructions to respond to events without specifying an overall sequence for the program. In dataflow programming, the programmer may write each section of a computing pipeline without specifying the timing relative to other sections. Branch prediction Instruction cache Instruction cycle Instruction unit Instruction pipeline Instruction register Instruction scheduling Program status word
XScale is a microarchitecture for central processing units designed by Intel implementing the ARM architecture instruction set. XScale comprises several distinct families: IXP, IXC, IOP, PXA and CE, with some models designed as SoCs. Intel sold the PXA family to Marvell Technology Group in June 2006. Marvell extended the brand to include processors with other microarchitectures, like ARM's Cortex; the XScale architecture is based on the ARMv5TE ISA without the floating point instructions. XScale uses an eight-stage memory super-pipelined microarchitecture, it is the successor to the Intel StrongARM line of microprocessors and microcontrollers, which Intel acquired from DEC's Digital Semiconductor division as part of a settlement of a lawsuit between the two companies. Intel used the StrongARM to replace its ailing line of outdated RISC processors, the i860 and i960. All the generations of XScale are 32-bit ARMv5TE processors manufactured with a 0.18 µm or 0.13 µm process and have a 32 KB data cache and a 32 KB instruction cache.
First and second generation XScale multi-core processors have a 2 KB mini data cache. Products based on the 3rd generation XScale have up to 512 KB unified L2 cache; the XScale core is used in a number of microcontroller families manufactured by Intel and Marvell: Application processors. There are four generations of XScale application processors, described below: PXA210/PXA25x, PXA26x, PXA27x, PXA3xx. I/O processors. Network processors. Control plane processors. Consumer electronics processors. There are standalone processors: the 80200 and 80219; the PXA210 was Intel's entry-level XScale targeted at mobile phone applications. It comes clocked at 133 MHz and 200 MHz; the PXA25x family consists of the PXA250 and PXA255. The PXA250 was Intel's first generation of XScale processors. There was a choice of three clock speeds: 300 MHz and 400 MHz, it came out in February 2002. In March 2003, the revision C0 of the PXA250 was renamed to PXA255; the main differences were a doubled internal bus speed for faster data transfer, lower core voltage for lower power consumption and writeback functionality for the data cache, the lack of which had impaired performance on the PXA250.
The PXA26x family consists of the PXA260 and PXA261-PXA263. The PXA260 is a stand-alone processor clocked at the same frequency as the PXA25x, but features a TPBGA package, about 53% smaller than the PXA25x's PBGA package; the PXA261-PXA263 are the same as the PXA260 but have Intel StrataFlash memory stacked on top of the processor in the same package. The PXA26x family was released in March 2003; the PXA27x family consists of the PXA271-PXA272 processors. This revision is a huge update to the XScale family of processors; the PXA270 is clocked in four different speeds: 312 MHz, 416 MHz, 520 MHz and 624 MHz and is a stand-alone processor with no packaged memory. The PXA271 can be clocked to 13, 104, 208 MHz or 416 MHz and has 32 MB of 16-bit stacked StrataFlash memory and 32 MB of 16-bit SDRAM in the same package; the PXA272 can be clocked to 312 MHz, 416 MHz or 520 MHz and has 64 MB of 32-bit stacked StrataFlash memory. Intel added many new technologies to the PXA27x family such as: SpeedStep: the operating system can clock the processor down based on load to save power.
Wireless MMX: 43 new SIMD instructions containing the full MMX instruction set and the integer instructions from Intel's SSE instruction set along with some instructions unique to the XScale. Wireless MMX provides 16 extra 64-bit registers that can be treated as an array of two 32-bit words, four 16-bit halfwords or eight 8-bit bytes; the XScale core can perform up to eight adds or four MACs in parallel in a single cycle. This capability is used to boost speed in playing games. Additional peripherals, such as a USB-Host interface and a camera interface. Internal 256 KB SRAM to reduce power latency; the PXA27x family was released in April 2004. Along with the PXA27x family Intel released the 2700G embedded graphics co-processor. In August 2005 Intel announced the successor to Bulverde, codenamed Monahans, they demonstrated it showing its capability to play back high definition encoded video on a PDA screen. The new processor was shown clocked at 1.25 GHz but Intel said it only offered a 25% increase in performance.
An announced successor to the 2700G graphics processor, code named Stanwood, has since been canceled. Sd features of Stanwood are integrated into Monahans. For extra graphics capabilities, Intel recommends third-party chips like the Nvidia GoForce chip family. In November 2006, Marvell Semiconductor introduced the Monahans family as Marvell PXA320, PXA300, PXA310. PXA320 is shipping in high volume, is scalable up to 806 MHz. PXA300 and PXA310 deliver performance "scalable to 624 MHz", are software-compatible with PXA320; the PXA90x combines an XScale core with a GSM/CDMA communication module. The PXA90x is built using a 130 nm process PXA16x is a processor designed by Marvell, combining the earlier Intel designed PXA SoC components with a new ARMv5TE CPU core named