1.
Ten and a quarter inch gauge
–
Ten and a quarter inch gauge is a large scale, generally only used for ridable miniature railways. Model railways at this scale normally confine the scale modelling aspects to the reproduction of the locomotive, rolling stock is generally made to carry passengers or maintenance equipment and is not to scale. There are also a number of railways which use this gauge of track but are narrow gauge railways, examples are Rudyard Lake Steam Railway, Isle of Mull Railway and Wells and Walsingham Light Railway. An organisation to promote this gauge of railway has been reformed in May 2010 as The ten and this will also cover the larger 12 1⁄4 in and smaller 9 1⁄2 in gauges. M. N. R. Commercial companies also build bespoke locomotives or in the case of the Exmoor Steam Railway a standard design of 2-4-2T, rolling stock was normally supplied in the form of seaside coaches. However the more growth in narrow gauge style railways shows that fully enclosed coaches seating two side by side are possible and preferable for commercial railways. Rail transport modelling scales Model railway scales History of a scale type atlantic locomotive built by David Curwen, information on standard narrow gauge style locomotives built by Exmoor Steam Railway. The Ten and a Quarter Railway Society website
2.
Microarchitecture
–
A given ISA may be implemented with different microarchitectures, implementations may vary due to different goals of a given design or due to shifts in technology. Computer architecture is the combination of microarchitecture and instruction set, the ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address, the microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. These diagrams generally separate the datapath and the control path, the person designing a system usually draws the specific microarchitecture as a kind of data flow diagram. Like a block diagram, the diagram shows microarchitectural elements such as the arithmetic and logic unit. Typically, the diagram connects those elements with arrows, thick lines, very simple computers have a single data bus organization – they have a single three-state bus. The diagram of more complex computers usually shows multiple three-state buses, each microarchitectural element is in turn represented by a schematic describing the interconnections of logic gates used to implement it. Each logic gate is in turn represented by a circuit diagram describing the connections of the used to implement it in some particular logic family. Machines with different microarchitectures may have the instruction set architecture. In principle, a single microarchitecture could execute several different ISAs with only changes to the microcode. The pipelined datapath is the most commonly used design in microarchitecture today. This technique is used in most modern microprocessors, microcontrollers, the pipelined architecture allows multiple instructions to overlap in execution, much like an assembly line. The pipeline includes several different stages which are fundamental in microarchitecture designs, some of these stages include instruction fetch, instruction decode, execute, and write back. Some architectures include other stages such as memory access, the design of pipelines is one of the central microarchitectural tasks. Execution units are essential to microarchitecture. Execution units include arithmetic logic units, floating point units, load/store units, branch prediction and these units perform the operations or calculations of the processor. The choice of the number of units, their latency. The size, latency, throughput and connectivity of memories within the system are also microarchitectural decisions, system-level design decisions such as whether or not to include peripherals, such as memory controllers, can be considered part of the microarchitectural design process
3.
Central processing unit
–
The computer industry has used the term central processing unit at least since the early 1960s. The form, design and implementation of CPUs have changed over the course of their history, most modern CPUs are microprocessors, meaning they are contained on a single integrated circuit chip. An IC that contains a CPU may also contain memory, peripheral interfaces, some computers employ a multi-core processor, which is a single chip containing two or more CPUs called cores, in that context, one can speak of such single chips as sockets. Array processors or vector processors have multiple processors that operate in parallel, there also exists the concept of virtual CPUs which are an abstraction of dynamical aggregated computational resources. Early computers such as the ENIAC had to be rewired to perform different tasks. Since the term CPU is generally defined as a device for software execution, the idea of a stored-program computer was already present in the design of J. Presper Eckert and John William Mauchlys ENIAC, but was initially omitted so that it could be finished sooner. On June 30,1945, before ENIAC was made, mathematician John von Neumann distributed the paper entitled First Draft of a Report on the EDVAC and it was the outline of a stored-program computer that would eventually be completed in August 1949. EDVAC was designed to perform a number of instructions of various types. Significantly, the programs written for EDVAC were to be stored in high-speed computer memory rather than specified by the wiring of the computer. This overcame a severe limitation of ENIAC, which was the considerable time, with von Neumanns design, the program that EDVAC ran could be changed simply by changing the contents of the memory. Early CPUs were custom designs used as part of a larger, however, this method of designing custom CPUs for a particular application has largely given way to the development of multi-purpose processors produced in large quantities. This standardization began in the era of discrete transistor mainframes and minicomputers and has accelerated with the popularization of the integrated circuit. The IC has allowed increasingly complex CPUs to be designed and manufactured to tolerances on the order of nanometers, both the miniaturization and standardization of CPUs have increased the presence of digital devices in modern life far beyond the limited application of dedicated computing machines. Modern microprocessors appear in electronic devices ranging from automobiles to cellphones, the so-called Harvard architecture of the Harvard Mark I, which was completed before EDVAC, also utilized a stored-program design using punched paper tape rather than electronic memory. Relays and vacuum tubes were used as switching elements, a useful computer requires thousands or tens of thousands of switching devices. The overall speed of a system is dependent on the speed of the switches, tube computers like EDVAC tended to average eight hours between failures, whereas relay computers like the Harvard Mark I failed very rarely. In the end, tube-based CPUs became dominant because the significant speed advantages afforded generally outweighed the reliability problems, most of these early synchronous CPUs ran at low clock rates compared to modern microelectronic designs. Clock signal frequencies ranging from 100 kHz to 4 MHz were very common at this time, the design complexity of CPUs increased as various technologies facilitated building smaller and more reliable electronic devices
4.
Intel
–
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California that was founded by Gordon Moore and Robert Noyce. It is the worlds largest and highest valued semiconductor chip makers based on revenue, and is the inventor of the x86 series of microprocessors, Intel supplies processors for computer system manufacturers such as Apple, Lenovo, HP, and Dell. Intel Corporation was founded on July 18,1968, by semiconductor pioneers Robert Noyce and Gordon Moore, the companys name was conceived as portmanteau of the words integrated and electronics. The fact that intel is the term for intelligence information made the name appropriate. Intel was a developer of SRAM and DRAM memory chips. Although Intel created the worlds first commercial microprocessor chip in 1971, during the 1990s, Intel invested heavily in new microprocessor designs fostering the rapid growth of the computer industry. The Open Source Technology Center at Intel hosts PowerTOP and LatencyTOP, and supports other projects such as Wayland, Intel Array Building Blocks, and Threading Building Blocks. Client Computing Group – 55% of 2016 revenues – produces hardware components used in desktop, data Center Group – 29% of 2016 revenues – produces hardware components used in server, network, and storage platforms. Internet of Things Group – 5% of 2016 revenues – offers platforms designed for retail, transportation, industrial, buildings, non-Volatile Memory Solutions Group – 4% of 2016 revenues – manufactures NAND flash memory products primarily used in solid-state drives. Intel Security Group – 4% of 2016 revenues – produces software, particularly security, programmable Solutions Group – 3% of 2016 revenues – manufactures programmable semiconductors. In 2016, Dell accounted for 15% of Intels total revenues, Lenovo accounted for 13% of total revenues, in the 1980s, Intel was among the top ten sellers of semiconductors in the world. In 1991, Intel became the biggest chip maker by revenue and has held the position ever since, other top semiconductor companies include TSMC, Advanced Micro Devices, Samsung, Texas Instruments, Toshiba and STMicroelectronics. Competitors in PC chip sets include Advanced Micro Devices, VIA Technologies, Silicon Integrated Systems, however, the cross-licensing agreement is canceled in the event of an AMD bankruptcy or takeover. Some smaller competitors such as VIA Technologies produce low-power x86 processors for small factor computers, however, the advent of such mobile computing devices, in particular, smartphones, has in recent years led to a decline in PC sales. Since over 95% of the worlds smartphones currently use processors designed by ARM Holdings, ARM is also planning to make inroads into the PC and server market. Intel has been involved in disputes regarding violation of antitrust laws. Intel was founded in Mountain View, California in 1968 by Gordon E. Moore, a chemist, and Robert Noyce, arthur Rock helped them find investors, while Max Palevsky was on the board from an early stage. Moore and Noyce had left Fairchild Semiconductor to found Intel, Rock was not an employee, but he was an investor and was chairman of the board
5.
ARM architecture
–
ARM, originally Acorn RISC Machine, later Advanced RISC Machine, is a family of reduced instruction set computing architectures for computer processors, configured for various environments. It also designs cores that implement this instruction set and licenses these designs to a number of companies that incorporate those core designs into their own products, a RISC-based computer design approach means processors require fewer transistors than typical complex instruction set computing x86 processors in most personal computers. This approach reduces costs, heat and power use and these characteristics are desirable for light, portable, battery-powered devices—including smartphones, laptops and tablet computers, and other embedded systems. For supercomputers, which large amounts of electricity, ARM could also be a power-efficient solution. ARM Holdings periodically releases updates to architectures and core designs, some older cores can also provide hardware execution of Java bytecodes. The ARMv8-A architecture, announced in October 2011, adds support for a 64-bit address space, with over 100 billion ARM processors produced as of 2017, ARM is the most widely used instruction set architecture in terms of quantity produced. Currently, the widely used Cortex cores, older classic cores, the British computer manufacturer Acorn Computers first developed the Acorn RISC Machine architecture in the 1980s to use in its personal computers. Its first ARM-based products were coprocessor modules for the BBC Micro series of computers, according to Sophie Wilson, all the tested processors at that time performed about the same, with about a 4 Mbit/second bandwidth. After testing all available processors and finding them lacking, Acorn decided it needed a new architecture, inspired by white papers on the Berkeley RISC project, Acorn considered designing its own processor. Wilson developed the set, writing a simulation of the processor in BBC BASIC that ran on a BBC Micro with a 6502 second processor. This convinced Acorn engineers they were on the right track, Wilson approached Acorns CEO, Hermann Hauser, and requested more resources. Hauser gave his approval and assembled a team to implement Wilsons model in hardware. The official Acorn RISC Machine project started in October 1983 and they chose VLSI Technology as the silicon partner, as they were a source of ROMs and custom chips for Acorn. Wilson and Furber led the design and they implemented it with a similar efficiency ethos as the 6502. A key design goal was achieving low-latency input/output handling like the 6502, the 6502s memory access architecture had let developers produce fast machines without costly direct memory access hardware. The first samples of ARM silicon worked properly when first received and tested on 26 April 1985, Wilson subsequently rewrote BBC BASIC in ARM assembly language. The in-depth knowledge gained from designing the instruction set enabled the code to be very dense, the original aim of a principally ARM-based computer was achieved in 1987 with the release of the Acorn Archimedes. In 1992, Acorn once more won the Queens Award for Technology for the ARM, the ARM2 featured a 32-bit data bus, 26-bit address space and 27 32-bit registers
6.
Instruction set architecture
–
An ISA includes a specification of the set of opcodes, and the native commands implemented by a particular processor. An instruction set architecture is distinguished from a microarchitecture, which is the set of design techniques used, in a particular processor. Processors with different microarchitectures can share a common instruction set, for example, the Intel Pentium and the AMD Athlon implement nearly identical versions of the x86 instruction set, but have radically different internal designs. The concept of an architecture, distinct from the design of a machine, was developed by Fred Brooks at IBM during the design phase of System/360. Prior to NPL, the companys computer designers had been free to honor cost objectives not only by selecting technologies, the SPREAD compatibility objective, in contrast, postulated a single architecture for a series of five processors spanning a wide range of cost and performance. In addition, these virtual machines execute less frequently used code paths by interpretation, transmeta implemented the x86 instruction set atop VLIW processors in this fashion. A complex instruction set computer has many specialized instructions, some of which may only be used in practical programs. Theoretically important types are the instruction set computer and the one instruction set computer. Another variation is the very long instruction word where the processor receives many instructions encoded and retrieved in one instruction word, machine language is built up from discrete statements or instructions. Examples of operations common to many instruction sets include, Set a register to a constant value. Copy data from a location to a register, or vice versa. Used to store the contents of a register, result of a computation, often called load and store operations. Read and write data from hardware devices, add, subtract, multiply, or divide the values of two registers, placing the result in a register, possibly setting one or more condition codes in a status register. Increment, decrement in some ISAs, saving operand fetch in trivial cases, perform bitwise operations, e. g. taking the conjunction and disjunction of corresponding bits in a pair of registers, taking the negation of each bit in a register. Floating-point instructions for arithmetic on floating-point numbers, branch to another location in the program and execute instructions there. Conditionally branch to another if a certain condition holds. Call another block of code, while saving the location of the instruction as a point to return to. Load/store data to and from a coprocessor, or exchanging with CPU registers, processors may include complex instructions in their instruction set
7.
System on a chip
–
A system on a chip or system on chip is an integrated circuit that integrates all components of a computer or other electronic systems. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single substrate, SoCs are very common in the mobile computing market because of their low power-consumption. A typical application is in the area of embedded systems, the contrast with a microcontroller, SoC integrates microcontroller with advanced peripherals like graphics processing unit, Wi-Fi module, or coprocessor. As long as we remember that the SoC does not necessarily contain built-in memory, in general, we can distinguish three types of SoC. SoC built around a microcontroller, SoC built around a microprocessor, a separate category may be Programmable SoC, part of elements is not permanently defined and can be programmable in a manner analogous to the FPGA or CPLD. When it is not feasible to construct a SoC for a particular application, in large volumes, SoC is believed to be more cost-effective than SiP since it increases the yield of the fabrication and because its packaging is simpler. Another option, as seen for example in cell phones, is package on package stacking during board assembly. The SoC includes processors and numerous digital peripherals, and comes in a ball grid package with lower and upper connections. The lower balls connect to the board and various peripherals, with the balls in a ring holding the memory buses used to access NAND flash. Memory packages could come from multiple vendors, DMA controllers route data directly between external interfaces and memory, bypassing the processor core and thereby increasing the data throughput of the SoC. A SoC consists of both the hardware, described above, and the controlling the microcontroller, microprocessor or DSP cores, peripherals. The design flow for a SoC aims to develop hardware and software in parallel. Most SoCs are developed from pre-qualified hardware blocks for the elements described above. Of particular importance are the protocol stacks that drive industry-standard interfaces like USB, the hardware blocks are put together using CAD tools, the software modules are integrated using a software-development environment. Once the architecture of the SoC has been defined, any new elements are written in an abstract language termed RTL which defines the circuit behaviour. These elements are connected together in the same RTL language to create the full SoC design, chips are verified for logical correctness before being sent to foundry. This process is called functional verification and it accounts for a significant portion of the time, with the growing complexity of chips, hardware verification languages like SystemVerilog, SystemC, e, and OpenVera are being used. Bugs found in the stage are reported to the designer
8.
Marvell Technology Group
–
Marvell Technology Group, Limited, is a producer of storage, communications and consumer semiconductor products. The company was founded in 1995 and has approximately 7,000 employees, marvells U. S. operating headquarters is located in Santa Clara, California, and the company operates design centers in places including Canada, Europe, Israel, India, Singapore and China. Marvell is a manufacturer of semiconductors that ships more than one billion integrated circuits per year. Its market segments include the enterprise, cloud, automotive, industrial, Marvell was founded in 1995 by Sehat Sutardja, his wife Weili Dai, and brother Pantas Sutardja. The initial public offering on June 27,2000 raised $90 million, after quickly raising from $19 to over $63 per share, three days later it was $55.25. At the time, the five largest customers, Samsung Electronics, Hitachi, Seagate Technology, Fujitsu and Toshiba, the shares dropped sharply in December when insiders were allowed to sell. The company is headquartered in Hamilton, Bermuda. The US operations known as Marvell Semiconductor, Incorporated, are located in Silicon Valley, through the years, Marvell acquired smaller companies to enter new markets. Marvells first products were sold for computer storage devices. In March 2000, computer networking products for the Ethernet family were first shipped, in October 2002, the Yukon brand Gigabit Ethernet controller was announced. On June 27,2006, the sale of Intels XScale assets was announced, intel agreed to sell the XScale business to Marvell for an estimated USD600 million in cash and the assumption of unspecified liabilities. The acquisition was completed on November 9,2006, in 2009, Marvell announced that the SheevaPlug, a small, low-power, SoC-based ARM architecture computer, would be released with full schematics. Marvell supplied the Wi-Fi chip for the original Apple iPhone, Marvell Mobile Hotspot is an in-car Wi-Fi connectivity. The 2010 Audi A8 was the first automobile in the market to feature a factory-installed MMH, googles Chromecast products are powered by Marvell SoCs. Namely the Marvell ARMADA1500 Mini SoC for the Chromecast 1st gen, in 2012, Marvell was named one of Thomson Reuters top 100 global innovators. In 2006, the US Securities and Exchange Commission started an inquiry on the stock option grant practices. An investigation determined grant dates were chosen with the benefit of hindsight to make the more valuable. The press estimated that the founders and other executives had made $760 million in gains from the options, the SEC asked to interview the company general counsel Matthew Gloss, but Marvell claimed attorney-client privilege
9.
Arm Holdings
–
ARM Holdings plc is a British multinational semiconductor and software design company, owned by SoftBank Group. It is considered to be dominant for processors in mobile phones. The company is one of the best-known Silicon Fen companies, processors based on designs licensed from ARM, or designed by licensees of one of the ARM instruction set architectures, are used in all classes of computing devices. ARMs Mali line of processing units are used in laptops, in over 50% of Android tablets by market share. It is the third most popular GPU in mobile devices, ARMs main CPU competitors in servers include Intel and AMD. In mobile applications, Intels x86 Atom is a competitor, AMD also sells ARM based chips as well as x86, Imagination Technologies offers another RISC design for embedded systems. ARMs main GPU competitors include mobile GPUs from Imagination Technologies, Qualcomm and increasingly Nvidia, despite competing within GPUs, Qualcomm and Nvidia have combined their GPUs with an ARM licensed CPU. ARM had a listing on the London Stock Exchange and was a constituent of the FTSE100 Index. It has a listing on NASDAQ. However Japanese telecommunications company SoftBank Group made an offer for ARM on 18 July 2016, subject to approval by ARMs shareholders. The transaction was completed on 5 September 2016, the acronym ARM was first used in 1983 and originally stood for Acorn RISC Machine. Acorn Computers first RISC processor was used in the original Acorn Archimedes and was one of the first RISC processors used in small computers. However, when the company was incorporated in 1990, the acronym was changed to Advanced RISC Machines, at the time of the IPO in 1998, the company name was changed to ARM Holdings, often just called ARM like the processors. The company was founded in November 1990 as Advanced RISC Machines Ltd, the new company intended to further the development of the Acorn RISC Machine processor, which was originally used in the Acorn Archimedes and had been selected by Apple for their Newton project. Its first profitable year was 1993, the companys Silicon Valley and Tokyo offices were opened in 1994. ARM invested in Palmchip Corporation in 1997 to provide system on chip platforms, in 1998 the Company changed its name from Advanced RISC Machines Ltd to ARM Ltd. The Company was first listed on the London Stock Exchange and NASDAQ in 1998 and by February 1999, in 2010, ARM joined with IBM, Texas Instruments, Samsung, ST-Ericsson and Freescale Semiconductor in forming a non-profit open source engineering company, Linaro. ARM also acquired the team of PowerEscape
10.
Floating-point arithmetic
–
In computing, floating-point arithmetic is arithmetic using formulaic representation of real numbers as an approximation so as to support a trade-off between range and precision. A number is, in general, represented approximately to a number of significant digits and scaled using an exponent in some fixed base. For example,1.2345 =12345 ⏟ significand ×10 ⏟ base −4 ⏞ exponent, the term floating point refers to the fact that a numbers radix point can float, that is, it can be placed anywhere relative to the significant digits of the number. This position is indicated as the exponent component, and thus the floating-point representation can be thought of as a kind of scientific notation. The result of dynamic range is that the numbers that can be represented are not uniformly spaced. Over the years, a variety of floating-point representations have been used in computers, however, since the 1990s, the most commonly encountered representation is that defined by the IEEE754 Standard. A floating-point unit is a part of a computer system designed to carry out operations on floating point numbers. A number representation specifies some way of encoding a number, usually as a string of digits, there are several mechanisms by which strings of digits can represent numbers. In common mathematical notation, the string can be of any length. If the radix point is not specified, then the string implicitly represents an integer, in fixed-point systems, a position in the string is specified for the radix point. So a fixed-point scheme might be to use a string of 8 decimal digits with the point in the middle. The scaling factor, as a power of ten, is then indicated separately at the end of the number, floating-point representation is similar in concept to scientific notation. Logically, a floating-point number consists of, A signed digit string of a length in a given base. This digit string is referred to as the significand, mantissa, the length of the significand determines the precision to which numbers can be represented. The radix point position is assumed always to be somewhere within the significand—often just after or just before the most significant digit and this article generally follows the convention that the radix point is set just after the most significant digit. A signed integer exponent, which modifies the magnitude of the number, using base-10 as an example, the number 7005152853504700000♠152853.5047, which has ten decimal digits of precision, is represented as the significand 1528535047 together with 5 as the exponent. In storing such a number, the base need not be stored, since it will be the same for the range of supported numbers. Symbolically, this value is, s b p −1 × b e, where s is the significand, p is the precision, b is the base
11.
Instruction pipelining
–
Instruction pipelining is a technique that implements a form of parallelism called instruction-level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a clock rate. The basic instruction cycle is broken up into a series called a pipeline, the first step is always to fetch the instruction from memory, the final step is usually writing the results of the instruction to processor registers or to memory. Just as the goal of the line is to keep each assembler productive at all times. Pipelining lets the computers cycle time be the time of the slowest step, Pipelining increases instruction throughput by performing multiple operations at the same time, but does not reduce latency, the time needed to complete a single instruction. Indeed, pipelining may increase due to additional overhead from breaking the computation into separate steps. The term pipeline is an analogy to the fact there is fluid in each link of a pipeline. Central processing units are driven by a clock, each clock pulse need not do the same thing, rather, logic in the CPU directs successive pulses to different places to perform a useful sequence. As another example, reading an instruction out of a memory unit cannot be done at the time that an instruction writes a result to the same memory unit. The number of dependent steps varies with the machine architecture, for example, The 1956-1961 IBM Stretch project proposed the terms Fetch, Decode, and Execute that have become common. Many designs include pipelines as long as 7,10 and even 20 stages, the later Prescott and Cedar Mill Netburst cores from Intel, used in the latest Pentium 4 models and their Pentium D and Xeon derivatives, have a long 31-stage pipeline. The Xelerated X10q Network Processor has a more than a thousand stages long. The remaining stages are used to coordinate accesses to memory and on-chip function units, as the pipeline is made deeper, a given step can be implemented with simpler circuitry, which may let the processor clock run faster. Such pipelines may be called superpipelines, a processor is said to be fully pipelined if it can fetch an instruction on every cycle. Thus, if some instructions or conditions require delays that inhibit fetching new instructions, the model of sequential execution assumes that each instruction completes before the next one begins, this assumption is not true on a pipelined processor. A situation where the result is problematic is known as a hazard. Instruction 2 would be fetched at t2 and would be complete at t6, the first instruction might deposit the incremented number into R5 as its fifth step at t5. But the second instruction might get the number from R5 in its second step at time t3 and it seems that the first instruction would not have incremented the value by then
12.
StrongARM
–
The StrongARM is a family of computer microprocessors developed by Digital Equipment Corporation and manufactured in the late 1990s which implemented the ARM v4 instruction set architecture. It was later sold to Intel in 1997, who continued to manufacture it before replacing it with the XScale in the early 2000s, the StrongARM was a collaborative project between DEC and Advanced RISC Machines to create a faster ARM microprocessor. The StrongARM was designed to address the upper-end of the embedded market. Targets were devices such as personal digital assistants and set-top boxes. Traditionally, the division of DEC was located in Massachusetts. In order to access to the design talent in Silicon Valley, DEC opened a design center in Palo Alto. This design center was led by Dan Dobberpuhl and was the main site for the StrongARM project. Another design site which worked on the project was in Austin, Texas that was created by some ex-DEC designers returning from Apple Computer, the project was set up in 1995, and quickly delivered their first design, the SA-110. DEC agreed to sell StrongARM to Intel as part of a settlement in 1997. Intel used the StrongARM to replace their ailing line of RISC processors, the Austin design group spun off to become Alchemy Semiconductor, another start-up company designing MIPS SoCs for the hand-held market. A new StrongARM core was developed by Intel and introduced in 2000 as the XScale, the SA-110 was the first microprocessor in the StrongARM family. The first versions, operating at 100,160, and 200 MHz, were announced on 5 February 1996, when announced, samples of these versions were available, with volume production slated for mid-1996. Faster 166 and 233 MHz versions were announced on 12 September 1996, samples of these versions were available at announcement, with volume production slated for December 1996. Throughout 1996, the SA-110 was the highest performing microprocessor for portable devices, towards the end of 1996 it was a leading CPU for internet/intranet appliances and thin client systems. The SA-110s first design win was the Apple MessagePad 2000 and it was also used in a number of products including the Acorn Computers Risc PC and Eidos Optima video editing system. The SA-110s lead designers were Daniel W. Dobberpuhl, Gregory W. Hoeppner, Liam Madden, the SA-110 had a simple microarchitecture. It was a design that executed instructions in-order with a five-stage classic RISC pipeline. The microprocessor was partitioned into several blocks, the IBOX, EBOX, IMMU, DMMU, BIU, WB, the IBOX contained hardware that operated in the first two stages of the pipeline such as the program counter
13.
Microprocessor
–
A microprocessor is a computer processor which incorporates the functions of a computers central processing unit on a single integrated circuit, or at most a few integrated circuits. Microprocessors contain both combinational logic and sequential digital logic, Microprocessors operate on numbers and symbols represented in the binary numeral system. The integration of a whole CPU onto a chip or on a few chips greatly reduced the cost of processing power. Integrated circuit processors are produced in numbers by highly automated processes resulting in a low per unit cost. Single-chip processors increase reliability as there are many electrical connections to fail. As microprocessor designs get better, the cost of manufacturing a chip generally stays the same, before microprocessors, small computers had been built using racks of circuit boards with many medium- and small-scale integrated circuits. Microprocessors combined this into one or a few large-scale ICs, the internal arrangement of a microprocessor varies depending on the age of the design and the intended purposes of the microprocessor. Advancing technology makes more complex and powerful chips feasible to manufacture, a minimal hypothetical microprocessor might only include an arithmetic logic unit and a control logic section. The ALU performs operations such as addition, subtraction, and operations such as AND or OR, each operation of the ALU sets one or more flags in a status register, which indicate the results of the last operation. The control logic retrieves instruction codes from memory and initiates the sequence of operations required for the ALU to carry out the instruction, a single operation code might affect many individual data paths, registers, and other elements of the processor. As integrated circuit technology advanced, it was feasible to manufacture more and more complex processors on a single chip, the size of data objects became larger, allowing more transistors on a chip allowed word sizes to increase from 4- and 8-bit words up to todays 64-bit words. Additional features were added to the architecture, more on-chip registers sped up programs. Floating-point arithmetic, for example, was not available on 8-bit microprocessors. Integration of the point unit first as a separate integrated circuit and then as part of the same microprocessor chip. Occasionally, physical limitations of integrated circuits made such practices as a bit slice approach necessary, instead of processing all of a long word on one integrated circuit, multiple circuits in parallel processed subsets of each data word. With the ability to put large numbers of transistors on one chip and this CPU cache has the advantage of faster access than off-chip memory, and increases the processing speed of the system for many applications. Processor clock frequency has increased more rapidly than external memory speed, except in the recent past, a microprocessor is a general purpose system. Several specialized processing devices have followed from the technology, A digital signal processor is specialized for signal processing, graphics processing units are processors designed primarily for realtime rendering of 3D images
14.
Microcontroller
–
A microcontroller is a small computer on a single integrated circuit. In modern terminology, it is a system on a chip or SoC, a microcontroller contains one or more CPUs along with memory and programmable input/output peripherals. Program memory in the form of Ferroelectric RAM, NOR flash or OTP ROM is also included on chip. Microcontrollers are designed for embedded applications, in contrast to the used in personal computers or other general purpose applications consisting of various discrete chips. Mixed signal microcontrollers are common, integrating analog components needed to control non-digital electronic systems, some microcontrollers may use four-bit words and operate at frequencies as low as 4 kHz, for low power consumption. Other microcontrollers may serve performance-critical roles, where they may need to act more like a signal processor, with higher clock speeds. The first microprocessor was the 4-bit Intel 4004 released in 1971, with the Intel 8008, however, both processors required external chips to implement a working system, raising total system cost, and making it impossible to economically computerize appliances. One book credits TI engineers Gary Boone and Michael Cochran with the creation of the first microcontroller in 1971. The result of their work was the TMS1000, which became available in 1974. It combined read-only memory, read/write memory, processor and clock on one chip and was targeted at embedded systems and it combined RAM and ROM on the same chip. This chip would find its way into one billion PC keyboards. At that time Intels President, Luke J. Valenter, stated that the microcontroller was one of the most successful in the companys history, most microcontrollers at this time had concurrent variants. One had an erasable EPROM program memory, with a transparent quartz window in the lid of the package to allow it to be erased by exposure to ultraviolet light, often used for prototyping. The PROM was of type of memory as the EPROM. The erasable versions required ceramic packages with quartz windows, making them more expensive than the OTP versions. The same year, Atmel introduced the first microcontroller using Flash memory, other companies rapidly followed suit, with both memory types. Cost has plummeted over time, with the cheapest 8-bit microcontrollers being available for under 0.25 USD in quantity in 2009, nowadays microcontrollers are cheap and readily available for hobbyists, with large online communities around certain processors. In the future, MRAM could potentially be used in microcontrollers as it has infinite endurance, in 2002, about 55% of all CPUs sold in the world were 8-bit microcontrollers and microprocessors
15.
Digital Equipment Corporation
–
Digital Equipment Corporation, also known as DEC and using the trademark Digital, was a major American company in the computer industry from the 1950s to the 1990s. DEC was a vendor of computer systems, including computers, software. Their PDP and successor VAX products were the most successful of all minicomputers in terms of sales, DEC was acquired in June 1998 by Compaq, in what was at that time the largest merger in the history of the computer industry. At the time, Compaq was focused on the market and had recently purchased several other large vendors. DEC was a major player overseas where Compaq had less presence, however, Compaq had little idea what to do with its acquisitions, and soon found itself in financial difficulty of its own. The company subsequently merged with Hewlett-Packard in May 2002, as of 2007 some of DECs product lines were still produced under the HP name. From 1957 until 1992, DECs headquarters were located in a wool mill in Maynard. DEC was acquired in June 1998 by Compaq, which merged with Hewlett-Packard in May 2002. Some parts of DEC, notably the business and the Hudson. Initially focusing on the end of the computer market allowed DEC to grow without its potential competitors making serious efforts to compete with them. Their PDP series of machines became popular in the 1960s, especially the PDP-8, looking to simplify and update their line, DEC replaced most of their smaller machines with the PDP-11 in 1970, eventually selling over 600,000 units and cementing DECs position in the industry. Originally designed as a follow-on to the PDP-11, DECs VAX-11 series was the first widely used 32-bit minicomputer and these systems were able to compete in many roles with larger mainframe computers, such as the IBM System/370. The VAX was a best-seller, with over 400,000 sold, at its peak, DEC was the second largest employer in Massachusetts, second only to the Massachusetts State Government. The rapid rise of the business microcomputer in the late 1980s, DECs last major attempt to find a space in the rapidly changing market was the DEC Alpha 64-bit RISC instruction set architecture. DEC initially started work on Alpha as a way to re-implement their VAX series, DEC was acquired in June 1998 by Compaq, in what was at that time the largest merger in the history of the computer industry. At the time, Compaq was focused on the market and had recently purchased several other large vendors. DEC was a major player overseas where Compaq had less presence, however, Compaq had little idea what to do with its acquisitions, and soon found itself in financial difficulty of its own. The company subsequently merged with Hewlett-Packard in May 2002, as of 2007 some of DECs product lines were still produced under the HP name
16.
Reduced instruction set computer
–
A computer based on this strategy is a reduced instruction set computer, also called RISC. The opposing architecture is called complex instruction set computing, although a number of systems from the 1960s and 70s have been identified as being forerunners of RISC, the modern version of the design dates to the 1980s. In particular, two projects at Stanford University and University of California, Berkeley are most associated with the popularization of this concept. Stanfords design would go on to be commercialized as the successful MIPS architecture, while Berkeleys RISC gave its name to the entire concept, another success from this era were IBMs efforts that eventually led to the Power Architecture. RISC families include DEC Alpha, AMD Am29000, ARC, ARM, Atmel AVR, Blackfin, Intel i860 and i960, MIPS, Motorola 88000, PA-RISC, Power, RISC-V, SuperH, and SPARC. In the 21st century, the use of ARM architecture processors in smart phones and tablet computers such as the iPad, a number of systems, going back to the 1960s, have been credited as the first RISC architecture, partly based on their use of load/store approach. The term RISC was coined by David Patterson of the Berkeley RISC project, michael J. Flynn views the first RISC system as the IBM801 design which began in 1975 by John Cocke, and completed in 1980. The 801 was eventually produced in a form as the ROMP in 1981. As the name implies, this CPU was designed for tasks, and was also used in the IBM RT-PC in 1986. But the 801 inspired several research projects, including new ones at IBM that would lead to the IBM POWER instruction set architecture. The most public RISC designs, however, were the results of university research programs run with funding from the DARPA VLSI Program, the VLSI Program, practically unknown today, led to a huge number of advances in chip design, fabrication, and even computer graphics. The Berkeley RISC project started in 1980 under the direction of David Patterson, Berkeley RISC was based on gaining performance through the use of pipelining and an aggressive use of a technique known as register windowing. In a traditional CPU, one has a number of registers. In a CPU with register windows, there are a number of registers, e. g.128. The Berkeley RISC project delivered the RISC-I processor in 1982, consisting of only 44,420 transistors RISC-I had only 32 instructions, and yet completely outperformed any other single-chip design. They followed this up with the 40,760 transistor,39 instruction RISC-II in 1983, which ran over three times as fast as RISC-I. The MIPS architecture grew out of a course by John L. Hennessy at Stanford University in 1981, resulted in a functioning system in 1983. The MIPS approach emphasized an aggressive clock cycle and the use of the pipeline, the MIPS system was followed by the MIPS-X and in 1984 Hennessy and his colleagues formed MIPS Computer Systems
17.
Intel i860
–
The Intel i860 was a RISC microprocessor design introduced by Intel in 1989. It was one of Intels first attempts at an entirely new and it was released with considerable fanfare, slightly obscuring the earlier Intel i960, which was successful in some niches of embedded systems, and which many considered to be a better design. The i860 never achieved success and the project was terminated in the mid-1990s. The first implementation of the architecture was the i860 XR microprocessor. A process shrink for the XP bumped it to 40 and 50 MHz, both microprocessors supported the same instruction set for application programs. The i860 combined a number of features that were unique at the time, most notably its very long instruction word architecture and powerful support for high-speed floating point operations. The design mounted a 32-bit ALU Core along with a 64-bit FPU that was built in three parts, an adder, a multiplier, and a graphics processor. The system had separate pipelines for the ALU, floating point adder and multiplier, all of the buses were at least 64 bits wide. The internal memory bus to the cache, for instance, was 128 bits wide, both units had thirty-two 32-bit registers, but the FPU used its set as sixteen 64-bit registers. Instructions for the ALU were fetched two at a time to use the external bus. Intel referred to the design as the i860 64-Bit Microprocessor, Intel i860 instructions acted on data sizes from 8-bit through 128-bit. The graphics unit was unique for the era and it was essentially a 64-bit integer unit using the FPU registers as eight 128-bit registers. It supported a number of commands for SIMD-like instructions in addition to basic 64-bit integer math, experience with the i860 influenced the MMX functionality later added to Intels Pentium processors. In traditional architectures these duties were handled at runtime by a scheduler on the CPU itself, the i860 was an attempt to avoid this entirely by moving this duty off-chip into the compiler. This allowed the i860 to devote more room to functional units, on paper, performance was impressive for a single-chip solution, however, real-world performance was anything but. One problem, perhaps unrecognized at the time, was that runtime code paths are difficult to predict, meaning that it becomes exceedingly difficult to order instructions properly at compile time. For instance, an instruction to add two numbers will take longer if the data are not in the cache, yet there is no way for the programmer to know if they are or not. If an incorrect guess is made, the pipeline will stall
18.
Intel i960
–
In spite of its success, Intel dropped i960 marketing in the late 1990s as a side effect of a settlement with DEC in which Intel received the rights to produce the StrongARM CPU. The processor continues to be used in a few military applications, the i960 design was started as a response to the failure of Intels iAPX432 design of the early 1980s. The iAPX432 was intended to directly support high-level languages that supported tagged, protected, garbage-collected memory — such as Ada, because of its instruction-set complexity, its multi-chip implementation, and design flaws, the iAPX432 was very slow in comparison to other processors of its time. In 1984 Intel and Siemens started a joint project, ultimately called BiiN, many of the original i432 team members joined this project, though a new lead architect, Glenford Myers, was brought in from IBM. The intended market for the BiiN systems were high-reliability computer users such as banks, industrial systems, Intels major contribution to the BiiN system was a new processor design, influenced by the protected-memory concepts from the i432. The new design included a number of features to improve performance and avoid problems that had led to the downfall of the i432, the BiiN effort eventually failed, due to market forces, and the 960MX was left without a use. Myers attempted to save the design by outlining several subsets of the capability architecture created for the BiiN system. Competition within and outside of Intel came not only from the i386 camp, Myers was unsuccessful at convincing Intel management to support the i960 as a general-purpose or Unix processor, but the chip found a ready market in early high-performance 32-bit embedded systems. The lead architect of i960 was superscalarity specialist Fred Pollack who was also the engineer of Intel iAPX432. The competing Stanford University design, commercialized as MIPS, did not use this system, relying on the compiler to generate optimal subroutine call, in common with most 32-bit designs, the i960 has a flat 32-bit memory space, with no memory segmentation. The i960 architecture also anticipated a superscalar implementation, with instructions being simultaneously dispatched to more than one unit within the processor, the full i960MX was never released for the non-military market, but the otherwise identical i960MC was used in high-end embedded applications. A version of the RISC core without memory management or an FPU became the i960KA, the versions were, however, all identical internally — only the labeling was different. This meant the CPUs were much larger than necessary for the actually supported feature sets, the i960KA became successful as a low-cost 32-bit processor for the laser-printer market, as well as for early graphics terminals and other embedded applications. Its success paid for future generations, which removed the complex memory sub-system, the i960CA, first announced in July 1989, was the first pure RISC implementation of the i960 architecture. It featured a newly designed superscalar RISC core and added an unusual addressable on-chip cache, the i960CA is widely considered to have been the first single-chip superscalar RISC implementation. The first versions released ran at 33 MHz, and Intel promoted the chip as capable of 66 MIPS, the i960CA microarchitecture was designed in 1987–1988 and formally announced on September 12,1989. Later, in May 1992, the i960CF included larger instruction cache and added 1 KB of data cache, the 80960Jx is a processor for embedded applications. It features 32-bit multiplexed address/data bus, instruction and data cache, 1K on-chip RAM, interrupt controller, the 80960Jx’s testability features included ONCE mode and boundary scan
19.
CPU cache
–
Cache memory makes use of the fast technology SRAM, against a slower MM DRAM, connected directly to the processor. The term cache is derived from the French and refers to a place one can hide something. This term has many meanings depending on the context, examples are, disk cache, TLB, branch prediction cache, branch history table, Branch Address Cache, trace cache, that are physical memories. Others are handled by the software, to store data in reserved MM space. Note – CPU cache is a term and rarely or wrongly used in both literature and in industrial environment. For instance, in the US patents documents relating to the cache, the term CPU cache is used in less of 2% of the documents against to the Cache Memory and the Memory Cache. Cache general definition The Cache is a memory that stores data, in silent mode to upper level of utilization. In MM read operation, the controller first of all checks if the data is stored in cache. In case of match the data is fastly and directly supplied from the cache to the processor without involving the MM.3, else the data is read from MM. A cache stores only a subset of MM data – the most recent-used MRU, Data read from MM are temporary stored in cache. If the processor requires the data, this is supplied by the cache. The cache is effective because short instruction loops and routines are a common program structure, spatial locality - If a data is referenced, it is very likely that nearby data will be accessed soon. Instructions and data are transferred from MM to the cache in fixed blocks, Cache line size is in the range of 4 to 512 bytes so that more than one processing data is stored in each cache entry. After a first MM access, all cache line data are available in cache, next instruction usually comes from the next memory location. Data is usually structured and data in these structures normally are stored in memory locations. Large lines size increase the spatial locality but increase also the number of invalidated data in case of line replacement, Cache efficiency is measured in terms of Hit Rate. Hit Rate represents the percentage of Hits compared to the number of cache accesses. The opposite of Hit is called Miss The cache efficiency depends by several elements, cache size, line size, type and cache architecture, a good figure of the cache efficiency, for business applications, may be in the range of 80-95 % of hit
20.
Multi-core processor
–
A multi-core processor is a single computing component with two or more independent actual processing units, which are units that read and execute program instructions. The instructions are ordinary CPU instructions, but the multiple cores can run multiple instructions at the same time, manufacturers typically integrate the cores onto a single integrated circuit die, or onto multiple dies in a single chip package. A multi-core processor implements multiprocessing in a physical package. Designers may couple cores in a multi-core device tightly or loosely, for example, cores may or may not share caches, and they may implement message passing or shared-memory inter-core communication methods. Common network topologies to interconnect cores include bus, ring, two-dimensional mesh, homogeneous multi-core systems include only identical cores, heterogeneous multi-core systems have cores that are not identical. Just as with single-processor systems, cores in multi-core systems may implement architectures such as VLIW, superscalar, Multi-core processors are widely used across many application domains, including general-purpose, embedded, network, digital signal processing, and graphics. The improvement in performance gained by the use of a multi-core processor depends very much on the algorithms used. In particular, possible gains are limited by the fraction of the software that can run in parallel simultaneously on multiple cores, most applications, however, are not accelerated so much unless programmers invest a prohibitive amount of effort in re-factoring the whole problem. The parallelization of software is a significant ongoing topic of research, the terms multi-core and dual-core most commonly refer to some sort of central processing unit, but are sometimes also applied to digital signal processors and system on a chip. This article uses the terms multi-core and dual-core for CPUs manufactured on the integrated circuit. In contrast to systems, the term multi-CPU refers to multiple physically separate processing-units. The terms many-core and massively multi-core are sometimes used to describe multi-core architectures with a high number of cores. Some systems use many soft microprocessor cores placed on a single FPGA, each core can be considered a semiconductor intellectual property core as well as a CPU core. While manufacturing technology improves, reducing the size of individual gates and these physical limitations can cause significant heat dissipation and data synchronization problems. Various other methods are used to improve CPU performance, some instruction-level parallelism methods such as superscalar pipelining are suitable for many applications, but are inefficient for others that contain difficult-to-predict code. Many applications are better suited to thread-level parallelism methods, and multiple independent CPUs are commonly used to increase a systems overall TLP, a combination of increased available space and the demand for increased TLP led to the development of multi-core CPUs. Several business motives drive the development of multi-core architectures, for decades, it was possible to improve performance of a CPU by shrinking the area of the integrated circuit, which reduced the cost per device on the IC. Alternatively, for the circuit area, more transistors could be used in the design
21.
Conventional PCI
–
Conventional PCI, often shortened to PCI, is a local computer bus for attaching hardware devices in a computer. PCI is the initialism for Peripheral Component Interconnect and is part of the PCI Local Bus standard, the PCI bus supports the functions found on a processor bus but in a standardized format that is independent of any particular processors native bus. Devices connected to the PCI bus appear to a bus master to be connected directly to its own bus and are assigned addresses in the address space. It is a bus, synchronous to a single bus clock. Attached devices can take either the form of an integrated circuit fitted onto the motherboard itself or a card that fits into a slot. The PCI Local Bus was first implemented in IBM PC compatibles and it has subsequently been adopted for other computer types. Typical PCI cards used in PCs include, network cards, sound cards, modems, extra ports such as USB or serial, TV tuner cards, PCI video cards replaced ISA and VESA cards until growing bandwidth requirements outgrew the capabilities of PCI. The preferred interface for video cards then became AGP, itself a superset of conventional PCI and these have one locating notch in the card. Version 2.0 of the PCI standard introduced 3.3 V slots, universal cards, which can operate on either voltage, have two notches. Version 2.1 of the PCI standard introduced optional 66 MHz operation, a server-oriented variant of conventional PCI, called PCI-X operated at frequencies up to 133 MHz for PCI-X1.0 and up to 533 MHz for PCI-X2.0. An internal connector for laptop cards, called Mini PCI, was introduced in version 2.2 of the PCI specification, the PCI bus was also adopted for an external laptop connector standard – the CardBus. The first PCI specification was developed by Intel, but subsequent development of the standard became the responsibility of the PCI Special Interest Group, Conventional PCIs heyday in the desktop computer market was approximately 1995–2005. PCI and PCI-X have become obsolete for most purposes, however, they are common on modern desktops for the purposes of backwards compatibility. Many kinds of devices available on PCI expansion cards are now commonly integrated onto motherboards or available in USB. Work on PCI began at Intels Architecture Development Lab c. 1990, a team of Intel engineers defined the architecture and developed a proof of concept chipset and platform partnering with teams in the companys desktop PC systems and core logic product organizations. PCI was immediately put to use in servers, replacing MCA, in mainstream PCs, PCI was slower to replace VESA Local Bus, and did not gain significant market penetration until late 1994 in second-generation Pentium PCs. By 1996, VLB was all but extinct, and manufacturers had adopted PCI even for 486 computers, EISA continued to be used alongside PCI through 2000. Apple Computer adopted PCI for professional Power Macintosh computers in mid-1995, the 64-bit version of plain PCI remained rare in practice though, although it was used for example by all G3 and G4 Power Macintosh computers
22.
Hertz
–
The hertz is the unit of frequency in the International System of Units and is defined as one cycle per second. It is named for Heinrich Rudolf Hertz, the first person to provide proof of the existence of electromagnetic waves. Hertz are commonly expressed in SI multiples kilohertz, megahertz, gigahertz, kilo means thousand, mega meaning million, giga meaning billion and tera for trillion. Some of the units most common uses are in the description of waves and musical tones, particularly those used in radio-. It is also used to describe the speeds at which computers, the hertz is equivalent to cycles per second, i. e. 1/second or s −1. In English, hertz is also used as the plural form, as an SI unit, Hz can be prefixed, commonly used multiples are kHz, MHz, GHz and THz. One hertz simply means one cycle per second,100 Hz means one hundred cycles per second, and so on. The unit may be applied to any periodic event—for example, a clock might be said to tick at 1 Hz, the rate of aperiodic or stochastic events occur is expressed in reciprocal second or inverse second in general or, the specific case of radioactive decay, becquerels. Whereas 1 Hz is 1 cycle per second,1 Bq is 1 aperiodic radionuclide event per second, the conversion between a frequency f measured in hertz and an angular velocity ω measured in radians per second is ω =2 π f and f = ω2 π. This SI unit is named after Heinrich Hertz, as with every International System of Units unit named for a person, the first letter of its symbol is upper case. Note that degree Celsius conforms to this rule because the d is lowercase. — Based on The International System of Units, the hertz is named after the German physicist Heinrich Hertz, who made important scientific contributions to the study of electromagnetism. The name was established by the International Electrotechnical Commission in 1930, the term cycles per second was largely replaced by hertz by the 1970s. One hobby magazine, Electronics Illustrated, declared their intention to stick with the traditional kc. Mc. etc. units, sound is a traveling longitudinal wave which is an oscillation of pressure. Humans perceive frequency of waves as pitch. Each musical note corresponds to a frequency which can be measured in hertz. An infants ear is able to perceive frequencies ranging from 20 Hz to 20,000 Hz, the range of ultrasound, infrasound and other physical vibrations such as molecular and atomic vibrations extends from a few femtoHz into the terahertz range and beyond. Electromagnetic radiation is described by its frequency—the number of oscillations of the perpendicular electric and magnetic fields per second—expressed in hertz. Radio frequency radiation is measured in kilohertz, megahertz, or gigahertz
23.
Cache (computing)
–
A cache hit occurs when the requested data can be found in a cache, while a cache miss occurs when it cannot. To be cost-effective and to enable efficient use of data, caches must be relatively small, nevertheless, caches have proven themselves in many areas of computing because access patterns in typical computer applications exhibit the locality of reference. There is an inherent trade-off between size and speed but also a tradeoff between expensive, premium technologies vs cheaper, easily mass-produced commodities and this is mitigated by reading in large chunks, in the hope that subsequent reads will be from nearby locations. Prediction or explicit prefetching might also guess where future reads will come from and make requests ahead of time, the use of a cache also allows for higher throughput from the underlying resource, by assembling multiple fine grain transfers into larger, more efficient requests. In the case of DRAM, this might be served by a wider bus, reading larger chunks reduces the fraction of bandwidth required for transmitting address information. Hardware implements cache as a block of memory for storage of data likely to be used again. Central processing units and hard disk drives use a cache, as do web browsers. A cache is made up of a pool of entries, each entry has associated data, which is a copy of the same data in some backing store. Each entry also has a tag, which specifies the identity of the data in the store of which the entry is a copy. When the cache client needs to access data presumed to exist in the backing store, if an entry can be found with a tag matching that of the desired data, the data in the entry is used instead. This situation is known as a cache hit, so, for example, a web browser program might check its local cache on disk to see if it has a local copy of the contents of a web page at a particular URL. In this example, the URL is the tag, and the contents of the web page is the data, the percentage of accesses that result in cache hits is known as the hit rate or hit ratio of the cache. The alternative situation, when the cache is consulted and found not to data with the desired tag, has become known as a cache miss. The previously uncached data fetched from the store during miss handling is usually copied into the cache. During a cache miss, the CPU usually ejects some other entry in order to make room for the previously uncached data, the heuristic used to select the entry to eject is known as the replacement policy. One popular replacement policy, least recently used, replaces the least recently used entry, more efficient caches compute use frequency against the size of the stored contents, as well as the latencies and throughputs for both the cache and the backing store. This works well for larger amounts of data, longer latencies and slower throughputs, such as experienced with a drive and the Internet. When a system writes data to cache, it must at some point write that data to the store as well
24.
MMX (instruction set)
–
MMX is a single instruction, multiple data instruction set designed by Intel, introduced in 1997 with its P5-based Pentium line of microprocessors, designated as Pentium with MMX Technology. It developed out of a similar unit introduced on the Intel i860, MMX is a processor supplementary capability that is supported on recent IA-32 processors by Intel and other vendors. MMX has subsequently been extended by several programs by Intel and others, 3DNow. AMD, during one of its numerous court battles with Intel, produced marketing material from Intel indicating that MMX stood for Matrix Math Extensions. Since an initialism cannot be trademarked, this was an attempt to invalidate Intels trademark, in 1995, Intel filed suit against AMD and Cyrix Corp. for misuse of its trademark MMX. AMD and Intel settled, with AMD acknowledging MMX as a trademark owned by Intel, and with Intel granting AMD rights to use the MMX trademark as a technology name, MMX defines eight registers, called MM0 through MM7, and operations that operate on them. On the other hand, the arithmetic operations in MMX could significantly speed up some digital signal processing applications. Unlike the x87 registers, which behave like a stack, the MMX registers are each directly addressable, to maximize performance, programmers often used the processor exclusively in one mode or the other, deferring the relatively slow switch between them as long as possible. Each 64-bit MMX register corresponds to the part of an 80-bit x87 register. The upper 16 bits of the x87 registers thus go unused in MMX, and this can be used by applications to decide whether a particular registers content is intended as floating point or SIMD data. Software support for MMX was slow in coming, Intels C Compiler and related development tools obtained intrinsics for invoking MMX instructions and Intel released libraries of common vectorized algorithms using MMX. AMD, a competing x86 microprocessor vendor, enhanced Intels MMX with their own 3DNow, 3DNow is best known for adding single-precision floating-point support to the SIMD instruction-set, among other integer and more general enhancements. Following MMX, Intels next major x86 extension was the SSE, SSE addressed the core shortcomings of MMX by creating a new 128-bit wide register file and new SIMD instructions for it. SSE focused exclusively on single-precision floating-point operations, integer SIMD operations were performed using the MMX register. However, the new XMM register-file allowed SSE SIMD-operations to be mixed with either MMX or x87 FPU ops. SSE2, introduced with the Pentium 4, further extended the x86 SIMD instruction set with integer, sSE2 also allowed the MMX opcodes to use XMM register operands, but ended this support with SSE4. However, since support for any SSE revision also implies support for MMX. It provides arithmetic and logic operations on 64-bit integer numbers, the extension contains 16 data registers of 64-bits and eight control registers of 32-bits. All registers are accessed through standard ARM architecture coprocessor mapping mechanism, iwMMXt occupies coprocessors 0 and 1 space, and some of its opcodes clash with the opcodes of the earlier floating-point extension, FPA
25.
SIMD
–
Single instruction, multiple data, is a class of parallel computers in Flynns taxonomy. It describes computers with multiple processing elements that perform the operation on multiple data points simultaneously. Thus, such machines exploit data level parallelism, but not concurrency, there are simultaneous computations, SIMD is particularly applicable to common tasks like adjusting the contrast in a digital image or adjusting the volume of digital audio. Most modern CPU designs include SIMD instructions in order to improve the performance of multimedia use, vector processing was especially popularized by Cray in the 1970s and 1980s. The first era of modern SIMD machines was characterized by massively parallel processing-style supercomputers such as the Thinking Machines CM-1 and these machines had many limited-functionality processors that would work in parallel. Supercomputing moved away from the SIMD approach when inexpensive scalar MIMD approaches based on commodity processors such as the Intel i860 XP became more powerful, the current era of SIMD processors grew out of the desktop-computer market rather than the supercomputer market. Sun Microsystems introduced SIMD integer instructions in its VIS instruction set extensions in 1995, MIPS followed suit with their similar MDMX system. The first widely deployed desktop SIMD was with Intels MMX extensions to the x86 architecture in 1996 and this sparked the introduction of the much more powerful AltiVec system in the Motorola PowerPCs and IBMs POWER systems. Intel responded in 1999 by introducing the all-new SSE system, since then, there have been several extensions to the SIMD instruction sets for both architectures. A modern supercomputer is almost always a cluster of MIMD machines, a modern desktop computer is often a multiprocessor MIMD machine where each processor can execute short-vector SIMD instructions. An application that may take advantage of SIMD is one where the value is being added to a large number of data points. One example would be changing the brightness of an image, each pixel of an image consists of three values for the brightness of the red, green and blue portions of the color. To change the brightness, the R, G and B values are read from memory, a value is added to them, with a SIMD processor there are two improvements to this process. For one the data is understood to be in blocks, instead of a series of instructions saying retrieve this pixel, now retrieve the next pixel, a SIMD processor will have a single instruction that effectively says retrieve n pixels. For a variety of reasons, this can take less time than retrieving each pixel individually. Another advantage is that the instruction operates on all loaded data in a single operation. In other words, if the SIMD system works by loading up eight points at once. Not all algorithms can be vectorized easily, note, Batch-pipeline systems are most advantageous for cache control when implemented with SIMD intrinsics, but they are not exclusive to SIMD features
26.
Streaming SIMD Extensions
–
SSE contains 70 new instructions, most of which work on single precision floating point data. SIMD instructions can greatly increase performance when exactly the same operations are to be performed on multiple data objects, typical applications are digital signal processing and graphics processing. Intels first IA-32 SIMD effort was the MMX instruction set, MMX had two main problems, it re-used existing floating point registers making the CPU unable to work on both floating point and SIMD data at the same time, and it only worked on integers. SSE floating point instructions operate on a new independent register set, SSE was subsequently expanded by Intel to SSE2, SSE3, SSSE3, and SSE4. Because it supports floating point math, it had a wider application than MMX, the addition of integer support in SSE2 made MMX largely redundant, though further performance increases can be attained in some situations by using MMX in parallel with SSE operations. SSE was originally called Katmai New Instructions, Katmai being the name for the first Pentium III core revision. During the Katmai project Intel sought to distinguish it from their product line. It was later renamed Intel Streaming SIMD Extensions, then SSE, AMD eventually added support for SSE instructions, starting with its Athlon XP and Duron processors. SSE originally added eight new 128-bit registers known as XMM0 through XMM7, the AMD64 extensions from AMD added a further eight registers XMM8 through XMM15, and this extension is duplicated in the Intel 64 architecture. There is also a new 32-bit control/status register, MXCSR, the registers XMM8 through XMM15 are accessible only in 64-bit operating mode. This means that the OS must know how to use the FXSAVE and FXRSTOR instructions and this support was quickly added to all major IA-32 operating systems. The first CPU to support SSE, the Pentium III, shared execution resources between SSE and the FPU, while a compiled application can interleave FPU and SSE instructions side-by-side, the Pentium III will not issue an FPU and an SSE instruction in the same clock cycle. SSE introduced both scalar and packed floating point instructions, consider an operation like vector addition, which is used very often in computer graphics applications. To add two single precision, four-component vectors together using x86 requires four floating-point addition instructions and this corresponds to four x86 FADD instructions in the object code. On the other hand, as the following shows, a single 128-bit packed-add instruction can replace the four scalar addition instructions. SSE2, Willamette New Instructions, introduced with the Pentium 4, is an enhancement to SSE. SSE2 adds two major features, double-precision floating point for all SSE operations, and MMX integer operations on 128-bit XMM registers, in the original SSE instruction set, conversion to and from integers placed the integer data in the 64-bit MMX registers. SSE2 enables the programmer to perform SIMD math on any data type entirely with the XMM vector-register file and it offers an orthogonal set of instructions for dealing with common data types
27.
Byte
–
The byte is a unit of digital information that most commonly consists of eight bits. Historically, the byte was the number of used to encode a single character of text in a computer. The size of the byte has historically been hardware dependent and no standards existed that mandated the size. The de-facto standard of eight bits is a convenient power of two permitting the values 0 through 255 for one byte, the international standard IEC 80000-13 codified this common meaning. Many types of applications use information representable in eight or fewer bits, the popularity of major commercial computing architectures has aided in the ubiquitous acceptance of the 8-bit size. The unit symbol for the byte was designated as the upper-case letter B by the IEC and IEEE in contrast to the bit, internationally, the unit octet, symbol o, explicitly denotes a sequence of eight bits, eliminating the ambiguity of the byte. It is a respelling of bite to avoid accidental mutation to bit. Early computers used a variety of four-bit binary coded decimal representations and these representations included alphanumeric characters and special graphical symbols. S. Government and universities during the 1960s, the prominence of the System/360 led to the ubiquitous adoption of the eight-bit storage size, while in detail the EBCDIC and ASCII encoding schemes are different. In the early 1960s, AT&T introduced digital telephony first on long-distance trunk lines and these used the eight-bit µ-law encoding. This large investment promised to reduce costs for eight-bit data. The development of microprocessors in the 1970s popularized this storage size. A four-bit quantity is called a nibble, also nybble. The term octet is used to specify a size of eight bits. It is used extensively in protocol definitions, historically, the term octad or octade was used to denote eight bits as well at least in Western Europe, however, this usage is no longer common. The exact origin of the term is unclear, but it can be found in British, Dutch, and German sources of the 1960s and 1970s, and throughout the documentation of Philips mainframe computers. The unit symbol for the byte is specified in IEC 80000-13, IEEE1541, in the International System of Quantities, B is the symbol of the bel, a unit of logarithmic power ratios named after Alexander Graham Bell, creating a conflict with the IEC specification. However, little danger of confusion exists, because the bel is a used unit
28.
Peripheral
–
A peripheral is an ancillary device used to put information into and get information out of the computer. Touchscreens are an example that combines different devices into a hardware component that can be used both as an input and output device. A peripheral device is defined as any auxiliary device such as a computer mouse or keyboard that connects to. Other examples of peripherals are image scanners, tape drives, microphones, loudspeakers, webcams, common input peripherals include keyboards, computer mice, graphic tablets, touchscreens, barcode readers, image scanners, microphones, webcams, game controllers, light pens, and digital cameras. Common output peripherals include computer displays, printers, projectors, computer hardware Controller Display device Expansion card Punched card input/output Punched tape Video game accessory
29.
Static random-access memory
–
Static random-access memory is a type of semiconductor memory that uses bistable latching circuitry to store each bit. SRAM exhibits data remanence, but it is volatile in the conventional sense that data is eventually lost when the memory is not powered. The term static differentiates SRAM from DRAM which must be periodically refreshed, SRAM is faster and more expensive than DRAM, it is typically used for CPU cache while DRAM is used for a computers main memory. Several techniques have been proposed to power consumption of SRAM-based memory structures. Some amount is also embedded in all modern appliances, toys. Several megabytes may be used in products such as digital cameras, cell phones, synthesizers. SRAM in its form is sometimes used for realtime digital signal processing circuits. LCD screens and printers also normally employ static RAM to hold the image displayed, static RAM was used for the main memory of some early personal computers such as the ZX80, TRS-80 Model 100 and Commodore VIC-20. Hobbyists, specifically homebuilt processor enthusiasts, often prefer SRAM due to the ease of interfacing and it is much easier to work with than DRAM as there are no refresh cycles and the address and data buses are directly accessible rather than multiplexed. In addition to buses and power connections, SRAM usually requires only three controls, Chip Enable, Write Enable and Output Enable, in synchronous SRAM, Clock is also included. Non-volatile SRAMs, or nvSRAMs, have standard SRAM functionality, but they save the data when the supply is lost. NvSRAMs are used in a range of situations – networking, aerospace, and medical, among many others – where the preservation of data is critical. Address, data in and other signals are associated with the clock signals In 1990s. Nowadays, synchronous SRAM is rather employed similarly like Synchronous DRAM – DDR SDRAM memory is used than asynchronous DRAM. Synchronous memory interface is much faster as access time can be reduced by employing pipeline architecture. Furthermore, as DRAM is much cheaper than SRAM, SRAM is often replaced by DRAM, SRAM memory is however much faster for random access. Therefore, SRAM memory is used for CPU cache, small on-chip memory. Zero bus turnaround – the turnaround is the number of cycles it takes to change access to the SRAM from write to read
30.
Coprocessor
–
A coprocessor is a computer processor used to supplement the functions of the primary processor. Operations performed by the coprocessor may be floating point arithmetic, graphics, signal processing, string processing, by offloading processor-intensive tasks from the main processor, coprocessors can accelerate system performance. Coprocessors allow a line of computers to be customized, so customers who do not need the extra performance dont need to pay for it. Coprocessors vary in their degree of autonomy, some rely on direct control via coprocessor instructions, embedded in the CPUs instruction stream. It is common for these to be driven by DMA, with the host processor building a command list, the PlayStation 2s Emotion engine contained an unusual DSP-like SIMD vector unit capable of both modes of operation. To make best use of mainframe computer processor time, input/output tasks were delegated to separate systems called Channel I/O, by dedicating relatively simple sub-processors to handle time-consuming I/O formatting and processing, overall system performance was improved. Coprocessors for floating-point arithmetic first appeared in desktop computers in the 1970s and became common throughout the 1980s, early 8-bit and 16-bit processors used software to carry out floating-point arithmetic operations. Where a co-processor was supported, floating-point calculations could be carried out many times faster, math co-processors were popular purchases for users of computer-aided design software and scientific and engineering calculations. Another form of co-processor was a video display coprocessor, as used in the Atari 8-bit family, the Texas Instruments TI-99/4A and MSX home-computers, the Commodore Amiga custom chipset included such a unit known as the Copper, as well as a Blitter for accelerating bitmap manipulation in memory. As microprocessors developed, the cost of integrating the floating point arithmetic functions into the processor declined, high processor speeds also made a closely integrated coprocessor difficult to implement. Separately packaged mathematics co-processors are now uncommon in desktop computers, the demand for a dedicated graphics co-processor has grown, however, particularly due to an increasing demand for realistic 3D graphics in computer games. The original IBM PC included a socket for the Intel 8087 floating-point coprocessor which was an option for people using the PC for CAD or mathematics-intensive calculations. In that architecture, the speeds up floating-point arithmetic on the order of fiftyfold. Users that only used the PC for word processing, for example, saved the high cost of the coprocessor, the 8087 was tightly integrated with the 8086/8088 and responded to floating-point machine code operation codes inserted in the 8088 instruction stream. Another coprocessor for the 8086/8088 central processor was the 8089 input/output coprocessor and it used the same programming technique as 8087 for input/output operations, such as transfer of data from memory to a peripheral device, and so reducing the load on the CPU. But IBM didnt use it in IBM PC design and Intel stopped development of type of coprocessor. The Intel 80386 microprocessor used a math coprocessor to perform floating point operations directly in hardware. The Intel 80486DX processor included floating-point hardware on the chip and these on-chip floating point processors are still referred to as coprocessors because they operate in parallel with the main CPU
31.
Nvidia
–
Nvidia Corporation is an American technology company based in Santa Clara, California. It designs graphics processing units for the market, as well as system on a chip units for the mobile computing. Its primary GPU product line, labeled GeForce, is in competition with Advanced Micro Devices Radeon products. Nvidia expanded its presence in the industry with its handheld SHIELD Portable, SHIELD Tablet. Since 2014, Nvidia has shifted to become a company focused on four markets – gaming, professional visualization, data centers. In addition to GPU manufacturing, Nvidia provides parallel processing capabilities to researchers and they are deployed in supercomputing sites around the world. More recently, It has moved into the computing market. In addition to AMD, its competitors include Intel, Qualcomm, Nvidia is now focused on artificial intelligence. The name of the company comes from Invidia in Roman mythology who corresponds to Nemesis, RIVA TNT in 1998 solidified Nvidias reputation for capable hardware. Autumn 1999 saw the release of the GeForce, most notably introducing on-board transformation, running at 120 MHz and featuring four pixel pipelines, it implemented advanced video acceleration, motion compensation and hardware sub-picture alpha blending. The GeForce outperformed existing products by a wide margin, due to the success of its products, Nvidia won the contract to develop the graphics hardware for Microsofts Xbox game console, which earned Nvidia a $200 million advance. However, the project drew the time of many of its best engineers away from other projects, in the short term this did not matter, and the GeForce2 GTS shipped in the summer of 2000. In December 2000, Nvidia reached an agreement to acquire the assets of its one-time rival 3dfx. The acquisition process was finalized in April 2002, in July 2002, Nvidia acquired Exluna for an undisclosed sum. Exluna made software rendering tools and the personnel were merged into the Cg project, in August 2003, Nvidia acquired MediaQ for approximately US$70 million. On April 22,2004, Nvidia acquired iReady, also a provider of high performance TCP/IP, in December 2004, it was announced that Nvidia would assist Sony with the design of the graphics processor in the PlayStation 3 game console. In March 2006, it emerged that Nvidia would deliver RSX to Sony as an IP core, under the agreement, Nvidia would provide ongoing support to port the RSX to Sonys fabs of choice, as well as die shrinks to 65 nm. This practice contrasted with its business arrangement with Microsoft, in which Nvidia managed production, meanwhile, in May 2005 Microsoft chose to license a design by ATI and to make its own manufacturing arrangements for the Xbox 360 graphics hardware, as had Nintendo for the Wii console
32.
Samsung Galaxy Tab 3 7.0
–
The Samsung Galaxy Tab 37.0 is a 7-inch Android-based tablet computer produced and marketed by Samsung Electronics. It belongs to the generation of the Samsung Galaxy Tab series, which also includes the 8-inch Galaxy Tab 38.0. It was announced on 24 June 2013 and launched in the US on 7 July 2013, the Galaxy Tab 37.0 was announced on 24 June 2013. It was shown along with the Galaxy Tab 310.1 at the 2013 Mobile World Conference, Samsung confirmed that the Galaxy Tab 37.0 would be released on 7 July, with a price of $199 for the 8GB model. Upgrade to Kitkat 4.4.2 in September 2014 does not support Miracast, the Galaxy Tab 37.0 was released with Android 4.1.2 Jelly Bean. But the Wi-Fi model has received the Android 4.4.2 Operating System Update. Samsung has customized the interface with its TouchWiz UX software, as well as apps from Google, including Google Play, Gmail and YouTube, it has access to Samsung apps such as ChatON, Smart Remote, S Voice, Group Play, Multi-Window and All Share Play. The Galaxy Tab 37.0 is available in WiFi-only, WiFi with an IR Blaster depending on region, 3G & WiFi, internal storage ranges from 8 GB to 32 GB, depending on the model, with a microSD card slot for expansion. It has a 7-inch TFT LCD screen with a resolution of 1024x600 pixels, reception for the Galaxy Tab 37.0 has been generally mixed. PC World Australia reviewer Ross Catanzariti commented, The Galaxy Tab 37.0 is an update to the Galaxy Tab 27.0 but theres not much thats new. Both Catanzariti and blog. gsmarenas Vince Lockford praised the size and lighter weight of the device, as well as the unified Samsung design language also used in the S4. As a special edition of this tablet, Samsung also released a Hello Kitty edition in November 2013, another special edition is the Samsung Galaxy Tab 3 Kids Edition. This is a tablet that has all the normal features of the tablet. It was launched on 10 November 2013
