Perseus-M is a pair of microsatellite developed by Russian-American company Dauria Aerospace and launched in 2014. The satellite is built in 6U Cubesat bus, optimized for piggy-back launch. All instruments are powered by solar cells mounted on the one side of spacecraft, providing 6W average power. Perseus-M1 and Perseus-M2 were launched from Dombarovsky site 13, Russia, on 19 June 2014 by a Dnepr rocket. Telemetry beacons were received and decoded by multiple amateur ground station operators starting on 6 July 2014; the satellites are intended for radio-frequency maritime survelliance under contract with Russian Federation. 2014 in spaceflight Dauria Aerospace facebook page http://www.deimos-space.com/en/
Titan was supposed to be a family of 32-bit Power ISA-based microprocessor cores designed by Applied Micro Circuits Corporation, but was scrapped in 2010 according to reports. Applied Micro chose to continue development of the PowerPC 400 core instead, on a 40 nm fabrication process, it was designed to be the foundation of system-on-a-chip solutions. While being high performance, reaching speeds up to 2 GHz, it would remain power efficient, drawing just 2.5 W per core. Where there is a trade-off between performance and power, AMCC used the Fast14 technology from Intrinsity to build an efficient microprocessor design leveraging high performance combined with low power and comparably cheap bulk 90 nm CMOS manufacturing. By using NMOS transistors and no latches, the design results in a chip with fewer transistors than traditional design, thus reducing cost; the design allows for dual core SoC implementations consuming less than 15 W. There were plans for single and quad-core versions; the Titan had a new superscalar, out of order 8-9 stage core with a novel three-stage CPU cache design.
Small 4/4 KiB instruction and data caches at "level 0" sit before the traditional 32/32 KiB L1 caches up to 1 MB L2 cache that will be shared between all cores. The Titan was compliant with the Power ISA v.2.04. APM 83290 – The first implementations of the Titan core design, codenamed Gemeni. Two 1.5 GHz cores with FPU, 512 kB shared L2 cache, DDR2 controller, security engine, multi-channel DMA and I/O engine for gigabit Ethernet, PCIe, USB, RapidIO and SATA. It began sampling in October 2009; the processor is aimed at control plane applications. It is built using TSMC's 90 nm bulk CMOS fabrication to reduce cost. AMCC's pressrelease AMCC Next Generation Power Architecture Processor - Titan – Power.org AMCC drives to high end of embedded PowerPC market – EETimes Intrinsity Nets 2 GHz, 4000 DMIPS PowerPC FastCore - Market Wire