1.
Effects unit
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An effects unit or pedal is an electronic or digital device that alters how a musical instrument or other audio source sounds. In the 2010s, most effects use solid state electronics and/or computer chips, some vintage effects units from the 1930s to the 1970s and modern reissues of these effects use mechanical components as well or vacuum tubes. Musicians, audio engineers and record producers use effects units during live performances or in the studio, typically with electric guitar, electronic keyboard, while guitar effects are most frequently used with electric or electronic instruments, effects can also be used with acoustic instruments, drums and vocals. Rackmounted or audio console-integrated reverb effects are used with vocals in live sound and sound recording. Examples of common units include wah-wah pedals, fuzzboxes and reverb units. A stompbox or pedal is a metal or plastic box placed on the floor in front of the musician and connected to the instrument. Pedals are usually the least expensive format, a rackmount device mounts on a standard 19-inch equipment rack and usually contains several types of effects. Rackmount effects typically have buttons and/or knobs on the face of the chassis for controlling the effects, an effects unit is also called an effect box, effects device, effects processor or simply effects. In audio engineer parlance, a signal without effects is dry, the abbreviation F/X or FX is sometimes used. A pedal-style unit may be called a box, stompbox. When a musician has multiple effects in a rack mounted road case, Effects units are available in a variety of formats or form factors. Stompboxes are usually the smallest, least expensive, and most rugged effects units, rackmount devices are generally more expensive and offer a wider range of functions. An effects unit can consist of analog or digital circuitry or a combination of the two, during a live performance, the effect is plugged into the electrical signal path of the instrument. In the studio, the instrument or other sound-sources auxiliary output is patched into the effect, form factors are part of a studio or musicians outboard gear. Stompboxes are small plastic or metal chassis which usually lie on the floor or in a pedalboard to be operated by the users feet, pedals are often rectangle-shaped, but there are a range of other shapes. Typical simple stompboxes have a single footswitch, one to three potentiometers for controlling the effect, and a single LED that indicates if the effect is on, depending on the type of pedal, the potentiometers may control different parameters of the effect. For a chorus effect, for example, the knobs may control the depth, some pedals have two knobs stacked on top of each other, enabling the unit to provide two knobs per single knob space. An effects chain or signal chain is formed by connecting two or more stompboxes, effect chains are typically created between the guitar and the amp or between the preamplifier and the power amp
2.
Microprocessor
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A microprocessor is a computer processor which incorporates the functions of a computers central processing unit on a single integrated circuit, or at most a few integrated circuits. Microprocessors contain both combinational logic and sequential digital logic, Microprocessors operate on numbers and symbols represented in the binary numeral system. The integration of a whole CPU onto a chip or on a few chips greatly reduced the cost of processing power. Integrated circuit processors are produced in numbers by highly automated processes resulting in a low per unit cost. Single-chip processors increase reliability as there are many electrical connections to fail. As microprocessor designs get better, the cost of manufacturing a chip generally stays the same, before microprocessors, small computers had been built using racks of circuit boards with many medium- and small-scale integrated circuits. Microprocessors combined this into one or a few large-scale ICs, the internal arrangement of a microprocessor varies depending on the age of the design and the intended purposes of the microprocessor. Advancing technology makes more complex and powerful chips feasible to manufacture, a minimal hypothetical microprocessor might only include an arithmetic logic unit and a control logic section. The ALU performs operations such as addition, subtraction, and operations such as AND or OR, each operation of the ALU sets one or more flags in a status register, which indicate the results of the last operation. The control logic retrieves instruction codes from memory and initiates the sequence of operations required for the ALU to carry out the instruction, a single operation code might affect many individual data paths, registers, and other elements of the processor. As integrated circuit technology advanced, it was feasible to manufacture more and more complex processors on a single chip, the size of data objects became larger, allowing more transistors on a chip allowed word sizes to increase from 4- and 8-bit words up to todays 64-bit words. Additional features were added to the architecture, more on-chip registers sped up programs. Floating-point arithmetic, for example, was not available on 8-bit microprocessors. Integration of the point unit first as a separate integrated circuit and then as part of the same microprocessor chip. Occasionally, physical limitations of integrated circuits made such practices as a bit slice approach necessary, instead of processing all of a long word on one integrated circuit, multiple circuits in parallel processed subsets of each data word. With the ability to put large numbers of transistors on one chip and this CPU cache has the advantage of faster access than off-chip memory, and increases the processing speed of the system for many applications. Processor clock frequency has increased more rapidly than external memory speed, except in the recent past, a microprocessor is a general purpose system. Several specialized processing devices have followed from the technology, A digital signal processor is specialized for signal processing, graphics processing units are processors designed primarily for realtime rendering of 3D images
3.
Digital signal processing
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Digital signal processing is the use of digital processing, such as by computers, to perform a wide variety of signal processing operations. The signals processed in this manner are a sequence of numbers that represent samples of a variable in a domain such as time, space. Digital signal processing and analog signal processing are subfields of signal processing, digital signal processing can involve linear or nonlinear operations. Nonlinear signal processing is closely related to system identification and can be implemented in the time, frequency. DSP is applicable to both streaming data and static data, the increasing use of computers has resulted in the increased use of, and need for, digital signal processing. To digitally analyze and manipulate an analog signal, it must be digitized with an analog-to-digital converter, sampling is usually carried out in two stages, discretization and quantization. Discretization means that the signal is divided into equal intervals of time, quantization means each amplitude measurement is approximated by a value from a finite set. Rounding real numbers to integers is an example, the Nyquist–Shannon sampling theorem states that a signal can be exactly reconstructed from its samples if the sampling frequency is greater than twice the highest frequency of the signal. In practice, the frequency is often significantly higher than twice that required by the signals limited bandwidth. Theoretical DSP analyses and derivations are typically performed on discrete-time signal models with no amplitude inaccuracies, numerical methods require a quantized signal, such as those produced by an analog-to-digital converter. The processed result might be a frequency spectrum or a set of statistics, but often it is another quantized signal that is converted back to analog form by a digital-to-analog converter. In DSP, engineers usually study digital signals in one of the domains, time domain, spatial domain, frequency domain. They choose the domain in which to process a signal by making an assumption as to which domain best represents the essential characteristics of the signal. The most common processing approach in the time or space domain is enhancement of the signal through a method called filtering. Digital filtering generally consists of linear transformation of a number of surrounding samples around the current sample of the input or output signal. There are various ways to characterize filters, for example, A linear filter is a transformation of input samples. A causal filter uses only samples of the input or output signals. A non-causal filter can usually be changed into a filter by adding a delay to it
4.
Mobile phone
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A mobile phone is a portable telephone that can make and receive calls over a radio frequency link while the user is moving within a telephone service area. The radio frequency link establishes a connection to the systems of a mobile phone operator. Most modern mobile telephone services use a network architecture, and, therefore. Mobile phones which offer these and more general computing capabilities are referred to as smartphones, the first handheld mobile phone was demonstrated by John F. Mitchell and Martin Cooper of Motorola in 1973, using a handset weighing c.4.4 lbs. In 1983, the DynaTAC 8000x was the first commercially available mobile phone. From 1983 to 2014, worldwide mobile phone subscriptions grew to seven billion, penetrating 100% of the global population. In first quarter of 2016, the top smartphone manufacturers were Samsung, Apple, a handheld mobile radio telephone service was envisioned in the early stages of radio engineering. In 1917, Finnish inventor Eric Tigerstedt filed a patent for a pocket-size folding telephone with a thin carbon microphone. Early predecessors of cellular phones included analog radio communications from ships, the race to create truly portable telephone devices began after World War II, with developments taking place in many countries. These 0G systems were not cellular, supported few simultaneous calls, the first handheld mobile phone was demonstrated by John F. Mitchell and Martin Cooper of Motorola in 1973, using a handset weighing c.4.4 lbs. The first commercial automated cellular network was launched in Japan by Nippon Telegraph and this was followed in 1981 by the simultaneous launch of the Nordic Mobile Telephone system in Denmark, Finland, Norway, and Sweden. Several other countries followed in the early to mid-1980s. These first-generation systems could support far more simultaneous calls but still used analog cellular technology, in 1983, the DynaTAC 8000x was the first commercially available handheld mobile phone. In 1991, the digital cellular technology was launched in Finland by Radiolinja on the GSM standard. This sparked competition in the sector as the new operators challenged the incumbent 1G network operators, ten years later, in 2001, the third generation was launched in Japan by NTT DoCoMo on the WCDMA standard. This was followed by 3. 5G, 3G+ or turbo 3G enhancements based on the high-speed packet access family, allowing UMTS networks to have data transfer speeds. By 2009, it had become clear that, at point, 3G networks would be overwhelmed by the growth of bandwidth-intensive applications. Consequently, the industry began looking to data-optimized fourth-generation technologies, with the promise of speed improvements up to ten-fold over existing 3G technologies
5.
Algorithm
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In mathematics and computer science, an algorithm is a self-contained sequence of actions to be performed. Algorithms can perform calculation, data processing and automated reasoning tasks, an algorithm is an effective method that can be expressed within a finite amount of space and time and in a well-defined formal language for calculating a function. The transition from one state to the next is not necessarily deterministic, some algorithms, known as randomized algorithms, giving a formal definition of algorithms, corresponding to the intuitive notion, remains a challenging problem. In English, it was first used in about 1230 and then by Chaucer in 1391, English adopted the French term, but it wasnt until the late 19th century that algorithm took on the meaning that it has in modern English. Another early use of the word is from 1240, in a manual titled Carmen de Algorismo composed by Alexandre de Villedieu and it begins thus, Haec algorismus ars praesens dicitur, in qua / Talibus Indorum fruimur bis quinque figuris. Which translates as, Algorism is the art by which at present we use those Indian figures, the poem is a few hundred lines long and summarizes the art of calculating with the new style of Indian dice, or Talibus Indorum, or Hindu numerals. An informal definition could be a set of rules that precisely defines a sequence of operations, which would include all computer programs, including programs that do not perform numeric calculations. Generally, a program is only an algorithm if it stops eventually, but humans can do something equally useful, in the case of certain enumerably infinite sets, They can give explicit instructions for determining the nth member of the set, for arbitrary finite n. An enumerably infinite set is one whose elements can be put into one-to-one correspondence with the integers, the concept of algorithm is also used to define the notion of decidability. That notion is central for explaining how formal systems come into being starting from a set of axioms. In logic, the time that an algorithm requires to complete cannot be measured, from such uncertainties, that characterize ongoing work, stems the unavailability of a definition of algorithm that suits both concrete and abstract usage of the term. Algorithms are essential to the way computers process data, thus, an algorithm can be considered to be any sequence of operations that can be simulated by a Turing-complete system. Although this may seem extreme, the arguments, in its favor are hard to refute. Gurevich. Turings informal argument in favor of his thesis justifies a stronger thesis, according to Savage, an algorithm is a computational process defined by a Turing machine. Typically, when an algorithm is associated with processing information, data can be read from a source, written to an output device. Stored data are regarded as part of the state of the entity performing the algorithm. In practice, the state is stored in one or more data structures, for some such computational process, the algorithm must be rigorously defined, specified in the way it applies in all possible circumstances that could arise. That is, any conditional steps must be dealt with, case-by-case
6.
Communications satellite
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Communications satellites are used for television, telephone, radio, internet, and military applications. There are over 2,000 communications satellites in Earth’s orbit, Wireless communication uses electromagnetic waves to carry signals. These waves require line-of-sight, and are thus obstructed by the curvature of the Earth, the purpose of communications satellites is to relay the signal around the curve of the Earth allowing communication between widely separated points. Communications satellites use a range of radio and microwave frequencies. To avoid signal interference, international organizations have regulations for which frequency ranges or bands certain organizations are allowed to use and this allocation of bands minimizes the risk of signal interference. The concept of the communications satellite was first proposed by Arthur C. Clarke, building on work by Konstantin Tsiolkovsky and on the 1929 work by Herman Potočnik Das Problem der Befahrung des Weltraums — der Raketen-motor, in October 1945 Clarke published an article titled Extraterrestrial Relays in the British magazine Wireless World. The article described the fundamentals behind the deployment of artificial satellites in geostationary orbits for the purpose of relaying radio signals, thus, Arthur C. Clarke is often quoted as being the inventor of the communications satellite and the term Clarke Belt employed as a description of the orbit. Decades later a project named Communication Moon Relay was a project carried out by the United States Navy. Its objective was to develop a secure and reliable method of communication by using the Moon as a passive reflector. The first artificial Earth satellite was Sputnik 1, put into orbit by the Soviet Union on October 4,1957, it was equipped with an on-board radio-transmitter that worked on two frequencies,20.005 and 40.002 MHz. Sputnik 1 was launched as a step in the exploration of space, while incredibly important it was not placed in orbit for the purpose of sending data from one point on earth to another. And it was the first artificial satellite in the leading to todays satellite communications. The first artificial satellite used solely to further advances in communications was a balloon named Echo 1. Echo 1 was the worlds first artificial communications satellite capable of relaying signals to other points on Earth and it soared 1,600 kilometres above the planet after its Aug.12,1960 launch, yet relied on humanitys oldest flight technology — ballooning. Launched by NASA, Echo 1 was a 30-metre aluminized PET film balloon served as a passive reflector for radio communications. The worlds first inflatable satellite — or satelloon, as they were informally known — helped lay the foundation of todays satellite communications, the idea behind a communications satellite is simple, Send data up into space and beam it back down to another spot on the globe. Echo 1 accomplished this by serving as an enormous mirror,10 stories tall
7.
SES S.A.
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SES S. A. is a communications satellite owner and operator based in Betzdorf, Luxembourg. The companys stock is listed on the Luxembourg Stock Exchange and Euronext Paris with ticker symbol SESG and is a component of the LuxX, CAC Next 20, the company was founded in 1985 as Société Européenne des Satellites. It renamed itself SES Global in 2001, reverting to SES in 2006, SES services are provided in the four areas of video, enterprise, mobility, and government. Video and TV distribution accounts for 70% of the business, as well as distribution SES also provides technical services to broadcasters such as content management, playout, encryption and interactive services, in particular through the MX1 division. SES has been a player in the development of the direct-to-home market in Europe. In the U. S. SES provides cable-feed services and HD-PRIME, in both geostationary orbit and medium earth orbit, SES offers satellite and integrated connectivity services worldwide. SES supplies the SES Broadband satellite-based, broadband access for users in remote locations where terrestrial broadband services are not available. In September 2015, after one year of operations, O3b had 40 customers across 31 countries. Maritime users at sea across the globe benefit from high-speed internet connectivity for web browsing, VoIP telephone, email, SES satellites are also used to fulfil the growing popularity of connectivity in the aeronautical industry, such as on-board fast broadband access and high-quality in-flight entertainment. SES has a history of providing satellite capacity to U. S, for Europe, SES Astra 5B and SES-5 satellites incorporate European geostationary navigation overlay system EGNOS payloads, a supplementary network to the Galileo navigation system. SES has pioneered many industry technological developments, including DTH transmission, co-location of satellites, free-to-air broadcast neighbourhoods, digital broadcasting, SES is currently pioneering the broadcast of next generation Ultra High Definition TV and helping to establish the international technical standards for UHD broadcast and reception. SES first produced demonstration UHD broadcasts in 2012 and transmitted the first HEVC-standard UHD TV in 2013, as of April 2016, SES broadcasts 23 Ultra HD channels, of which 15 are commercial operations. SES-8 was the first geostationary satellite to be launched by privately funded company, SpaceX, the SES-10 satellite, was launched on a Falcon 9 rocket, the first SpaceX launch with a flight-proven Falcon first stage, recovered from a previous launch. SES reckons that SES-12 would weigh some 4700 kg more with a chemical propulsion system. SES satellites are positioned in more than 30 orbital slots around the World and this was put in place in May 2011 to consolidate the then subsidiary companies, SES Astra and SES World Skies under a new streamlined management structure. SES was formed on the initiative and support of the Luxembourg Government in 1985 as Société Européenne des Satellites, the Luxembourg State remains a major shareholder. In 1988, as Europe’s first private operator, SES launched its first satellite, Astra 1A. Rupert Murdoch’s Sky TV, along with German broadcasters Pro7, Sat.1, by 1990, Astra was broadcasting to 14 million cable and DTH viewers
8.
Airbus Defence and Space
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Airbus Defence and Space is a division of Airbus Group responsible for defence and aerospace products and services. The division was formed in January 2014 during the restructuring of European Aeronautic Defence and Space, and comprises the former Airbus Military, Astrium. It is the second largest space company after Boeing and one of the top ten defence companies in the world. Airbus Defence and Space has its headquarters in Toulouse, France, and is led by Dirk Hoke. The company is divided into three sections, Military Aircraft, Space Systems, and Communication-Intelligence-Security, with its presence in 35 countries, the company employs 40,000 people from 86 nationalities and contributes to 21% of Airbus Group revenues. In 2015 Airbus ranked 100th on the Fortune Global 500 list, the two companies envisaged including the French company Aérospatiale, the other major European aerospace company, but only after its privatisation. The first stage of integration was seen as the transformation of Airbus from a consortium of British Aerospace, DASA, Aérospatiale. The merger of British Aerospace and MES to form BAE Systems was announced on 19 January 1999, DASA and the Spanish aircraft company Construcciones Aeronáuticas SA agreed to merge on 11 June 1999. On 14 October 1999 DASA agreed to merge with Aérospatiale-Matra to create the European Aeronautic Defence and Space Company,10 July 2000 was Day One for the new company which became the worlds second-largest aerospace company after Boeing and the second-largest European arms manufacturer after BAE Systems. In January 2001 Airbus Industrie was transformed from an inherently inefficient consortium structure to a joint stock company, with legal. On 16 June 2003 EADS acquired BAEs 25 % share in Astrium, EADS paid £84 million, however due to the lossmaking status of the company BAE invested an equal amount for restructuring. It was subsequently renamed EADS Astrium, and had the divisions Astrium Satellites, Astrium Space Transportation, on 1 July 2003 EADS Defence & Security Systems was founded with the merger of the activities of missile systems, defence electronics, military aircraft and telecommunications of the EADS Group. Tom Enders became the first CEO of the new division, the predecessor company was established in January 1999 as the Airbus Military Company SAS to manage the Airbus A400M project, taking over from the Euroflag consortium. In May 2003, the company was restructured as Airbus Military Sociedad Limitada prior to the execution of the production contract, the Military Transport Aircraft Division was a division of EADS which designs, manufactures and commercialises EADS-CASA light and medium transport aircraft, and headquartered in Madrid, Spain. In 1999 was Construcciones Aeronáuticas SA in the EADS Group incorporated, in Spain it was still referred to as EADS-CASA. The division manufactured tanker, transport and mission aircraft including Airbus A330 MRTT, Airbus A400M, CASA C-212 Aviocar, CASA/IPTN CN-235, after the merger, it also acquired the production of Eurofighter Typhoon, which was earlier under Cassidian. Eurocopter, which was earlier under Airbus Military, was reorganized as Airbus Helicopters, Astrium was formed in 2000 by the merger of Matra Marconi Space with the space division of DaimlerChrysler Aerospace AG and Computadores Redes e Ingeniería SA. Henceforth Astrium was a joint venture between EADS and BAE Systems, on 16 June 2003 the minority shareholder, BAE Systems, sold its 25% share to EADS, making EADS the sole shareholder
9.
Assembly language
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Each assembly language is specific to a particular computer architecture. In contrast, most high-level programming languages are generally portable across multiple architectures, Assembly language may also be called symbolic machine code. Assembly language is converted into machine code by a utility program referred to as an assembler. The conversion process is referred to as assembly, or assembling the source code, Assembly time is the computational step where an assembler is run. Assembly language uses a mnemonic to represent each low-level machine instruction or opcode, typically also each architectural register, flag, depending on the architecture, these elements may also be combined for specific instructions or addressing modes using offsets or other data as well as fixed addresses. Many assemblers offer additional mechanisms to facilitate development, to control the assembly process. A macro assembler includes a facility so that assembly language text can be represented by a name. A cross assembler is an assembler that is run on a computer or operating system of a different type from the system on which the code is to run. Cross-assembling facilitates the development of programs for systems that do not have the resources to support software development, a microassembler is a program that helps prepare a microprogram, called firmware, to control the low level operation of a computer. A meta-assembler is a used in some circles for a program that accepts the syntactic and semantic description of an assembly language. An assembler program creates object code by translating combinations of mnemonics and syntax for operations and this representation typically includes an operation code as well as other control bits and data. The assembler also calculates constant expressions and resolves symbolic names for memory locations, the use of symbolic references is a key feature of assemblers, saving tedious calculations and manual address updates after program modifications. Most assemblers also include facilities for performing textual substitution – e. g. to generate common short sequences of instructions as inline. Some assemblers may also be able to some simple types of instruction set-specific optimizations. One concrete example of this may be the ubiquitous x86 assemblers from various vendors, most of them are able to perform jump-instruction replacements in any number of passes, on request. Like early programming languages such as Fortran, Algol, Cobol and Lisp, assemblers have been available since the 1950s, however, assemblers came first as they are far simpler to write than compilers for high-level languages. There may be several assemblers with different syntax for a particular CPU or instruction set architecture, despite different appearances, different syntactic forms generally generate the same numeric machine code, see further below. A single assembler may also have different modes in order to support variations in syntactic forms as well as their exact semantic interpretations, there are two types of assemblers based on how many passes through the source are needed to produce the executable program
10.
Matrix (mathematics)
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In mathematics, a matrix is a rectangular array of numbers, symbols, or expressions, arranged in rows and columns. For example, the dimensions of the matrix below are 2 ×3, the individual items in an m × n matrix A, often denoted by ai, j, where max i = m and max j = n, are called its elements or entries. Provided that they have the size, two matrices can be added or subtracted element by element. The rule for multiplication, however, is that two matrices can be multiplied only when the number of columns in the first equals the number of rows in the second. Any matrix can be multiplied element-wise by a scalar from its associated field, a major application of matrices is to represent linear transformations, that is, generalizations of linear functions such as f = 4x. The product of two matrices is a matrix that represents the composition of two linear transformations. Another application of matrices is in the solution of systems of linear equations, if the matrix is square, it is possible to deduce some of its properties by computing its determinant. For example, a matrix has an inverse if and only if its determinant is not zero. Insight into the geometry of a transformation is obtainable from the matrixs eigenvalues. Applications of matrices are found in most scientific fields, in computer graphics, they are used to manipulate 3D models and project them onto a 2-dimensional screen. Matrix calculus generalizes classical analytical notions such as derivatives and exponentials to higher dimensions, Matrices are used in economics to describe systems of economic relationships. A major branch of analysis is devoted to the development of efficient algorithms for matrix computations. Matrix decomposition methods simplify computations, both theoretically and practically, algorithms that are tailored to particular matrix structures, such as sparse matrices and near-diagonal matrices, expedite computations in finite element method and other computations. Infinite matrices occur in planetary theory and in atomic theory, a simple example of an infinite matrix is the matrix representing the derivative operator, which acts on the Taylor series of a function. A matrix is an array of numbers or other mathematical objects for which operations such as addition and multiplication are defined. Most commonly, a matrix over a field F is an array of scalars each of which is a member of F. Most of this focuses on real and complex matrices, that is, matrices whose elements are real numbers or complex numbers. More general types of entries are discussed below, for instance, this is a real matrix, A =
11.
Convolution
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It has applications that include probability, statistics, computer vision, natural language processing, image and signal processing, engineering, and differential equations. The convolution can be defined for functions on other than Euclidean space. For example, periodic functions, such as the discrete-time Fourier transform, can be defined on a circle, a discrete convolution can be defined for functions on the set of integers. Computing the inverse of the operation is known as deconvolution. The convolution of f and g is written f∗g, using an asterisk or star and it is defined as the integral of the product of the two functions after one is reversed and shifted. As such, it is a kind of integral transform. While the symbol t is used above, it need not represent the time domain, but in that context, the convolution formula can be described as a weighted average of the function f at the moment t where the weighting is given by g simply shifted by amount t. As t changes, the weighting function emphasizes different parts of the input function, for the multi-dimensional formulation of convolution, see Domain of definition. A primarily engineering convention that one sees is, f ∗ g = d e f ∫ − ∞ ∞ f g d τ ⏟. For instance, ƒ*g is equivalent to, but ƒ*g is in fact equivalent to, Convolution describes the output of an important class of operations known as linear time-invariant. See LTI system theory for a derivation of convolution as the result of LTI constraints, in terms of the Fourier transforms of the input and output of an LTI operation, no new frequency components are created. The existing ones are only modified, in other words, the output transform is the pointwise product of the input transform with a third transform. See Convolution theorem for a derivation of that property of convolution, conversely, convolution can be derived as the inverse Fourier transform of the pointwise product of two Fourier transforms. One of the earliest uses of the convolution integral appeared in DAlemberts derivation of Taylors theorem in Recherches sur différents points importants du système du monde, soon thereafter, convolution operations appear in the works of Pierre Simon Laplace, Jean-Baptiste Joseph Fourier, Siméon Denis Poisson, and others. The term itself did not come into use until the 1950s or 60s. Prior to that it was known as faltung, composition product, superposition integral. Yet it appears as early as 1903, though the definition is rather unfamiliar in older uses, the operation, ∫0 t φ ψ d s,0 ≤ t < ∞, is a particular case of composition products considered by the Italian mathematician Vito Volterra in 1913. The summation is called a summation of the function f
12.
Dot product
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In mathematics, the dot product or scalar product is an algebraic operation that takes two equal-length sequences of numbers and returns a single number. Sometimes it is called inner product in the context of Euclidean space, algebraically, the dot product is the sum of the products of the corresponding entries of the two sequences of numbers. Geometrically, it is the product of the Euclidean magnitudes of the two vectors and the cosine of the angle between them, the dot product may be defined algebraically or geometrically. The geometric definition is based on the notions of angle and distance, the equivalence of these two definitions relies on having a Cartesian coordinate system for Euclidean space. In such a presentation, the notions of length and angles are not primitive, so the equivalence of the two definitions of the dot product is a part of the equivalence of the classical and the modern formulations of Euclidean geometry. For instance, in space, the dot product of vectors and is. In Euclidean space, a Euclidean vector is an object that possesses both a magnitude and a direction. A vector can be pictured as an arrow and its magnitude is its length, and its direction is the direction that the arrow points. The magnitude of a vector a is denoted by ∥ a ∥, the dot product of two Euclidean vectors a and b is defined by a ⋅ b = ∥ a ∥ ∥ b ∥ cos , where θ is the angle between a and b. In particular, if a and b are orthogonal, then the angle between them is 90° and a ⋅ b =0. The scalar projection of a Euclidean vector a in the direction of a Euclidean vector b is given by a b = ∥ a ∥ cos θ, where θ is the angle between a and b. In terms of the definition of the dot product, this can be rewritten a b = a ⋅ b ^. The dot product is thus characterized geometrically by a ⋅ b = a b ∥ b ∥ = b a ∥ a ∥. The dot product, defined in this manner, is homogeneous under scaling in each variable and it also satisfies a distributive law, meaning that a ⋅ = a ⋅ b + a ⋅ c. These properties may be summarized by saying that the dot product is a bilinear form, moreover, this bilinear form is positive definite, which means that a ⋅ a is never negative and is zero if and only if a =0. En are the basis vectors in Rn, then we may write a = = ∑ i a i e i b = = ∑ i b i e i. The vectors ei are a basis, which means that they have unit length and are at right angles to each other. Hence since these vectors have unit length e i ⋅ e i =1 and since they form right angles with each other, thus in general we can say that, e i ⋅ e j = δ i j
13.
Horner scheme
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The latter is also known as Ruffini–Horners method. To accomplish this, we define a new sequence of constants as follows, then b 0 is the value of p. To see why this works, note that the polynomial can be written in the form p = a 0 + x. Thus, by substituting the b i into the expression. Evaluate f =2 x 3 −6 x 2 +2 x −1 for x =3. We use synthetic division as follows, x₀│ x³ x² x¹ x⁰3 │2 −62 −1 │606 └────────────────────────2025 The entries in the row are the sum of those in the first two. Each entry in the row is the product of the x-value with the third-row entry immediately to the left. The entries in the first row are the coefficients of the polynomial to be evaluated, then the remainder of f on division by x −3 is 5. But by the polynomial remainder theorem, we know that the remainder is f, so, synthetic division is based on Horners method. As a consequence of the polynomial remainder theorem, the entries in the row are the coefficients of the second-degree polynomial. This makes Horners method useful for long division. Divide x 3 −6 x 2 +11 x −6 by x −2,2 │1 -611 -6 │2 -86 └────────────────────────1 -430 The quotient is x 2 −4 x +3. Let f 1 =4 x 4 −6 x 3 +3 x −5 and f 2 =2 x −1, divide f 1 by f 2 using Horners method. 2 │4 -603 │ -5 ────┼──────────────────────┼───────1 │2 -2 -1 │1 │ │ └──────────────────────┼───────2 -2 -11 │ -4 The third row is the sum of the first two rows, divided by 2. Each entry in the row is the product of 1 with the third-row entry to the left. The answer is f 1 f 2 =2 x 3 −2 x 2 − x +1 −42 x −1, Horners method is a fast, code-efficient method for multiplication and division of binary numbers on a microcontroller with no hardware multiplier. One of the numbers to be multiplied is represented as a trivial polynomial, where, ai =1. Then, x is repeatedly factored out, in this binary numeral system, x =2, so powers of 2 are repeatedly factored out
14.
Finite impulse response
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In signal processing, a finite impulse response filter is a filter whose impulse response is of finite duration, because it settles to zero in finite time. This is in contrast to infinite impulse response filters, which may have internal feedback, the impulse response of an Nth-order discrete-time FIR filter lasts exactly N +1 samples before it then settles to zero. FIR filters can be discrete-time or continuous-time, and digital or analog, if the filter is a direct form FIR filter then b i is also a coefficient of the filter. This computation is also known as discrete convolution, one may speak of a 5th order/6-tap filter, for instance. The impulse response of the filter as defined is nonzero over a finite duration, including zeros, the impulse response is the infinite sequence, h = ∑ i =0 N b i ⋅ δ = { b n 0 ≤ n ≤ N0 otherwise. If an FIR filter is non-causal, the range of values in its impulse response can start before n =0. An FIR filter has a number of properties which sometimes make it preferable to an infinite impulse response filter. This means that any rounding errors are not compounded by summed iterations, the same relative error occurs in each calculation. Are inherently stable, since the output is a sum of a number of finite multiples of the input values. Can easily be designed to be linear phase by making the coefficient sequence symmetric and this property is sometimes desired for phase-sensitive applications, for example data communications, seismology, crossover filters, and mastering. However many digital signal processors provide specialized hardware features to make FIR filters approximately as efficient as IIR for many applications, therefore, the complex-valued, multiplicative function H is the filters frequency response. It is defined by a Fourier series, H2 π = d e f ∑ n = − ∞ ∞ h ⋅ − n = ∑ n =0 N b n ⋅ − n, here ω represents frequency in normalized units. The substitution ω =2 π f, favored by many filter design programs, changes the units of frequency to cycles/sample and the periodicity to 1. When the x sequence has a known sampling-rate, f s samples/second, the substitution ω =2 π f / f s changes the units of frequency to cycles/second and the periodicity to f s. The value ω = π corresponds to a frequency of f = f s 2 Hz =12 cycles/sample, which is the Nyquist frequency. The frequency response, H2 π, can also be written as H, Z is a complex variable, and H is a surface. One cycle of the frequency response can be found in the region defined by z = e i ω, − π ≤ ω ≤ π. Filter transfer functions are used to verify the stability of IIR designs
15.
Fast Fourier transform
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A fast Fourier transform algorithm computes the discrete Fourier transform of a sequence, or its inverse. Fourier analysis converts a signal from its domain to a representation in the frequency domain. An FFT rapidly computes such transformations by factorizing the DFT matrix into a product of sparse factors. As a result, it manages to reduce the complexity of computing the DFT from O, which if one simply applies the definition of DFT, to O. Fast Fourier transforms are used for many applications in engineering, science. The basic ideas were popularized in 1965, but some algorithms had been derived as early as 1805, the DFT is obtained by decomposing a sequence of values into components of different frequencies. This operation is useful in many fields but computing it directly from the definition is too slow to be practical. The difference in speed can be enormous, especially for data sets where N may be in the thousands or millions. In practice, the time can be reduced by several orders of magnitude in such cases. The best-known FFT algorithms depend upon the factorization of N, but there are FFTs with O complexity for all N, even for prime N. Since the inverse DFT is the same as the DFT, but with the sign in the exponent. The development of fast algorithms for DFT can be traced to Gausss unpublished work in 1805 when he needed it to interpolate the orbit of asteroids Pallas and Juno from sample observations. His method was similar to the one published in 1965 by Cooley and Tukey. While Gausss work predated even Fouriers results in 1822, he did not analyze the computation time, between 1805 and 1965, some versions of FFT were published by other authors. Yates in 1932 published his version called interaction algorithm, which provided efficient computation of Hadamard, yates algorithm is still used in the field of statistical design and analysis of experiments. In 1942, Danielson and Lanczos published their version to compute DFT for x-ray crystallography, Cooley and Tukey published a more general version of FFT in 1965 that is applicable when N is composite and not necessarily a power of 2. To analyze the output of these sensors, a fast Fourier transform algorithm would be needed, garwin gave Tukeys idea to Cooley for implementation. Cooley and Tukey published the paper in a short six months
16.
SIMD
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Single instruction, multiple data, is a class of parallel computers in Flynns taxonomy. It describes computers with multiple processing elements that perform the operation on multiple data points simultaneously. Thus, such machines exploit data level parallelism, but not concurrency, there are simultaneous computations, SIMD is particularly applicable to common tasks like adjusting the contrast in a digital image or adjusting the volume of digital audio. Most modern CPU designs include SIMD instructions in order to improve the performance of multimedia use, vector processing was especially popularized by Cray in the 1970s and 1980s. The first era of modern SIMD machines was characterized by massively parallel processing-style supercomputers such as the Thinking Machines CM-1 and these machines had many limited-functionality processors that would work in parallel. Supercomputing moved away from the SIMD approach when inexpensive scalar MIMD approaches based on commodity processors such as the Intel i860 XP became more powerful, the current era of SIMD processors grew out of the desktop-computer market rather than the supercomputer market. Sun Microsystems introduced SIMD integer instructions in its VIS instruction set extensions in 1995, MIPS followed suit with their similar MDMX system. The first widely deployed desktop SIMD was with Intels MMX extensions to the x86 architecture in 1996 and this sparked the introduction of the much more powerful AltiVec system in the Motorola PowerPCs and IBMs POWER systems. Intel responded in 1999 by introducing the all-new SSE system, since then, there have been several extensions to the SIMD instruction sets for both architectures. A modern supercomputer is almost always a cluster of MIMD machines, a modern desktop computer is often a multiprocessor MIMD machine where each processor can execute short-vector SIMD instructions. An application that may take advantage of SIMD is one where the value is being added to a large number of data points. One example would be changing the brightness of an image, each pixel of an image consists of three values for the brightness of the red, green and blue portions of the color. To change the brightness, the R, G and B values are read from memory, a value is added to them, with a SIMD processor there are two improvements to this process. For one the data is understood to be in blocks, instead of a series of instructions saying retrieve this pixel, now retrieve the next pixel, a SIMD processor will have a single instruction that effectively says retrieve n pixels. For a variety of reasons, this can take less time than retrieving each pixel individually. Another advantage is that the instruction operates on all loaded data in a single operation. In other words, if the SIMD system works by loading up eight points at once. Not all algorithms can be vectorized easily, note, Batch-pipeline systems are most advantageous for cache control when implemented with SIMD intrinsics, but they are not exclusive to SIMD features
17.
Superscalar processor
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A superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. It therefore allows for more throughput than would otherwise be possible at a clock rate. A superscalar processor can execute more than one instruction during a cycle by simultaneously dispatching multiple instructions to different execution units on the processor. Each execution unit is not a processor, but an execution resource within a single CPU such as an arithmetic logic unit. In Flynns taxonomy, a superscalar processor is classified as an SISD processor, though many superscalar processors support short vector operations. A multi-core superscalar processor is classified as an MIMD processor, while a superscalar CPU is typically also pipelined, pipelining and superscalar execution are considered different performance enhancement techniques. The Motorola MC88100, the Intel i960CA and the AMD 29000-series 29050 microprocessors were the first commercial single-chip superscalar microprocessors, RISC microprocessors like these were the first to have superscalar execution, because RISC architectures frees transistors and die area which could be used to include multiple execution units. Except for CPUs used in applications, embedded systems, and battery-powered devices. The simplest processors are scalar processors, each instruction executed by a scalar processor typically manipulates one or two data items at a time. By contrast, each executed by a vector processor operates simultaneously on many data items. An analogy is the difference between scalar and vector arithmetic, a superscalar processor is a mixture of the two. Each instruction processes one data item, but there are multiple execution units within each CPU thus multiple instructions can be processing separate data items concurrently, superscalar CPU design emphasizes improving the instruction dispatcher accuracy, and allowing it to keep the multiple execution units in use at all times. This has become important as the number of units has increased. While early superscalar CPUs would have two ALUs and a single FPU, a modern design such as the PowerPC970 includes four ALUs, two FPUs, and two SIMD units. If the dispatcher is ineffective at keeping all of these units fed with instructions, a superscalar processor usually sustains an execution rate in excess of one instruction per machine cycle. In a superscalar CPU the dispatcher reads instructions from memory and decides which ones can be run in parallel, therefore, a superscalar processor can be envisioned having multiple parallel pipelines, each of which is processing instructions simultaneously from a single instruction thread. Available performance improvement from superscalar techniques is limited by three key areas, The degree of parallelism in the instruction stream. The complexity and time cost of dependency checking logic and register renaming circuitry The branch instruction processing, existing binary executable programs have varying degrees of intrinsic parallelism
18.
Modular arithmetic
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In mathematics, modular arithmetic is a system of arithmetic for integers, where numbers wrap around upon reaching a certain value—the modulus. The modern approach to modular arithmetic was developed by Carl Friedrich Gauss in his book Disquisitiones Arithmeticae, a familiar use of modular arithmetic is in the 12-hour clock, in which the day is divided into two 12-hour periods. If the time is 7,00 now, then 8 hours later it will be 3,00. Usual addition would suggest that the time should be 7 +8 =15. Likewise, if the clock starts at 12,00 and 21 hours elapse, then the time will be 9,00 the next day, because the hour number starts over after it reaches 12, this is arithmetic modulo 12. According to the definition below,12 is congruent not only to 12 itself, Modular arithmetic can be handled mathematically by introducing a congruence relation on the integers that is compatible with the operations on integers, addition, subtraction, and multiplication. For a positive n, two integers a and b are said to be congruent modulo n, written, a ≡ b. The number n is called the modulus of the congruence, for example,38 ≡14 because 38 −14 =24, which is a multiple of 12. The same rule holds for negative values, −8 ≡72 ≡ −3 −3 ≡ −8. Equivalently, a ≡ b mod n can also be thought of as asserting that the remainders of the division of both a and b by n are the same, for instance,38 ≡14 because both 38 and 14 have the same remainder 2 when divided by 12. It is also the case that 38 −14 =24 is a multiple of 12. A remark on the notation, Because it is common to consider several congruence relations for different moduli at the same time, in spite of the ternary notation, the congruence relation for a given modulus is binary. This would have been if the notation a ≡n b had been used. The properties that make this relation a congruence relation are the following, if a 1 ≡ b 1 and a 2 ≡ b 2, then, a 1 + a 2 ≡ b 1 + b 2 a 1 − a 2 ≡ b 1 − b 2. The above two properties would still hold if the theory were expanded to all real numbers, that is if a1, a2, b1, b2. The next property, however, would fail if these variables were not all integers, the notion of modular arithmetic is related to that of the remainder in Euclidean division. The operation of finding the remainder is referred to as the modulo operation. For example, the remainder of the division of 14 by 12 is denoted by 14 mod 12, as this remainder is 2, we have 14 mod 12 =2
19.
Circular buffer
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A circular buffer, circular queue, cyclic buffer or ring buffer is a data structure that uses a single, fixed-size buffer as if it were connected end-to-end. This structure lends itself easily to buffering data streams, the useful property of a circular buffer is that it does not need to have its elements shuffled around when one is consumed. In other words, the buffer is well-suited as a FIFO buffer while a standard. Circular buffering makes an implementation strategy for a queue that has fixed maximum size. Should a maximum size be adopted for a queue, then a circular buffer is an ideal implementation. However, expanding a circular buffer requires shifting memory, which is comparatively costly, for arbitrarily expanding queues, a linked list approach may be preferred instead. In some situations, overwriting circular buffer can be used, e. g. in multimedia. If the buffer is used as the buffer in the producer-consumer problem then it is probably desired for the producer to overwrite old data if the consumer is unable to momentarily keep up. Also, the LZ77 family of data compression algorithms operates on the assumption that strings seen more recently in a data stream are more likely to occur soon in the stream. Implementations store the most recent data in a circular buffer, a circular buffer first starts empty and of some predefined length. Whether or not data is overwritten is up to the semantics of the buffer routines or the using the circular buffer. In the pointer-based implementation strategy, the full or empty state can be resolved from the start. When they are equal, the buffer is empty, and when the start is one greater than the end, the buffer is full. When the buffer is instead designed to track the number of inserted elements n, checking for emptiness means checking n =0, a circular-buffer implementation may be optimized by mapping the underlying buffer to two contiguous regions of virtual memory. When the read offset is advanced into the second virtual-memory region, perhaps the most common version of the circular buffer uses 8-bit bytes as elements. Some implementations of the buffer use fixed-length elements that are bigger than 8-bit bytes—16-bit integers for audio buffers, 53-byte ATM cells for telecom buffers. Each item is contiguous and has the correct alignment, so software reading and writing these values can be faster than software that handles non-contiguous. Ping-pong buffering can be considered a very specialized circular buffer with exactly two large fixed-length elements, the Bip Buffer is very similar to a circular buffer, except it always returns contiguous blocks which can be variable length
20.
Floating-point arithmetic
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In computing, floating-point arithmetic is arithmetic using formulaic representation of real numbers as an approximation so as to support a trade-off between range and precision. A number is, in general, represented approximately to a number of significant digits and scaled using an exponent in some fixed base. For example,1.2345 =12345 ⏟ significand ×10 ⏟ base −4 ⏞ exponent, the term floating point refers to the fact that a numbers radix point can float, that is, it can be placed anywhere relative to the significant digits of the number. This position is indicated as the exponent component, and thus the floating-point representation can be thought of as a kind of scientific notation. The result of dynamic range is that the numbers that can be represented are not uniformly spaced. Over the years, a variety of floating-point representations have been used in computers, however, since the 1990s, the most commonly encountered representation is that defined by the IEEE754 Standard. A floating-point unit is a part of a computer system designed to carry out operations on floating point numbers. A number representation specifies some way of encoding a number, usually as a string of digits, there are several mechanisms by which strings of digits can represent numbers. In common mathematical notation, the string can be of any length. If the radix point is not specified, then the string implicitly represents an integer, in fixed-point systems, a position in the string is specified for the radix point. So a fixed-point scheme might be to use a string of 8 decimal digits with the point in the middle. The scaling factor, as a power of ten, is then indicated separately at the end of the number, floating-point representation is similar in concept to scientific notation. Logically, a floating-point number consists of, A signed digit string of a length in a given base. This digit string is referred to as the significand, mantissa, the length of the significand determines the precision to which numbers can be represented. The radix point position is assumed always to be somewhere within the significand—often just after or just before the most significant digit and this article generally follows the convention that the radix point is set just after the most significant digit. A signed integer exponent, which modifies the magnitude of the number, using base-10 as an example, the number 7005152853504700000♠152853.5047, which has ten decimal digits of precision, is represented as the significand 1528535047 together with 5 as the exponent. In storing such a number, the base need not be stored, since it will be the same for the range of supported numbers. Symbolically, this value is, s b p −1 × b e, where s is the significand, p is the precision, b is the base
21.
Harvard architecture
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The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data. The term originated from the Harvard Mark I relay-based computer, which stored instructions on punched tape and these early machines had data storage entirely contained within the central processing unit, and provided no access to the instruction storage as data. Programs needed to be loaded by an operator, the processor could not initialize itself, in a Harvard architecture, there is no need to make the two memories share characteristics. In particular, the width, timing, implementation technology. In some systems, instructions for pre-programmed tasks can be stored in memory while data memory generally requires read-write memory. In some systems, there is much more memory than data memory so instruction addresses are wider than data addresses. Under pure von Neumann architecture the CPU can be either reading an instruction or reading/writing data from/to the memory, both cannot occur at the same time since the instructions and data use the same bus system. In a computer using the Harvard architecture, the CPU can both read an instruction and perform a data memory access at the time, even without a cache. A Harvard architecture computer can thus be faster for a given circuit complexity because instruction fetches, also, a Harvard architecture machine has distinct code and data address spaces, instruction address zero is not the same as data address zero. Instruction address zero might identify a twenty-four bit value, while data address zero might indicate an eight-bit byte that is not part of that twenty-four bit value, the most common modification includes separate instruction and data caches backed by a common address space. While the CPU executes from cache, it acts as a pure Harvard machine, when accessing backing memory, it acts like a von Neumann machine. This modification is widespread in modern processors, such as the ARM architecture and it is sometimes loosely called a Harvard architecture, overlooking the fact that it is actually modified. Another modification provides a pathway between the memory and the CPU to allow words from the instruction memory to be treated as read-only data. This technique is used in some microcontrollers, including the Atmel AVR and this allows constant data, such as text strings or function tables, to be accessed without first having to be copied into data memory, preserving scarce data memory for read/write variables. Special machine language instructions are provided to read data from the instruction memory, in recent years, the speed of the CPU has grown many times in comparison to the access speed of the main memory. Care needs to be taken to reduce the number of main memory is accessed in order to maintain performance. If, for instance, every run in the CPU requires an access to memory. It is possible to make extremely fast memory, but this is only practical for small amounts of memory for cost, power, the solution is to provide a small amount of very fast memory known as a CPU cache which holds recently accessed data
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Von Neumann architecture
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The meaning has evolved to be any stored-program computer in which an instruction fetch and a data operation cannot occur at the same time because they share a common bus. This is referred to as the von Neumann bottleneck and often limits the performance of the system, a stored-program digital computer is one that keeps its program instructions, as well as its data, in read-write, random-access memory. The earliest computing machines had fixed programs, some very simple computers still use this design, either for simplicity or training purposes. For example, a calculator is a fixed program computer. It can do mathematics, but it cannot be used as a word processor or a gaming console. Changing the program of a machine requires rewiring, restructuring. The earliest computers were not so much programmed as they were designed and it could take three weeks to set up a program on ENIAC and get it working. With the proposal of the computer, this changed. A stored-program computer includes, by design, an instruction set, a stored-program design also allows for self-modifying code. One early motivation for such a facility was the need for a program to increment or otherwise modify the address portion of instructions and this became less important when index registers and indirect addressing became usual features of machine architecture. Another use was to embed frequently used data in the stream using immediate addressing. Self-modifying code has largely fallen out of favor, since it is hard to understand and debug. On a large scale, the ability to treat instructions as data is what makes assemblers, compilers, linkers, loaders, one can write programs which write programs. This has allowed a sophisticated self-hosting computing ecosystem to flourish around von Neumann architecture machines, on a smaller scale, some repetitive operations such as BITBLT or pixel & vertex shaders could be accelerated on general purpose processors with just-in-time compilation techniques. This is one use of self-modifying code that has remained popular, in it he described a hypothetical machine which he called a universal computing machine, and which is now known as the Universal Turing machine. The hypothetical machine had a store that contained both instructions and data. Whether he knew of Turings paper of 1936 at that time is not clear, in 1936, Konrad Zuse also anticipated in two patent applications that machine instructions could be stored in the same storage used for data. In planning a new machine, EDVAC, Eckert wrote in January 1944 that they would store data and programs in a new addressable memory device and this was the first time the construction of a practical stored-program machine was proposed
23.
Direct memory access
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Direct memory access is a feature of computer systems that allows certain hardware subsystems to access main system memory, independent of the central processing unit. Without DMA, when the CPU is using programmed input/output, it is fully occupied for the entire duration of the read or write operation. This feature is useful at any time that the CPU cannot keep up with the rate of data transfer, many hardware systems use DMA, including disk drive controllers, graphics cards, network cards and sound cards. DMA is also used for data transfer in multi-core processors. Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without DMA channels, DMA can also be used for memory to memory copying or moving of data within memory. DMA can offload expensive memory operations, such as copies or scatter-gather operations. An implementation example is the I/O Acceleration Technology, Standard DMA, also called third-party DMA, uses a DMA controller. A DMA controller can generate memory addresses and initiate memory read or write cycles and it contains several hardware registers that can be written and read by the CPU. These include an address register, a byte count register. To carry out an input, output or memory-to-memory operation, the host processor initializes the DMA controller with a count of the number of words to transfer, the CPU then sends commands to a peripheral device to initiate transfer of data. The DMA controller then provides addresses and read/write control lines to the system memory, each time a byte of data is ready to be transferred between the peripheral device and memory, the DMA controller increments its internal address register until the full block of data is transferred. In a bus mastering system, also known as a first-party DMA system, where a peripheral can become bus master, it can directly write to system memory without involvement of the CPU, providing memory address and control signals as required. Some measure must be provided to put the processor into a hold condition so that bus contention does not occur, DMA transfers can either occur one byte at a time or all at once in burst mode. In burst mode DMA, the CPU can be put on hold while the DMA transfer occurs, when memory cycles are much faster than processor cycles, an interleaved DMA cycle is possible, where the DMA controller uses memory while the CPU cannot. An entire block of data is transferred in one contiguous sequence, the mode is also called Block Transfer Mode. It is also used to stop unnecessary data, the cycle stealing mode is used in systems in which the CPU should not be disabled for the length of time needed for burst transfer modes. However, in cycle stealing mode, after one byte of data transfer and it is then continually requested again via BR, transferring one byte of data per request, until the entire block of data has been transferred. By continually obtaining and releasing the control of the system bus, the CPU processes an instruction, then the DMA controller transfers one data value, and so on
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Virtual memory
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In computing, virtual memory is a memory management technique that is implemented using both hardware and software. It maps memory addresses used by a program, called virtual addresses, main storage as seen by a process or task appears as a contiguous address space or collection of contiguous segments. The operating system virtual address spaces and the assignment of real memory to virtual memory. Address translation hardware in the CPU, often referred to as a management unit or MMU. Memory virtualization can be considered a generalization of the concept of virtual memory, virtual memory is an integral part of a modern computer architecture, implementations usually require hardware support, typically in the form of a memory management unit built into the CPU. While not necessary, emulators and virtual machines can employ hardware support to increase performance of their virtual memory implementations, during the 1960s and early 70s, computer memory was very expensive. The introduction of virtual memory provided an ability for software systems with large memory demands to run on computers with less real memory, the savings from this provided a strong incentive to switch to virtual memory for all systems. The additional capability of providing virtual address spaces added another level of security and reliability, most modern operating systems that support virtual memory also run each process in its own dedicated address space. Each program thus appears to have access to the virtual memory. However, some operating systems and even modern ones are single address space operating systems that run all processes in a single address space composed of virtualized memory. This is because embedded hardware costs are kept low by implementing all such operations with software rather than with dedicated hardware. In the 1940s and 1950s, all larger programs had to contain logic for managing primary and secondary storage, virtual memory was therefore introduced not only to extend primary memory, but to make such an extension as easy as possible for programmers to use. To allow for multiprogramming and multitasking, many early systems divided memory between multiple programs without virtual memory, such as models of the PDP-10 via registers. The first Atlas was commissioned in 1962 but working prototypes of paging had been developed by 1959, in 1961, the Burroughs Corporation independently released the first commercial computer with virtual memory, the B5000, with segmentation rather than paging. Before virtual memory could be implemented in operating systems, many problems had to be addressed. Dynamic address translation required expensive and difficult to build specialized hardware, there were worries that new system-wide algorithms utilizing secondary storage would be less effective than previously used application-specific algorithms. The first minicomputer to introduce virtual memory was the Norwegian NORD-1, during the 1970s, other minicomputers implemented virtual memory, virtual memory was introduced to the x86 architecture with the protected mode of the Intel 80286 processor, but its segment swapping technique scaled poorly to larger segment sizes. The Intel 80386 introduced paging support underneath the existing segmentation layer, however, loading segment descriptors was an expensive operation, causing operating system designers to rely strictly on paging rather than a combination of paging and segmentation
25.
Process (computing)
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In computing, a process is an instance of a computer program that is being executed. It contains the code and its current activity. Depending on the system, a process may be made up of multiple threads of execution that execute instructions concurrently. A computer program is a collection of instructions, while a process is the actual execution of those instructions. Several processes may be associated with the program, for example. Multitasking is a method to allow processes to share processors. Each CPU executes a task at a time. However, multitasking allows each processor to switch between tasks that are being executed without having to wait for each task to finish. Depending on the system implementation, switches could be performed when tasks perform input/output operations. A common form of multitasking is time-sharing, time-sharing is a method to allow fast response for interactive user applications. In time-sharing systems, context switches are performed rapidly, which makes it seem like multiple processes are being executed simultaneously on the same processor and this seeming execution of multiple processes simultaneously is called concurrency. In general, a system process consists of the following resources. Memory, which includes the code, process-specific data, a call stack. Operating system descriptors of resources that are allocated to the process, such as file descriptors or handles, security attributes, such as the process owner and the process set of permissions. Processor state, such as the content of registers and physical memory addressing, the state is typically stored in computer registers when the process is executing, and in memory otherwise. The operating system holds most of this information about processes in data structures called process control blocks. Any subset of the resources, typically at least the processor state, the operating system keeps its processes separate and allocates the resources they need, so that they are less likely to interfere with each other and cause system failures. The operating system may also provide mechanisms for communication to enable processes to interact in safe
26.
Memory management unit
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It is usually implemented as part of the central processing unit, but it also can be in the form of a separate integrated circuit. An MMU effectively performs virtual memory management, handling at the same memory protection, cache control, bus arbitration and, in simpler computer architectures. Modern MMUs typically divide the address space into pages, each having a size which is a power of 2, usually a few kilobytes. The bottom bits of the address are left unchanged, the upper address bits are the virtual page numbers. Most MMUs use a table of items called a page table, containing one page table entry per page. An associative cache of PTEs is called a translation lookaside buffer and is used to avoid the necessity of accessing the main memory every time a virtual address is mapped, other MMUs may have a private array of memory or registers that hold a set of page table entries. The physical page number is combined with the offset to give the complete physical address. A PTE may also include information about whether the page has been written to, when it was last used, what kind of processes may read and write it, and whether it should be cached. Sometimes, a PTE prohibits access to a page, perhaps because no physical random access memory has been allocated to that virtual page. In this case, the MMU signals a page fault to the CPU, the operating system then handles the situation, perhaps by trying to find a spare frame of RAM and set up a new PTE to map it to the requested virtual address. If no RAM is free, it may be necessary to choose an existing page, using some replacement algorithm, with some MMUs, there can also be a shortage of PTEs, in which case the OS will have to free one for the new mapping. Typically, an operating system assigns each program its own address space. An MMU also mitigates the problem of fragmentation of memory, after blocks of memory have been allocated and freed, the free memory may become fragmented so that the largest contiguous block of free memory may be much smaller than the total amount. With virtual memory, a range of virtual addresses can be mapped to several non-contiguous blocks of physical memory. Later microprocessors placed the MMU together with the CPU on the integrated circuit, as did the Intel 80286. While this article concentrates on modern MMUs, commonly based on pages and those are occasionally also present on modern architectures. The x86 architecture provided segmentation, rather than paging, in the 80286, most modern systems divide memory into pages that are 4-64 KB in size, often with the capability to use huge pages from 2 MB to 1 GB in size. Page translations are cached in a translation lookaside buffer, some systems, mainly older RISC designs, trap into the OS when a page translation is not found in the TLB
27.
Address generation unit
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Address generation unit, sometimes also called address computation unit, is an execution unit inside central processing units that calculates addresses used by the CPU to access main memory. Those address-generation calculations involve different integer arithmetic operations, such as addition, subtraction, modulo operations, often, calculating a memory address involves more than one general-purpose machine instruction, which do not necessarily decode and execute quickly. Capabilities of an AGU depend on a particular CPU and its architecture, thus, some AGUs implement and expose more address-calculation operations, while some also include more advanced specialized instructions that can operate on multiple operands at a time. Computer Architecture, September 2013, by Ian Wienand
28.
AMD Am2900
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Am2900 is a family of integrated circuits created in 1975 by Advanced Micro Devices. They were constructed with bipolar devices, in a bit-slice topology, by using a bit slicing technique, Am2900 family was able to implement a CCU with data, addresses, and instructions to be any multiple of 4 bits by multiplying the number of ICs. One major problem with this technique was it required a larger amount of ICs to implement what could be done on a single CPU IC. The Am2901 chip was the unit, and the core of the series. It could count using 4 bits and implement binary operations as well as various bit-shifting operations, in the Soviet Union and later Russia the Am2900 family was manufactured as the 1804 series which was still in production as of 2016. There are probably more, but here are some known machines using these parts, The Apollo Computer Tern family. All used the system board emulating the Mc68010 instruction set. Four special instructions were added to the Galileo version of the ATAC, Data General Nova 4, which obtained 16-bit word width using four Am2901 ALUs in parallel, one of the boards had 15 Am2901 ALUs on it. Digital Equipment Corporation PDP-11 models PDP-11/23, PDP-11/34, and PDP-11/44 floating-point options The Xerox Dandelion, several models of the GEC4000 series minicomputers,4060,4150,4160, and 4090 and all 418x and 419x systems. The UCSD Pascal P-machine processor designed at NCR by Joel McCormack, a number of MAI Basic Four machines. The Tektronix 4052 graphics system computer, the SM-1420, Soviet clone of PDP-11, used Soviet clone of AM2901 perhaps also used in others. The Lilith computer designed at ETH Zürich by Niklaus Wirth, ataris vector graphics arcade machines Tempest, Battlezone, and Red Baron each used 4 Am2901 ICs in their math box auxiliary circuit boards. The Sim-X machine used a 16-bit integer multiplier to optimize graphical transformations, the machine debuted in 1983 and the company shut down in 1987. Eventide H949 Harmonizer, four Am2901 chips are used to generate addresses, many Siemens Teleperm and S5 PLCs used for industrial control were built using the 2900 series. Metheus / Barco Omega 400 and 500 Series graphics systems, four Am2901 chips were used to perform operations on this 1982 display processor. Geac Computer Corporation 2000,6000,8000, and 9000 were all based on 4 x AM2901 chips, the GEAC9500 was based on the AM29101. The GEAC2000 was used in pharmacies, the other models were used in library, banking, and insurance automation. The 2000 was a single processor unit, the 6000 and 8000 contained four processors, each dedicated to one of comms, disk, tape, or program processing
29.
TRW Inc.
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TRW Inc. was an American corporation involved in a variety of businesses, mainly aerospace, automotive, and credit reporting. It was a pioneer in multiple fields including electronic components, integrated circuits, computers, software, TRW built many spacecraft, including Pioneer 1, Pioneer 10, and several space-based observatories. It was #57 on the Fortune 500 list, and had 122,258 employees, tRW’s roots were founded in 1901, and it lasted for more than a century until being acquired by Northrop Grumman in 2002. Persons coming from TRW were important to build up corporations like SpaceX, in 1953, the company was recruited to lead the development of the United States first ICBM. Starting with the design by Convair, the multi-corporate team launched Atlas in 1957. It flew its full range in 1958, and was adapted to fly the Mercury astronauts into orbit, TRW also led development of the Titan missile, which was later adapted to fly the Gemini missions. The company served the US Air Force as systems engineers on all subsequent ICBM development efforts, in 1960, Congress spurred the formation of the non-profit Aerospace Corporation to provide systems engineering to the US government, but TRW continued to guide the ICBM efforts. TRW originated in 1901 with the Cleveland Cap Screw Company, founded by David Kurtz and their initial products were bolts with heads electrically welded to the shafts. In 1904, a welder named Charles E. Thompson adapted their process to making automobile engine valves, and, by 1915, Charles Thompson was named General Manager of the company, which became Thompson Products in 1926. Their experimental hollow sodium-cooled valves aided Charles Lindberghs solo flight across the Atlantic, in 1937, Thompson Motor Products bought J. A. Drake and Sons. The company made high performance valves that were used in racing engines of the day. Dale Drake bought the Offy engine design with his partner Louis Meyer in 1946 and won the Indianapolis 500 twenty-seven times, more than any other engine design. During the period leading up to World War II, through the end of the Korean war, Thompson Products was a key manufacturer of component parts for aircraft engines, including aircraft valves. The TAPCO plant, owned by the U. S. Government and it employed over 16,000 workers at the peak of WW II production. They grew frustrated with Howard Hughes’ management, and formed the Ramo-Wooldridge Corporation in September 1953, the detonation of a thermonuclear bomb by the Soviet Union spurred Trevor Gardner to form the Teapot Committee in October 1953. Chaired by John von Neumann, its purpose was to study the development of ballistic missiles, Ramo and Wooldridge were committee members, and Ramo-Wooldridge Corp. became the lead contractor of the resulting ICBM development effort, reporting to the United States Air Force. With continued backing from Thompson Products, Ramo-Wooldridge diversified into computers and electronic components and they also produced scientific spacecraft such as Pioneer 1. Thompson Products and Ramo-Wooldridge merged in October 1958 to form Thompson Ramo Wooldridge Inc. unofficially known as TRW, in February 1959, Jimmy Doolittle became Chairman of the Board of Space Technology Laboratories, the division which continued to support the Air Force ICBM efforts
30.
Speak & Spell (toy)
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The Speak & Spell was named an IEEE Milestone in 2009. The Speak & Spell was created by a team of engineers led by Paul Breedlove, himself an engineer. Development began in 1976 with an budget of $25,000. Additional purchased cartridges could be inserted through the receptacle to provide new solid-state libraries. This represented the first time an educational toy utilized speech that was not recorded on tape or phonograph record, the original Speak & Spell was the first of a three-part talking educational toy series that also included Speak & Read and Speak & Math. This series was a subset of TIs Learning Center product group and the Speak & Spell was released simultaneously with the Spelling B, the Speak & Spell was sold, with regional variations, in the United States, Canada, Australia, in Europe, and Japan. The toy was originally advertised as a tool for helping children ages 7 and up to learn to spell and it shipped without a cartridge, in this configuration called simply the Basic Unit. Between its release and 1983, the Speak & Spell was redesigned twice under the name Speak & Spell. It was completely recreated in 1982 as the Speak & Spell Compact, between 1989 and 1992 the Super Speak & Spell would see three redesigns as well. The 1992 Super Speak & Spell would mark the last release of the series, regional variations with different speech libraries and different games were released in at least 9 countries with seven language variations. In 1980, the original Speak & Spell was redesigned to give it a membrane keyboard in place of raised buttons. Outside of the United States, the 1980 release was marketed in the United Kingdom under the name, in German as the Buddy. In 1982, the Speak & Spell Compact was released at about half the size of the Speak & Spell, the Speak & Spell Compact was a dedicated console and only one other version, the Speak & Write, was released for English markets. Speak & Spell Compact sales were poor in the United States. UK Marketing Manager Martin Finn had the product retitled for the UK, in 1983, the Speak & Spell was again redesigned. The change was even more minute, however, representing nothing more substantial than a redesign of the faceplate graphics. This version was marketed first in Italian as Grillo Parlante, and then later in the United States and the United Kingdom as the Speak & Spell, the Super Speak & Spell was released in 1989 with a number of major changes. The display screen was changed to an LCD screen instead of the former VFD screen, the keyboard layout was also altered to match the standard QWERTY keyboard rather than the ABC keyboard
31.
Texas Instruments LPC Speech Chips
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The Texas Instruments LPC Speech Chips are a series of speech synthesizer digital signal processor integrated circuits created by Texas Instruments beginning in 1978. They continued to be developed and marketed for years, though the speech department moved around several times within TI until finally dissolving in late 2001. The rights to the subset of the MSP line, the last remaining line of TI speech products as of 2001, were sold to Sensory. Speech data is stored through pitch-excited linear predictive coding, where words are created by a lattice filter, linear predictive coding achieves a vast reduction in data volume needed to recreate intelligible speech data. The TMC0280/TMS5100 was the first self-contained LPC speech synthesizer IC ever made and it was designed for Texas Instruments by Larry Brantingham, Paul S. Breedlove, Richard H. Wiggins, and Gene A. Frantz and its silicon was laid out by Larry Brantingham. The chip was designed for the Spelling Bee project at TI, a speech-less Spelling B was released at the same time as the Speak & Spell. All TI LPC speech chips until the TSP50cxx series used PMOS architecture, Chips in the TI LPC speech series were labeled as TMCxxxx or CDxxxx when used by TIs consumer product division, or labeled as TMS5xxx when sold to 3rd parties. 1978 TMS5100, First LPC speech chip, Used a custom 4-bit serial interface using TMS6100 or TMS6125 mask ROM ICs, used on all non-super versions of the Speak & Spell except for the 1980 UK version, which used the TMC0280/CD2801 below. It was also used on the Byron Petite Electronic Talking Typewriter toy, superseded in 1979 by TMS5100A and TMS5110. 1980 TMC0280 AKA CD2801, Used in the Speak & Math, Speak & Read, pin, but not function compatible with TMS5100/TMC0280, has a different LPC and slightly different Chirp table. The CD2801/Die revision F fixes an interpolator bug, very minor differences in function, uses die rev F, fixing a bug in the interpolator. Used on the Century Video System arcade platform, pin, but not function compatible with TMS5100. It was used in the Monkgomery puppet toy made by Hasbro, an SDIP version of this chip was sold at some point as the TMS5111. Superseded by TMS5220 in late 1980/1981, and possibly sold as cheap, cD2802, A version of the TMS5100/5110 with different LPC and Chirp tables, not the same as either the TMS5100 or TMS5110. Used on the Touch and Tell only, never sold outside of the company, uses its own, unique, chirp table. TMS5110A, Die shrink of TMS5110, pin and function compatible, Used on at least two home computer products. It was used on the arcade game Bagman by Valadon Automation, by Omnicron Electronics on the TCC-14 Talking Clock/Calendar, Used on the Chrysler Electronic Voice Alert vehicle monitoring system. Arcade games, including Star Wars, Firefox, Return of the Jedi, Road Runner, later Atari arcade games used the TMS5220C, see below
