The POWER5 is a microprocessor developed and fabricated by IBM. It is an improved version of the POWER4; the principal improvements are support for simultaneous multithreading and an on-die memory controller. The POWER5 is a dual-core microprocessor, with each core supporting one physical thread and two logical threads, for a total of two physical threads and four logical threads. Technical details of the microprocessor were first presented at the 2003 Hot Chips conference. A more complete description was given at Microprocessor Forum 2003 on 14 October 2003; the POWER5 was not sold and was used by IBM and their partners. Systems using the microprocessor were introduced in 2004; the POWER5 competed in the high-end enterprise server market against the Intel Itanium 2 and to a lesser extent, the Sun Microsystems UltraSPARC IV and the Fujitsu SPARC64 V. It was superseded in 2005 by an improved iteration, the POWER5+; the POWER5 is a further development of the POWER4. The addition of two-way multithreading required the duplication of the return stack, program counter, instruction buffer, group completion unit and store queue so that each thread may have its own.
Most resources, such as the register files and execution units, are shared, although each thread sees its own set of registers. The POWER5 implements simultaneous multithreading; the POWER5 can disable SMT to optimize for the current workload. As many resources such as the register files are shared by two threads, they are increased in capacity in many cases to compensate for the loss of performance; the number of integer and floating-point registers is increased to 120 each, from 80 integer and 72 floating-point registers in the POWER4. The floating-point instruction cache is increased in capacity to 24 entries from 20; the capacity of the L2 unified cache was increased to the set-associativity to 10-way. The unified L3 cache was brought on-package instead of located externally in separate chips, its capacity was increased to 36 MB. Like the POWER4, the cache is shared by the two cores; the cache is accessed via two unidirectional 128-bit buses operating at half the core frequency. The on-die memory controller supports up to 64 GB of DDR2 memory.
It uses high-frequency serial buses to communicate with external buffers that interface the dual inline memory modules to the microprocessor. The POWER5 contains 276 million transistors and has an area of 389 mm2, it is fabricated by IBM in a 0.13 µm silicon on insulator complementary metal–oxide–semiconductor process with eight layers of copper interconnect. The POWER5 die is packaged in either a multi-chip module; the DCM contains one POWER5 die and its associated L3 cache die. The MCM contains four POWER5 dies and four L3 cache dies, one for each POWER5 die, measures 95 mm by 95 mm. Several POWER5 processors in high-end systems can be coupled together to act as a single vector processor by a technology called ViVA; the POWER5+ is an improved iteration of the POWER5 introduced on 4 October 2005. Improvements were lower power consumption, due to the newer process it was fabricated in; the POWER5+ chip uses a 90 nm fabrication process. This resulted in the die size decrease from 389 mm2 to 243 mm2.
Clock frequency remained between at 1.5 to 1.9 GHz. On 14 February 2006, new versions raised the clock frequency to 2.2 GHz and to 2.3 GHz on 25 July 2006. The POWER5+ was packaged in the same packages as previous POWER5 microprocessors, but was available in a quad-chip module containing two POWER5+ dies and two L3 cache dies, one for each POWER5+ die; these QCM chips ran at a clock frequency of between 1.8 GHz. IBM uses the DCM and MCM POWER5 microprocessors in its System p and System i server families, in its DS8000 storage server, as embedded microprocessors in its high-end Infoprint printers. DCM POWER5 microprocessors are used by IBM in its high-end IntelliStation POWER 285 workstation. Third-party users of POWER5 microprocessors are Groupe Bull, in its Escala servers, Hitachi, in its SR11000 computers with up to 128 POWER5+ microprocessors, which have several installations featured in the 2007 TOP500 list of supercomputers. IBM uses the POWER5 + in its System p5 520Q, 550Q and 560Q servers.
IBM System p IBM POWER microprocessors PowerPC POWER6 "IBM Previews Power5".. Microprocessor Report. Clabes, Joachim et al.. "Design and Implementation of the POWER5 Microprocessor". Proceedings of 2004 IEEE International Solid-State Circuits Conference. Glaskowsky, Peter N.. "IBM Raises Curtain on Power5". Microprocessor Report. Kalla, Ron. "IBM Power5 Chip: A Dual-Core Multithreaded Processor". IEEE Micro. Krewell, Kevin. "Power5 Tops On Bandwidth". Microprocessor Report. Sinharoy, Balaram et al.. "POWER5 System Microarchitecture". IBM Journal of Research and Development. Vance, Ashlee. "IBM pumps Unix line full of Power5+". The Register. Sizing up the Super Heavyweights, a comparison and analysis of the POWER5 and Montecito, that explains the major changes between the POWER4 to the POWER5, along with performance estimates A High-Performance IBM Power5+ p5-575 Cluster 1600 and DDN S2A9550 Storage, Texas A&M University
PureSystems is an IBM product line of factory pre-configured components and servers being referred to as an "Expert Integrated System". The centrepiece of PureSystems is the IBM Flex System Manager in tandem with the so-called "Patterns of Expertise" for the automated configuration and management of PureSystems. PureSystems can host four different operating systems and five hypervisors on two different instruction set architectures: Power ISA and x86. PureSystems is marketed as a converged system, which packages multiple information technology components into a single product; the architecture itself is called IBM Flex System. It aims at managing hybrid cloud infrastructure environments "out of the box"; the basic intention is for the combination of integrated hardware and software that can be maintained. A similar concept had been introduced with the IBM AS/400. Today, such systems are called converged systems. More specialized integrated hardware and software are referred to as appliances; the compute nodes of the server blades can be x86 or Power ISA and they can be used either individually or mixed in the same rack thus offering a hybrid ensemble which borrows from the zEnterprise/zBX ensemble, including its ability to manage a combined physical/virtual hybrid environment from a single console.
PureSystems is shipped with the IBM Flex System Manager. It is an appliance which manages the resources according to the so-called "Patterns of Expertise", which provide field engineers' expertise from decades of system configuration; these "Patterns of Expertise" offer industry-specific defaults for the automatic and optimal orchestration of resources. PureApplication uses in conjunction with the IBM System Manager first Flex repeatable software patterns and industry-specific processes, which are derived from the year-long collaboration of IBM with their customers and business partners; the basic building block of the system is the 10U high Flex Enterprise system chassis with 14 bays in the front for compute nodes and storage nodes. Additionally, there are bays in the rear for I/O modules. A flex-chassis can accommodate up to 14 horizontal compute and storage nodes in the front, 4 vertically oriented switch modules in the rear. Contrasting to this, the IBM BladeCenter has vertically oriented compute nodes.
This means that the components between the BladeCenter chassis and Flex chassis are not interchangeable. Based upon the Flex Systems architecture, there are three main products: PureFlex System PureApplication System PureData System PureFlex is a factory pre-configured and combined hardware-/software system for IaaS in terms of cloud computing, it combines server and storage. IBM PureFlex is available in three configurations: Express, Enterprise. PureApplication is a pre-configured platform for platform as a service applications, it is optimized for transaction-oriented database applications. PureApplication comes with IBM DB2 database and WebSphere Application Server pre-configured so users can run their applications into a preconfigured middleware engine. Unlike PureFlex, sold by IBM Systems and Technology Group, PureApplication is marketed by the IBM Software Group. IBM claims; the system's virtual pattern deployers encrypt on-disk data using Security First Corp's SPxBitFiler-IPS encryption technology, licensed by IBM for its Cloud Data Encryption Service.
IBM PureApplication System is available in three classes: W1500-32 and W1500-64, using Intel Xeon E5-2670 processors, housed in a 25U rack W1500-96 through to W1500-608, using Intel Xeon E5-2670 processors, housed in a 42U rack W1700-96 through to W1700-608, using IBM POWER7+ processors, housed in a 42U rack PureData Systems takes the approach of PureApplication a step further being a coupled and specialized computer appliance and software appliance, the latter supporting both Oracle and DB2. It is thence marketed by a brand of IBM Software Group. PureData is focused at three main tasks within enterprise computing: business intelligence, near real-time data analysis and online transactional processing, it comes in four flavours: PureData Systems for Transactions PureData Systems for Analytics PureData Systems for Operational Analytics PureData Systems for HadoopPureData System for Transactions is a reliable and scalable database platform. It is aimed at e-commerce [i.e. retail and credit card processing environments) which depends on rapid handling of transactions and interactions.
These transactions are small in size, but their sheer volume and frequency require a specialized environment. The new system can provide 5x performance improvement through advances in high performance storage. PureData System for Analytics builds on Netezza technology and it is aimed at business intelligence that entails huge queries with complex algorithms, it provides a large library of database analytical functions for data warehouse applications, can scale across the terabyte or petabytes running on the system. It can support high volume high speed analytics for clients. PureData Systems for Operational Analytics is an operational warehouse system which supports real-time decision making. In contrast to PureData System for A
IBM Power Systems
Power Systems is a family of server computers from IBM that are based on its POWER processors. Before the Power Systems line was announced on April 2, 2008, IBM had two distinct POWER processor-based lines: the System i running IBM i – and the System p series running AIX or Linux. IBM had two distinct POWER- and PowerPC-based hardware lines since the early 1990s: Servers running processors based on the IBM PowerPC-AS architecture in the AS/400 family, running OS/400 Servers and workstations using IBM POWER and PowerPC microprocessors in the RS/6000 family, running IBM AIX and Linux, they merged to use the same hardware platform in 2001/2002 with the introduction of the POWER4 processor. After that, there was little difference between both the "i" hardware. With the introduction of the POWER5 processor in 2004 the product numbering was synchronized; the System i5 570 was identical to the System p5 570. In April 2008, IBM merged the two lines of servers and workstations under the same name, Power Systems, with identical hardware and a choice of operating systems and service contracts.
In February 2010, IBM announced new models with the new POWER7 microprocessor. IBM Power Systems models: 2008/2009 BladeCenter JS12 Express BladeCenter JS22 Express BladeCenter JS23 Express BladeCenter JS43 Express Power 520 Express Power 550 Express Power 560 Express Power 570 Power 575 Power 595 2010 BladeCenter PS700 Express BladeCenter PS701 Express BladeCenter PS702 Express Power 710 Express Power 720 Express Power 730 Express Power 740 Express Power 750 Express Power 755 – for high-performance computing Power 770 Power 780 Power 795 2011 Power 775 – known as PERCS 2012 Flex System p260 Flex System p460 Flex System p24L 2014 Power Systems S812L Power Systems S822 and S822L Power Systems S814 Power Systems S824 and S824L Power Systems E870 Power Systems E880 2015 Power Systems E850 Power Systems S812L Power Systems S822LC IBM BladeCenter PureSystems Linux on Power Power Systems – IBM.com IBM Power Systems Redbooks It's Official: Now We're Power Systems and i for Business – ITjungle.com IBM: i + p = Power – Cnet.com Hardware, OS Get New Names--And That's a Good Thing – IBM Systems Magazine.com IBM IT Infrastructure web page IBM Systems Power Systems Magazine
Forschungszentrum Jülich is a member of the Helmholtz Association of German Research Centres and is one of the largest interdisciplinary research centres in Europe. It was founded on 11 December 1956 by the state of North Rhine-Westphalia as a registered association, before it became "Kernforschungsanlage Jülich GmbH" or Nuclear Research Centre Jülich in 1967. In 1990, the name of the association was changed to "Forschungszentrum Jülich GmbH", it has close collaborations with RWTH Aachen in the form of Jülich-Aachen Research Alliance. Forschungszentrum Jülich is situated in the middle of the Stetternich Forest in Jülich and covers an area of 2.2 square kilometres. The annual budget of Forschungszentrum Jülich is € 530 million. Public funds are split between the German Federal Government and the Federal State of North Rhine-Westphalia. Forschungszentrum Jülich employs more than 5,700 members of staff and works within the framework of the disciplines physics, biology and engineering on the basic principles and applications in the areas of health, information and energy.
Amongst the members of staff, there are approx. 1,500 scientists including 400 PhD students and 130 diploma students. Around 600 people work in the administration and service areas, 500 work for project management agencies, there are 1,600 technical staff members, while around 330 trainees are completing their training in more than 20 different professions. More than 800 visiting scientists come to Forschungszentrum Jülich every year from about 50 different countries. In 2003, 367 people were trained in 20 different professions at Forschungszentrum Jülich; the proportion of trainees lies around 9% and is more than twice as high as the German national average. In cooperation with RWTH Aachen University and Aachen University of Applied Sciences, Forschungszentrum Jülich offers combined practical and academic courses. After they have completed their exams, graduates are offered six months employment in their chosen profession. Between 1959 and 2007 around 3,800 trainees completed their training in more than 25 different professions.
No lectures are held at Forschungszentrum Jülich itself, but in line with the so-called "Jülich model", the directors of the institutes are appointed professors at nearby universities in a joint procedure with the Federal State of North Rhine-Westphalia. By holding a lectureship there, they can fulfil their teaching duties. Many other scientists at Forschungszentrum Jülich who have achieved habilitation undertake lectureships in the nearby universities. In cooperation with the universities, what are known as "research schools" are founded in an effort to support the scientific training of students. An exception to this is the training of mathematical-technical software developers. In cooperation with Aachen University of Applied Sciences, the lectures required for the B. Sc. in "Applied Mathematics and Computer Science" are held in the Central Institute for Applied Mathematics by university professors and ZAM instructors. For the subsequent M. Sc. in "Technomathematics", the same model applies and some of the lectures are held by ZAM staff.
Every year, Forschungszentrum Jülich hosts a two-week IFF Summer School, which addresses current issues in solid-state physics. Forschungszentrum Jülich is organised into 8 institutes, 4 central divisions, 2 programme groups, 2 projects and 2 project management organizations Project Management Jülich Project Management Organization "Energy, Sustainability" The bodies of Forschungszentrum Jülich are: the Partners' Meeting the Supervisory Board the Board of Directors, made up of Prof. Dr.-Ing. Wolfgang Marquardt Karsten Beneke Prof. Dr. Sebastian M. Schmidt Prof. Dr. Dr. Hans-Harald Bolt Committees of Forschungszentrum Jülich are: the Scientific Advisory Council the Scientific and Technical Council Research at Jülich is divided into four research areas: health, information and energy; the key competencies of physics and scientific computing provide the basis for world-class research in these areas. Institutes:Institute for Advanced Simulation Institute of Bio- and Geosciences Institute of Complex Systems Institute of Energy and Climate Research Institute of Neuroscience and Medicine Jülich Centre for Neutron Science Nuclear Physics Institute Peter Grünberg Institute COSY is a particle accelerator and storage ring for accelerating protons and deuterons operated by the Institute of Nuclear Physics at Forschungszentrum Jülich.
COSY is characterised by what is known as beam cooling, which reduces the deviation of particles from their predetermined path using electron or stochastic cooling. At COSY there are a number of experimental facilities for studies in the field of hadron physics; these include the ANKE magnetic spectrometer, the TOF flight spectrometer and the WASA universal detector, moved to COSY from the CELSIUS storage ring of The Svedberg Laboratoriet in Uppsala, Sweden in 2005. COSY is one of the only accelerators in the medium energy range with both electron cooling and stochastic cooling. Th
IBM POWER microprocessors
IBM has a series of high performance microprocessors called POWER followed by a number designating generation, i.e. POWER1, POWER2, POWER3 and so forth up to the latest POWER9; these processors have been used by IBM in their RS/6000, AS/400, pSeries, iSeries, System p, System i and Power Systems line of servers and supercomputers. They have been used in data storage devices by IBM and by other server manufacturers like Bull and Hitachi; the name "POWER" was presented as an acronym for "Performance Optimization With Enhanced RISC". The POWERn family of processors were developed in the late 1980s and are still in active development nearly 30 years later. In the beginning, they utilized the POWER instruction set architecture, but that evolved into PowerPC in generations and to Power ISA, so modern POWER processors do not use the POWER ISA, they use the Power ISA. In 1974 IBM started a project to build a telephone switching computer with, for the time, immense computational power. Since the application was comparably simple, this machine would need only to perform I/O, add register-register, move data between registers and memory, would have no need for special instructions to perform heavy arithmetic.
This simple design philosophy, whereby each step of a complex operation is specified explicitly by one machine instruction, all instructions are required to complete in the same constant time, would come to be known as RISC. When the telephone switch project was cancelled IBM kept the design for the general purpose processor and named it 801 after building #801 at Thomas J. Watson Research Center. By 1982 IBM continued to explore the superscalar limits of the 801 design by using multiple execution units to improve performance to determine if a RISC machine could maintain multiple instructions per cycle. Many changes were made to the 801 design to allow for multiple execution units and the Cheetah processor had separate branch prediction, fixed-point, floating-point execution units. By 1984 CMOS was chosen since it allowed an increase in the level of circuit integration while improving transistor-logic performance. In 1985, research on a second-generation RISC architecture started at the IBM Thomas J. Watson Research Center, producing the "AMERICA architecture".
This was to become the first POWER processors using the first POWER ISA. In February 1990, the first computers from IBM to incorporate the POWER ISA were called the "RISC System/6000" or RS/6000; these RS/6000 computers were divided into two classes and servers, hence introduced as the POWERstation and POWERserver. The RS/6000 CPU had 2 configurations, called the "RIOS-1" and "RIOS.9". A RIOS-1 configuration had a total of 10 discrete chips — an instruction cache chip, fixed-point chip, floating-point chip, 4 data L1 cache chips, storage control chip, input/output chips, a clock chip; the lower cost RIOS.9 configuration had 8 discrete chips—an instruction cache chip, fixed-point chip, floating-point chip, 2 data cache chips, storage control chip, input/output chip, a clock chip. The POWER1 is the first microprocessor that used register out-of-order execution. A simplified and less powerful version of the 10 chip RIOS-1 was made in 1992 was developed for lower-end RS/6000s, it used only one chip and was called "RISC Single Chip" or RSC.
RIOS-1 – the original 10-chip version RIOS.9 – a less powerful version of RIOS-1 POWER1+ – a faster version of RIOS-1 made on a reduced fabrication process POWER1++ – an faster version of RIOS-1 RSC – a single-chip implementation of RIOS-1 RAD6000 – a radiation-hardened version of the RSC was made available for use in space. By adding a second fixed-point unit, a second powerful floating point unit, other performance enhancements and new instructions to the design, the POWER2 ISA had leadership performance when it was announced in November 1993; the POWER2 was a multi-chip design, but IBM made a single chip design of it, called the POWER2 Super Chip or P2SC that went into high performance servers and supercomputers. At the time of its introduction in 1996, the P2SC was the largest processor with the highest transistor count in the industry and was a leader in floating point operations. POWER2 – 6 to 8 chips were mounted on a ceramic multi chip module POWER2+ – a cheaper 6-chip version of POWER2 with support for external L2 caches P2SC – a faster and single chip version of POWER2 P2SC+ – an faster version or P2SC due to reduced fabrication process In 1991, Apple looked for a future alternative to Motorola's 68000-based CISC platform, Motorola experimented with a RISC platform of its own, the 88000.
IBM joined the discussion and the three founded the AIM alliance to build the PowerPC ISA based on the POWER ISA, but with additions from both Apple and Motorola. It was to be a complete 32/64 bit RISC architecture, with a promise to range from low end embedded microcontrollers to the high end supercomputer and server applications. After two years of development, the resulting PowerPC ISA was introduced in 1993. A modified version of the RSC architecture, PowerPC added single-precision floating point instructions and general register-to-register multiply and divide instructions, removed some POWER features, it added a 64-bit version of the ISA and support for SMP. In 1990, IBM wanted to merge the low end server and mid range server architectures, the RS/6000 RISC ISA and AS/400 CISC ISA into one common RISC ISA that could host both IBM's AIX and OS/400 operating sys
Random-access memory is a form of computer data storage that stores data and machine code being used. A random-access memory device allows data items to be read or written in the same amount of time irrespective of the physical location of data inside the memory. In contrast, with other direct-access data storage media such as hard disks, CD-RWs, DVD-RWs and the older magnetic tapes and drum memory, the time required to read and write data items varies depending on their physical locations on the recording medium, due to mechanical limitations such as media rotation speeds and arm movement. RAM contains multiplexing and demultiplexing circuitry, to connect the data lines to the addressed storage for reading or writing the entry. More than one bit of storage is accessed by the same address, RAM devices have multiple data lines and are said to be "8-bit" or "16-bit", etc. devices. In today's technology, random-access memory takes the form of integrated circuits. RAM is associated with volatile types of memory, where stored information is lost if power is removed, although non-volatile RAM has been developed.
Other types of non-volatile memories exist that allow random access for read operations, but either do not allow write operations or have other kinds of limitations on them. These include most types of ROM and a type of flash memory called NOR-Flash. Integrated-circuit RAM chips came into the market in the early 1970s, with the first commercially available DRAM chip, the Intel 1103, introduced in October 1970. Early computers used relays, mechanical counters or delay lines for main memory functions. Ultrasonic delay lines could only reproduce data in the order. Drum memory could be expanded at low cost but efficient retrieval of memory items required knowledge of the physical layout of the drum to optimize speed. Latches built out of vacuum tube triodes, out of discrete transistors, were used for smaller and faster memories such as registers; such registers were large and too costly to use for large amounts of data. The first practical form of random-access memory was the Williams tube starting in 1947.
It stored data. Since the electron beam of the CRT could read and write the spots on the tube in any order, memory was random access; the capacity of the Williams tube was a few hundred to around a thousand bits, but it was much smaller and more power-efficient than using individual vacuum tube latches. Developed at the University of Manchester in England, the Williams tube provided the medium on which the first electronically stored program was implemented in the Manchester Baby computer, which first ran a program on 21 June 1948. In fact, rather than the Williams tube memory being designed for the Baby, the Baby was a testbed to demonstrate the reliability of the memory. Magnetic-core memory was developed up until the mid-1970s, it became a widespread form of random-access memory. By changing the sense of each ring's magnetization, data could be stored with one bit stored per ring. Since every ring had a combination of address wires to select and read or write it, access to any memory location in any sequence was possible.
Magnetic core memory was the standard form of memory system until displaced by solid-state memory in integrated circuits, starting in the early 1970s. Dynamic random-access memory allowed replacement of a 4 or 6-transistor latch circuit by a single transistor for each memory bit increasing memory density at the cost of volatility. Data was stored in the tiny capacitance of each transistor, had to be periodically refreshed every few milliseconds before the charge could leak away; the Toshiba Toscal BC-1411 electronic calculator, introduced in 1965, used a form of DRAM built from discrete components. DRAM was developed by Robert H. Dennard in 1968. Prior to the development of integrated read-only memory circuits, permanent random-access memory was constructed using diode matrices driven by address decoders, or specially wound core rope memory planes; the two used forms of modern RAM are static RAM and dynamic RAM. In SRAM, a bit of data is stored using the state of a six transistor memory cell.
This form of RAM is more expensive to produce, but is faster and requires less dynamic power than DRAM. In modern computers, SRAM is used as cache memory for the CPU. DRAM stores a bit of data using a transistor and capacitor pair, which together comprise a DRAM cell; the capacitor holds a high or low charge, the transistor acts as a switch that lets the control circuitry on the chip read the capacitor's state of charge or change it. As this form of memory is less expensive to produce than static RAM, it is the predominant form of computer memory used in modern computers. Both static and dynamic RAM are considered volatile, as their state is lost or reset when power is removed from the system. By contrast, read-only memory stores data by permanently enabling or disabling selected transistors, such that the memory cannot be altered. Writeable variants of ROM share properties of both ROM and RAM, enabling data to persist without power and to be updated without requiring special equipment; these persistent forms of semiconductor ROM include USB flash drives, memory cards for cameras and portable devices, solid-state drives.
ECC memory includes special circuitry to detect and/or correct random faults (mem
IBM eServer was a family of computer servers from IBM Corporation. Announced in the year 2000, it combined the various IBM server brands under one brand; the various sub-brands were at the same time rebranded from: IBM AS/400 to IBM eServer iSeries, i for Integrated. IBM RS/6000 to IBM eServer pSeries, p for POWER IBM Netfinity to IBM eServer xSeries, x for eXtended architecture IBM S/390 to IBM eServer zSeries, z for Zero downtimeIn 2005 announced a new brand, IBM System as an umbrella for all IBM server and storage brands; the name change was finished in 2006 when the IBM xSeries became the IBM System x Lenovo System x. IBM eServer iSeries became IBM System i IBM eServer pSeries became IBM System p IBM eServer xSeries became Lenovo System x IBM eServer zSeries became IBM Z IBM TotalStorage became IBM Storage IBM eServer BladeCenter became IBM BladeCenter IBM eServer 1350 became IBM System Cluster 1350 IBM servers