An embedded system is a controller programmed and controlled by a real-time operating system with a dedicated function within a larger mechanical or electrical system with real-time computing constraints. It is embedded as part of a complete device including hardware and mechanical parts. Embedded systems control many devices in common use today. Ninety-eight percent of all microprocessors manufactured are used in embedded systems. Examples of properties of typical embedded computers when compared with general-purpose counterparts are low power consumption, small size, rugged operating ranges, low per-unit cost; this comes at the price of limited processing resources, which make them more difficult to program and to interact with. However, by building intelligence mechanisms on top of the hardware, taking advantage of possible existing sensors and the existence of a network of embedded units, one can both optimally manage available resources at the unit and network levels as well as provide augmented functions, well beyond those available.
For example, intelligent techniques can be designed to manage power consumption of embedded systems. Modern embedded systems are based on microcontrollers, but ordinary microprocessors are common in more complex systems. In either case, the processor used may be types ranging from general purpose to those specialized in certain class of computations, or custom designed for the application at hand. A common standard class of dedicated processors is the digital signal processor. Since the embedded system is dedicated to specific tasks, design engineers can optimize it to reduce the size and cost of the product and increase the reliability and performance; some embedded systems are mass-produced. Embedded systems range from portable devices such as digital watches and MP3 players, to large stationary installations like traffic lights, factory controllers, complex systems like hybrid vehicles, MRI, avionics. Complexity varies from low, with a single microcontroller chip, to high with multiple units and networks mounted inside a large chassis or enclosure.
One of the first recognizably modern embedded systems was the Apollo Guidance Computer, developed ca. 1965 by Charles Stark Draper at the MIT Instrumentation Laboratory. At the project's inception, the Apollo guidance computer was considered the riskiest item in the Apollo project as it employed the newly developed monolithic integrated circuits to reduce the size and weight. An early mass-produced embedded system was the Autonetics D-17 guidance computer for the Minuteman missile, released in 1961; when the Minuteman II went into production in 1966, the D-17 was replaced with a new computer, the first high-volume use of integrated circuits. Since these early applications in the 1960s, embedded systems have come down in price and there has been a dramatic rise in processing power and functionality. An early microprocessor for example, the Intel 4004, was designed for calculators and other small systems but still required external memory and support chips. In 1978 National Engineering Manufacturers Association released a "standard" for programmable microcontrollers, including any computer-based controllers, such as single board computers and event-based controllers.
As the cost of microprocessors and microcontrollers fell it became feasible to replace expensive knob-based analog components such as potentiometers and variable capacitors with up/down buttons or knobs read out by a microprocessor in consumer products. By the early 1980s, memory and output system components had been integrated into the same chip as the processor forming a microcontroller. Microcontrollers find applications. A comparatively low-cost microcontroller may be programmed to fulfill the same role as a large number of separate components. Although in this context an embedded system is more complex than a traditional solution, most of the complexity is contained within the microcontroller itself. Few additional components may be needed and most of the design effort is in the software. Software prototype and test can be quicker compared with the design and construction of a new circuit not using an embedded processor. Embedded systems are found in consumer, automotive, medical and military applications.
Telecommunications systems employ numerous embedded systems from telephone switches for the network to cell phones at the end user. Computer networking uses dedicated routers and network bridges to route data. Consumer electronics include MP3 players, mobile phones, video game consoles, digital cameras, GPS receivers, printers. Household appliances, such as microwave ovens, washing machines and dishwashers, include embedded systems to provide flexibility and features. Advanced HVAC systems use networked thermostats to more and efficiently control temperature that can change by time of day and season. Home automation uses wired- and wireless-networking that can be used to control lights, security, audio/visual, etc. all of which use embedded devices for sensing and controlling. Transportation systems from flight to automobiles use embedded systems. New airplanes contain advanced avionics such as inertial guidance systems and GPS receivers that have considerable safety requirements. Various electric motors — brushless DC motors, induction motors and DC motors — use electric/electronic motor controllers.
Automobiles, electric vehicles, hy
A CPU cache is a hardware cache used by the central processing unit of a computer to reduce the average cost to access data from the main memory. A cache is a smaller, faster memory, closer to a processor core, which stores copies of the data from used main memory locations. Most CPUs have different independent caches, including instruction and data caches, where the data cache is organized as a hierarchy of more cache levels. All modern CPUs have multiple levels of CPU caches; the first CPUs that used a cache had only one level of cache. All current CPUs with caches have a split L1 cache, they have L2 caches and, for larger processors, L3 caches as well. The L2 cache is not split and acts as a common repository for the split L1 cache; every core of a multi-core processor has a dedicated L2 cache and is not shared between the cores. The L3 cache, higher-level caches, are shared between the cores and are not split. An L4 cache is uncommon, is on dynamic random-access memory, rather than on static random-access memory, on a separate die or chip.
That was the case with L1, while bigger chips have allowed integration of it and all cache levels, with the possible exception of the last level. Each extra level of cache tends to be optimized differently. Other types of caches exist, such as the translation lookaside buffer, part of the memory management unit that most CPUs have. Caches are sized in powers of two: 4, 8, 16 etc. KiB or MiB sizes; when trying to read from or write to a location in main memory, the processor checks whether the data from that location is in the cache. If so, the processor will read from or write to the cache instead of main memory, much slower. Most modern desktop and server CPUs have at least three independent caches: an instruction cache to speed up executable instruction fetch, a data cache to speed up data fetch and store, a translation lookaside buffer used to speed up virtual-to-physical address translation for both executable instructions and data. A single TLB can be provided for access to both instructions and data, or a separate Instruction TLB and data TLB can be provided.
The data cache is organized as a hierarchy of more cache levels. However, the TLB cache is part of the memory management unit and not directly related to the CPU caches. Data is transferred between memory and cache in blocks of fixed size, called cache lines or cache blocks; when a cache line is copied from memory into the cache, a cache entry is created. The cache entry will include the copied data as well as the requested memory location; when the processor needs to read or write a location in memory, it first checks for a corresponding entry in the cache. The cache checks for the contents of the requested memory location in any cache lines that might contain that address. If the processor finds that the memory location is in the cache, a cache hit has occurred. However, if the processor does not find the memory location in the cache, a cache miss. In the case of a cache hit, the processor reads or writes the data in the cache line. For a cache miss, the cache allocates a new entry and copies data from main memory the request is fulfilled from the contents of the cache.
To make room for the new entry on a cache miss, the cache may have to evict one of the existing entries. The heuristic it uses to choose the entry to evict is called the replacement policy; the fundamental problem with any replacement policy is that it must predict which existing cache entry is least to be used in the future. Predicting the future is difficult, so there is no perfect method to choose among the variety of replacement policies available. One popular replacement policy, least-recently used, replaces the least accessed entry. Marking some memory ranges as non-cacheable can improve performance, by avoiding caching of memory regions that are re-accessed; this avoids the overhead of loading something into the cache without having any reuse. Cache entries may be disabled or locked depending on the context. If data is written to the cache, at some point it must be written to main memory. In a write-through cache, every write to the cache causes a write to main memory. Alternatively, in a write-back or copy-back cache, writes are not mirrored to the main memory, the cache instead tracks which locations have been written over, marking them as dirty.
The data in these locations is written back to the main memory only when that data is evicted from the cache. For this reason, a read miss in a write-back cache may sometimes require two memory accesses to service: one to first write the dirty location to main memory, another to read the new location from memory. A write to a main memory location, not yet mapped in a write-back cache may evict an dirty location, thereby freeing that cache space for the new memory location. There are intermediate policies as well; the cache may be write-through, but the writes may be held in a store data queue temporarily so multiple stores can be processed together. Cached data from the main memory may be changed b
Motorola, Inc. was an American multinational telecommunications company founded on September 25, 1928, based in Schaumburg, Illinois. After having lost $4.3 billion from 2007 to 2009, the company was divided into two independent public companies, Motorola Mobility and Motorola Solutions on January 4, 2011. Motorola Solutions is considered to be the direct successor to Motorola, as the reorganization was structured with Motorola Mobility being spun off. Motorola Mobility was sold to Google in 2012, acquired by Lenovo in 2014. Motorola designed and sold wireless network equipment such as cellular transmission base stations and signal amplifiers. Motorola's home and broadcast network products included set-top boxes, digital video recorders, network equipment used to enable video broadcasting, computer telephony, high-definition television, its business and government customers consisted of wireless voice and broadband systems, public safety communications systems like Astro and Dimetra. These businesses are now part of Motorola Solutions.
Google sold Motorola Home to the Arris Group in December 2012 for US$2.35 billion. Motorola's wireless telephone handset division was a pioneer in cellular telephones. Known as the Personal Communication Sector prior to 2004, it pioneered the "mobile phone" with DynaTAC, "flip phone" with the MicroTAC, as well as the "clam phone" with the StarTAC in the mid-1990s, it had staged a resurgence by the mid-2000s with the Razr, but lost market share in the second half of that decade. It focused on smartphones using Google's open-source Android mobile operating system; the first phone to use the newest version of Google's open source OS, Android 2.0, was released on November 2, 2009 as the Motorola Droid. The handset division was spun off into the independent Motorola Mobility. On May 22, 2012, Google CEO Larry Page announced that Google had closed on its deal to acquire Motorola Mobility. On January 29, 2014, Page announced that, pending closure of the deal, Motorola Mobility would be acquired by Chinese technology company Lenovo for US$2.91 billion.
On October 30, 2014, Lenovo finalized its purchase of Motorola Mobility from Google. Motorola started in Chicago, Illinois, as Galvin Manufacturing Corporation in 1928 when brothers Paul V. and Joseph E. Galvin purchased the bankrupt Stewart Battery Company's battery-eliminator plans and manufacturing equipment at auction for $750. Galvin Manufacturing Corporation set up shop in a small section of a rented building; the company had $565 in five employees. The first week's payroll was $63; the company's first products were the battery eliminators, devices that enabled battery-powered radios to operate on household electricity. Due to advances in radio technology, battery-eliminators soon became obsolete. Paul Galvin learned that some radio technicians were installing sets in cars, challenged his engineers to design an inexpensive car radio that could be installed in most vehicles, his team was successful, Galvin was able to demonstrate a working model of the radio at the June 1930 Radio Manufacturers Association convention in Atlantic City, New Jersey.
He brought home enough orders to keep the company in business. Paul Galvin wanted a brand name for Galvin Manufacturing Corporation's new car radio, created the name “Motorola” by linking "motor" with "ola", a popular ending for many companies at the time, e.g. Moviola, Crayola; the company sold its first Motorola branded radio on June 23, 1930, to Herbert C. Wall of Fort Wayne, for $30. Wall went on to become one of the first Motorola distributors in the country; the Motorola brand name became so well known that Galvin Manufacturing Corporation changed its name to Motorola, Inc. Galvin Manufacturing Corporation began selling Motorola car-radio receivers to police departments and municipalities in November 1930; the company's first public safety customers included the Village of River Forest, Village of Bellwood Police Department, City of Evanston Police, Illinois State Highway Police, Cook County Police with a one-way radio communication. In the same year, the company built its research and development program with Dan Noble, a pioneer in FM radio and semiconductor technologies, who joined the company as director of research.
The company produced the hand-held AM SCR-536 radio during World War II, vital to Allied communication. Motorola ranked 94th among United States corporations in the value of World War II military production contracts. Motorola went public in 1943, became Motorola, Inc. in 1947. At that time Motorola's main business was selling televisions and radios. In October 1946 Motorola communications equipment carried the first calls on Illinois Bell telephone company's new car radiotelephone service in Chicago; the company began making televisions in 1947, with the model VT-71 with 7-inch cathode ray tube. In 1952, Motorola opened its first international subsidiary in Toronto, Canada to produce radios and televisions. In 1953, the company established the Motorola Foundation to support leading universities in the United States. In 1955, years after Motorola started its research and development laboratory in Phoenix, Arizona, to research new solid-state technology, Motorola introduced the world's first commercial high-power germanium-based transistor.
A microprocessor is a computer processor that incorporates the functions of a central processing unit on a single integrated circuit, or at most a few integrated circuits. The microprocessor is a multipurpose, clock driven, register based, digital integrated circuit that accepts binary data as input, processes it according to instructions stored in its memory, provides results as output. Microprocessors contain sequential digital logic. Microprocessors operate on symbols represented in the binary number system; the integration of a whole CPU onto a single or a few integrated circuits reduced the cost of processing power. Integrated circuit processors are produced in large numbers by automated processes, resulting in a low unit price. Single-chip processors increase reliability because there are many fewer electrical connections that could fail; as microprocessor designs improve, the cost of manufacturing a chip stays the same according to Rock's law. Before microprocessors, small computers had been built using racks of circuit boards with many medium- and small-scale integrated circuits.
Microprocessors combined this into a few large-scale ICs. Continued increases in microprocessor capacity have since rendered other forms of computers completely obsolete, with one or more microprocessors used in everything from the smallest embedded systems and handheld devices to the largest mainframes and supercomputers; the complexity of an integrated circuit is bounded by physical limitations on the number of transistors that can be put onto one chip, the number of package terminations that can connect the processor to other parts of the system, the number of interconnections it is possible to make on the chip, the heat that the chip can dissipate. Advancing technology makes more powerful chips feasible to manufacture. A minimal hypothetical microprocessor might include only an arithmetic logic unit, a control logic section; the ALU performs addition and operations such as AND or OR. Each operation of the ALU sets one or more flags in a status register, which indicate the results of the last operation.
The control logic retrieves instruction codes from memory and initiates the sequence of operations required for the ALU to carry out the instruction. A single operation code might affect many individual data paths and other elements of the processor; as integrated circuit technology advanced, it was feasible to manufacture more and more complex processors on a single chip. The size of data objects became larger. Additional features were added to the processor architecture. Floating-point arithmetic, for example, was not available on 8-bit microprocessors, but had to be carried out in software. Integration of the floating point unit first as a separate integrated circuit and as part of the same microprocessor chip sped up floating point calculations. Physical limitations of integrated circuits made such practices as a bit slice approach necessary. Instead of processing all of a long word on one integrated circuit, multiple circuits in parallel processed subsets of each data word. While this required extra logic to handle, for example and overflow within each slice, the result was a system that could handle, for example, 32-bit words using integrated circuits with a capacity for only four bits each.
The ability to put large numbers of transistors on one chip makes it feasible to integrate memory on the same die as the processor. This CPU cache has the advantage of faster access than off-chip memory and increases the processing speed of the system for many applications. Processor clock frequency has increased more than external memory speed, so cache memory is necessary if the processor is not delayed by slower external memory. A microprocessor is a general-purpose entity. Several specialized processing devices have followed: A digital signal processor is specialized for signal processing. Graphics processing units are processors designed for realtime rendering of images. Other specialized units exist for video machine vision. Microcontrollers integrate a microprocessor with peripheral devices in embedded systems. Systems on chip integrate one or more microprocessor or microcontroller cores. Microprocessors can be selected for differing applications based on their word size, a measure of their complexity.
Longer word sizes allow each clock cycle of a processor to carry out more computation, but correspond to physically larger integrated circuit dies with higher standby and operating power consumption. 4, 8 or 12 bit processors are integrated into microcontrollers operating embedded systems. Where a system is expected to handle larger volumes of data or require a more flexible user interface, 16, 32 or 64 bit processors are used. An 8- or 16-bit processor may be selected over a 32-bit processor for system on a chip or microcontroller applications that require low-power electronics, or are part of a mixed-signal integrated circuit with noise-sensitive on-chip analog electronics such as high-resolution analog to digital converters, or both. Running 32-bit arithmetic on an 8-bit chip could end up using more power, as the chip must execute software with multiple instructions. Thousands of items that were traditionally not computer-related inc
PowerPC is a reduced instruction set computing instruction set architecture created by the 1991 Apple–IBM–Motorola alliance, known as AIM. PowerPC, as an evolving instruction set, has since 2006 been named Power ISA, while the old name lives on as a trademark for some implementations of Power Architecture-based processors. PowerPC was the cornerstone of AIM's PReP and Common Hardware Reference Platform initiatives in the 1990s. Intended for personal computers, the architecture is well known for being used by Apple's Power Macintosh, PowerBook, iMac, iBook, Xserve lines from 1994 until 2006, when Apple migrated to Intel's x86, it has since become a niche in personal computers, but remains popular for embedded and high-performance processors. Its use in 7th generation of video game consoles and embedded applications provided an array of uses. In addition, PowerPC CPUs are still used in third party AmigaOS 4 personal computers. PowerPC is based on IBM's earlier POWER instruction set architecture, retains a high level of compatibility with it.
The history of RISC began with IBM's 801 research project, on which John Cocke was the lead developer, where he developed the concepts of RISC in 1975–78. 801-based microprocessors were used in a number of IBM embedded products becoming the 16-register IBM ROMP processor used in the IBM RT PC. The RT PC was a rapid design implementing the RISC architecture. Between the years of 1982–1984, IBM started a project to build the fastest microprocessor on the market; the result is the POWER instruction set architecture, introduced with the RISC System/6000 in early 1990. The original POWER microprocessor, one of the first superscalar RISC implementations, is a high performance, multi-chip design. IBM soon realized that a single-chip microprocessor was needed in order to scale its RS/6000 line from lower-end to high-end machines. Work began on a one-chip POWER microprocessor, designated the RSC. In early 1991, IBM realized its design could become a high-volume microprocessor used across the industry. Apple had realized the limitations and risks of its dependency upon a single CPU vendor at a time when Motorola was falling behind on delivering the 68040 CPU.
Furthermore, Apple had conducted its own research and made an experimental quad-core CPU design called Aquarius, which convinced the company's technology leadership that the future of computing was in the RISC methodology. IBM approached Apple with the goal of collaborating on the development of a family of single-chip microprocessors based on the POWER architecture. Soon after, being one of Motorola's largest customers of desktop-class microprocessors, asked Motorola to join the discussions due to their long relationship, Motorola having had more extensive experience with manufacturing high-volume microprocessors than IBM, to form a second source for the microprocessors; this three-way collaboration between Apple, IBM, Motorola became known as the AIM alliance. In 1991, the PowerPC was just one facet of a larger alliance among these three companies. At the time, most of the personal computer industry was shipping systems based on the Intel 80386 and 80486 chips, which have a complex instruction set computer architecture, development of the Pentium processor was well underway.
The PowerPC chip was one of several joint ventures involving the three alliance members, in their efforts to counter the growing Microsoft-Intel dominance of personal computing. For Motorola, POWER looked like an unbelievable deal, it allowed the company to sell a tested and powerful RISC CPU for little design cash on its own part. It maintained ties with an important customer and seemed to offer the possibility of adding IBM too, which might buy smaller versions from Motorola instead of making its own. At this point Motorola had its own RISC design in the form of the 88000, doing poorly in the market. Motorola was doing well with its 68000 family and the majority of the funding was focused on this; the 88000 effort was somewhat starved for resources. The 88000 was in production, however; the 88000 had achieved a number of embedded design wins in telecom applications. If the new POWER one-chip version could be made bus-compatible at a hardware level with the 88000, that would allow both Apple and Motorola to bring machines to market far faster since they would not have to redesign their board architecture.
The result of these various requirements is the PowerPC specification. The differences between the earlier POWER instruction set and that of PowerPC is outlined in Appendix E of the manual for PowerPC ISA v.2.02. Since 1991, IBM had a long-standing desire for a unifying operating system that would host all existing operating systems as personalities upon one microkernel. From 1991 to 1995, the company designed and aggressively evangelized what would become Workplace OS targeting PowerPC; when the first PowerPC products reached the market, they were met with enthusiasm. In addition to Apple, both IBM and the Motorola Computer Group offered systems built around the processors. Microsoft released Windows NT 3.51 for the architecture, used in Motorola's
Arithmetic logic unit
An arithmetic logic unit is a combinational digital electronic circuit that performs arithmetic and bitwise operations on integer binary numbers. This is in contrast to a floating-point unit. An ALU is a fundamental building block of many types of computing circuits, including the central processing unit of computers, FPUs, graphics processing units. A single CPU, FPU or GPU may contain multiple ALUs; the inputs to an ALU are the data to be operated on, called operands, a code indicating the operation to be performed. In many designs, the ALU has status inputs or outputs, or both, which convey information about a previous operation or the current operation between the ALU and external status registers. An ALU has a variety of input and output nets, which are the electrical conductors used to convey digital signals between the ALU and external circuitry; when an ALU is operating, external circuits apply signals to the ALU inputs and, in response, the ALU produces and conveys signals to external circuitry via its outputs.
A basic ALU has three parallel data buses consisting of a result output. Each data bus is a group of signals; the A, B and Y bus widths are identical and match the native word size of the external circuitry. The opcode input is a parallel bus that conveys to the ALU an operation selection code, an enumerated value that specifies the desired arithmetic or logic operation to be performed by the ALU; the opcode size determines the maximum number of different operations. An ALU opcode is not the same as a machine language opcode, though in some cases it may be directly encoded as a bit field within a machine language opcode; the status outputs are various individual signals that convey supplemental information about the result of the current ALU operation. General-purpose ALUs have status signals such as: Carry-out, which conveys the carry resulting from an addition operation, the borrow resulting from a subtraction operation, or the overflow bit resulting from a binary shift operation. Zero, which indicates all bits of Y are logic zero.
Negative, which indicates the result of an arithmetic operation is negative. Overflow, which indicates the result of an arithmetic operation has exceeded the numeric range of Y. Parity, which indicates whether an or odd number of bits in Y are logic one. At the end of each ALU operation, the status output signals are stored in external registers to make them available for future ALU operations or for controlling conditional branching; the collection of bit registers that store the status outputs are treated as a single, multi-bit register, referred to as the "status register" or "condition code register". The status inputs allow additional information to be made available to the ALU when performing an operation; this is a single "carry-in" bit, the stored carry-out from a previous ALU operation. An ALU is a combinational logic circuit, meaning that its outputs will change asynchronously in response to input changes. In normal operation, stable signals are applied to all of the ALU inputs and, when enough time has passed for the signals to propagate through the ALU circuitry, the result of the ALU operation appears at the ALU outputs.
The external circuitry connected to the ALU is responsible for ensuring the stability of ALU input signals throughout the operation, for allowing sufficient time for the signals to propagate through the ALU before sampling the ALU result. In general, external circuitry controls an ALU by applying signals to its inputs; the external circuitry employs sequential logic to control the ALU operation, paced by a clock signal of a sufficiently low frequency to ensure enough time for the ALU outputs to settle under worst-case conditions. For example, a CPU begins an ALU addition operation by routing operands from their sources to the ALU's operand inputs, while the control unit applies a value to the ALU's opcode input, configuring it to perform addition. At the same time, the CPU routes the ALU result output to a destination register that will receive the sum; the ALU's input signals, which are held stable until the next clock, are allowed to propagate through the ALU and to the destination register while the CPU waits for the next clock.
When the next clock arrives, the destination register stores the ALU result and, since the ALU operation has completed, the ALU inputs may be set up for the next ALU operation. A number of basic arithmetic and bitwise logic functions are supported by ALUs. Basic, general purpose ALUs include these operations in their repertoires: Add: A and B are summed and the sum appears at Y and carry-out. Add with carry: A, B and carry-in are summed and the sum appears at Y and carry-out. Subtract: B is subtracted from A and the difference appears at Y and carry-out. For this function, carry-out is a "borrow" indicator; this operation may be used to compare the magnitudes of A and B. Subtract with borrow: B is subtracted from A with borrow and the difference appears at Y and carry-
This article is based on material taken from the Free On-line Dictionary of Computing prior to 1 November 2008 and incorporated under the "relicensing" terms of the GFDL, version 1.3 or later. The Motorola 68040 is a 32-bit microprocessor from Motorola, released in 1990, it is the successor to the 68030 and is followed by the 68060. There was no 68050. In keeping with general Motorola naming, the 68040 is referred to as the'040. In Apple Macintosh computers, the 68040 was introduced in the Macintosh Quadra, named for the chip; the fastest 68040 processor was clocked at 40 MHz and it was used only in the Quadra 840AV. The more expensive models in the Macintosh Centris line used the 68040, while the cheaper Quadra and Macintosh Performa used the 68LC040; the 68040 was used in other personal computers, such as the Amiga 4000 and Amiga 4000T, as well as a number of workstations, Alpha Microsystems servers, the HP 9000/400 series, versions of the NeXT computer. The 68040 was the first 680x0 family member with an on-chip Floating-Point Unit.
It thus included all of the functionality that required external chips, namely the FPU and Memory Management Unit, added in the 68030. It had split instruction and data caches of 4 kilobytes each, it was pipelined, with six stages. The 68040 ran into the transistor budget limit early in design. While the MMU did not take many transistors—indeed, having it on the same die as the CPU saved on transistors—the FPU did. Motorola's 68882 external FPU was known as a high performance unit and Motorola did not wish to risk integrators using the "LC" version with a 68882 instead of the more profitable full "RC" unit; the FPU in the 68040 was thus made incapable of IEEE transcendental functions, supported by both the 68881 and 68882 and were used by the popular fractal generating software of the time and little else. The Motorola floating point support package emulated these instructions in software under interrupt; as this was an exception handler, heavy use of the transcendental functions caused severe performance penalties.
Heat was always a problem throughout the 68040's life. While it delivered over four times the per-clock performance of the 68020 and 68030, the chip's complexity and power requirements came from a large die and large caches; this affected the scaling of the processor and it was never able to run with a clock rate exceeding 40 MHz. A 50 MHz variant canceled. Overclocking enthusiasts reported success reaching 50 MHz using a 100 MHz oscillator instead of an 80 MHz part and the novel technique of adding oversized heat sinks with fans; the 68040 offered the same features as the Intel 80486, but on a clock-for-clock basis could outperform the Intel chip in integer and floating point instructions. However, the 80486 had the ability to be clocked faster without suffering from overheating problems. In late 1991, as the higher-end Macintosh desktop lineup transitioned to the'040, Apple was unable to offer the newer processor in their top-of-the-line PowerBooks until early 1994. With PowerBooks being restricted to 68030s for several years, Macworld reviewers conceded that the best choice for power users was the PC-compatible Texas Instruments 80486 notebook, rather than the top-of-the-line PowerBook 180.
Versions of the 68040 were created for specific market segments, including the 68LC040, which removed the FPU, the 68EC040, which removed both the FPU and MMU. Motorola had intended the EC variant for embedded use, but embedded processors during the 68040's time did not need the power of the 68040, so EC variants of the 68020 and 68030 continued to be common in designs. Motorola produced several speed grades; the 16 MHz and 20 MHz parts were never qualified and used as prototyping samples. 25 MHz and 33 MHz grades featured across the whole line, but until around 2000 the 40 MHz grade was only for the "full" 68040. A planned 50 MHz grade was canceled. For more information on the instructions and architecture, see Motorola 68000; the 68EC040 is a version of the Motorola 68040 microprocessor, intended for embedded controllers. It differs from the 68040 in that it has neither an FPU nor an MMU; this makes it less expensive and it draws less power. The 68EC040 was used in Cisco switch Supervisor Engine I, the heart of models 2900, 2948G, 2980G, 4000, 4500, 5000, 5500, 6000, 6500 and 7600.
The 68LC040 is a low cost version of the Motorola 68040 microprocessor with no FPU. This makes it less expensive and it draws less power. Although the CPU now fits into a feature chart more like the Motorola 68020, it continues to include the 68040's caches and pipeline and is thus faster than the 68020; some mask revisions of the 68LC040 contained a bug that prevents the chip from operating when a software FPU emulator is used. According to Motorola's errata, any chip with a mask set 2E71M or does not contain the bug; this new mask was converted the 68LC040 chip to MC status. The buggy revisions are found in 68LC040-based Apple Macintosh computers. Chips with mask set; the fault relates to pending writes being lost. The 68040 cannot update its microcode in the manner of modern x86 chips; this means that the only way to use software that requires floating-point functionality is to replace the buggy 68LC040 with a revision, or a full 68040. ATC = Add