A workstation is a special computer designed for technical or scientific applications. Intended to be used by one person at a time, they are connected to a local area network and run multi-user operating systems; the term workstation has been used loosely to refer to everything from a mainframe computer terminal to a PC connected to a network, but the most common form refers to the group of hardware offered by several current and defunct companies such as Sun Microsystems, Silicon Graphics, Apollo Computer, DEC, HP, NeXT and IBM which opened the door for the 3D graphics animation revolution of the late 1990s. Workstations offered higher performance than mainstream personal computers with respect to CPU and graphics, memory capacity, multitasking capability. Workstations were optimized for the visualization and manipulation of different types of complex data such as 3D mechanical design, engineering simulation and rendering of images, mathematical plots; the form factor is that of a desktop computer, consist of a high resolution display, a keyboard and a mouse at a minimum, but offer multiple displays, graphics tablets, 3D mice, etc.
Workstations were the first segment of the computer market to present advanced accessories and collaboration tools. The increasing capabilities of mainstream PCs in the late 1990s have blurred the lines somewhat with technical/scientific workstations; the workstation market employed proprietary hardware which made them distinct from PCs. However, by the early 2000s this difference disappeared, as workstations now use commoditized hardware dominated by large PC vendors, such as Dell, Hewlett-Packard and Fujitsu, selling Microsoft Windows or Linux systems running on x86-64 processors; the first computer that might qualify as a "workstation" was the IBM 1620, a small scientific computer designed to be used interactively by a single person sitting at the console. It was introduced in 1960. One peculiar feature of the machine was. To perform addition, it required a memory-resident table of decimal addition rules; this saved on the cost of logic circuitry. The machine was code-named CADET and rented for $1000 a month.
In 1965, IBM introduced the IBM 1130 scientific computer, meant as the successor to the 1620. Both of these systems came with the ability to run programs written in other languages. Both the 1620 and the 1130 were built into desk-sized cabinets. Both were available with add-on disk drives and both paper-tape and punched-card I/O. A console typewriter for direct interaction was standard on each. Early examples of workstations were dedicated minicomputers. A notable example was the PDP-8 from Digital Equipment Corporation, regarded to be the first commercial minicomputer; the Lisp machines developed at MIT in the early 1970s pioneered some of the principles of the workstation computer, as they were high-performance, single-user systems intended for interactive use. Lisp Machines were commercialized beginning 1980 by companies like Symbolics, Lisp Machines, Texas Instruments and Xerox; the first computer designed for single-users, with high-resolution graphics facilities was the Xerox Alto developed at Xerox PARC in 1973.
Other early workstations include the Terak 8510/a, Three Rivers PERQ and the Xerox Star. In the early 1980s, with the advent of 32-bit microprocessors such as the Motorola 68000, a number of new participants in this field appeared, including Apollo Computer and Sun Microsystems, who created Unix-based workstations based on this processor. Meanwhile, DARPA's VLSI Project created several spinoff graphics products as well, notably the SGI 3130, Silicon Graphics' range of machines that followed, it was not uncommon to differentiate the target market for the products, with Sun and Apollo considered to be network workstations, while the SGI machines were graphics workstations. As RISC microprocessors became available in the mid-1980s, these were adopted by many workstation vendors. Workstations tended to be expensive several times the cost of a standard PC and sometimes costing as much as a new car. However, minicomputers sometimes cost as much as a house; the high expense came from using costlier components that ran faster than those found at the local computer store, as well as the inclusion of features not found in PCs of the time, such as high-speed networking and sophisticated graphics.
Workstation manufacturers tend to take a "balanced" approach to system design, making certain to avoid bottlenecks so that data can flow unimpeded between the many different subsystems within a computer. Additionally, given their more specialized nature, tend to have higher profit margins than commodity-driven PCs; the systems that come out of workstation companies feature SCSI or Fibre Channel disk storage systems, high-end 3D accelerators, single or multiple 64-bit processors, large amounts of RAM, well-designed cooling. Additionally, the companies that make the products tend to have good repair/replacement plans. However, the line between workstation and PC is becoming blurred as the demand for fast computers and graphics have become
The Motorola 68881 and Motorola 68882 are floating-point coprocessor devices that were used in some computer systems in conjunction with the 68020 or 68030 microprocessors. The Motorola 68881 was introduced in 1984; the addition of one of these devices added substantial cost to a computer, but added a floating-point unit that could perform floating point mathematical calculations. In the mid 1980s, this feature was useful for scientific and mathematical software; the 68020 and 68030 CPUs were designed with the separate 68881 chip in mind. Their instruction sets reserved the "F-line" instructions – that is, all opcodes beginning with the hexadecimal digit "F" could either be forwarded to an external coprocessor or be used as "traps" which would throw an exception, handing control to the computer's operating system. If an FPU is not present in the system, the OS would either call an FPU emulator to execute the instruction's equivalent using 68020 integer-based software code, return an error to the program, terminate the program, or crash and require a reboot.
The 68881 had eight 80-bit data. It allowed seven different modes of numeric representation, including single-precision, double-precision, extended-precision, as defined by the IEEE floating-point standard, IEEE 754, it was designed for floating-point math and was not a general-purpose CPU. For example, when an instruction required any address calculations, the main CPU would handle them before the 68881 took control; the CPU/FPU pair were designed such. When the CPU encountered a 68881 instruction, it would hand the FPU all operands needed for that instruction, the FPU would release the CPU to go on and execute the next instruction; the 68882 was an improved version of the 68881, with better pipelining, available at higher clock speeds. Its instruction set was the same as that of the 68881. Motorola claimed in some marketing literature that it executed some instructions 40% faster than a 68881 at the same clock speed, though this did not reflect typical performance, as seen by its more modest improvement in the table below.
The 68882 can be used as a direct replacement in most systems. The most important software incompatibility was that the 68882 used a larger FSAVE state frame, which affected UNIX and other preemptive multitasking OSes that had to be modified to allocate more space for it; the 68881 or 68882 were used in the Sun Microsystems Sun-3 workstations, IBM RT PC workstations, Apple Computer Macintosh II family, NeXT Computer, Amiga 3000, Atari Mega STE, TT, Falcon030. Some third-party Amiga and Atari products used the 68881 or 68882 as a memory-mapped peripheral to the 68000. 155 000 transistors on-chip 12 MHz version 16 MHz version ran at 160 kFLOPS 20 MHz version ran at 192 kFLOPS 25 MHz version ran at 240 kFLOPS 176 000 transistors on-chip 25 MHz version ran at 264 kFLOPS 33 MHz version ran at 352 kFLOPS 40 MHz version ran at 422 kFLOPS 50 MHz version ran at 528 kFLOPSThese statistics came from the comp.sys.m68k FAQ. No statistics are listed for 20 MHz 68882, though these chips were indeed produced.
Starting with the Motorola 68040, floating point support was included in the CPU itself. Notesfreescale.com - Motorola MC68000 Family Programmer's Reference Manual faqs.org - comp.sys.m68k FAQ
Macintosh Centris is a family of personal computers designed and sold by Apple Computer, Inc. in 1992 and 1993. They were introduced as a replacement for the six-year-old Macintosh II family of computers. Centris machines were the first to offer Motorola 68040 CPUs at a price point around $2,500 USD, making them less expensive than Quadra computers, but offering higher performance than the Macintosh LC computers of the time. Apple released three computers bearing the Centris name: the Centris 610 and Centris 650, both of which were introduced in March 1993, the Centris 660AV which followed in July. Apple considered the Macintosh IIvx to be part of the Centris line; the IIvx was released in October of the previous year but, according to Apple, their lawyers were unable to complete the trademark check on the "Centris" name in time for the IIvx's release. The retirement of the Centris name was announced in September 1993, with the 610, 650 and 660AV all being rebranded the following month as Macintosh Quadra machines as part of Apple's effort to reposition their product families to correlate with customer markets instead of price ranges and features.
The IIvx was discontinued in favor of the newly announced Quadra 605. The Centris 610 uses a 20 MHz 68LC040 CPU, it used a new "pizza box" case, intended to be placed under the user's computer monitor. This case was used again in the Quadra 610 and Power Macintosh 6100 lines of computers and, when these computers were introduced, Apple offered consumers a product upgrade path by letting them buy a new motherboard. Apple's motherboard upgrades of this type were considered expensive and were not a popular option; the Centris 610 provided the basis for the Workgroup Server 60. The base-model Centris 650 used a 25 MHz 68LC040 CPU, it uses the Macintosh IIvx-style desktop case. The Centris 660AV uses a 25 MHz 68040 and includes a digital signal processor chip from AT&T Corporation. Like other "AV" computers from Apple, it supports output; the Centris 610 and 650 were replaced about six months after their introduction by the Quadra 610 and 650 models, which kept the same case and designs but raised the CPU speeds from 20 MHz and 25 MHz to 25 MHz and 33 MHz – while the Centris 660AV was renamed as the Quadra 660AV without any actual design change.
These Macs existed during Apple's transition from auto-inject floppy drives to manual-inject drives. This is; some Centris 660AV Macs have manual-inject floppy drives, so this change was not concurrent with the name change
A floating-point unit is a part of a computer system specially designed to carry out operations on floating point numbers. Typical operations are addition, multiplication, square root, bitshifting; some systems can perform various transcendental functions such as exponential or trigonometric calculations, though in most modern processors these are done with software library routines. In general purpose computer architectures, one or more FPUs may be integrated as execution units within the central processing unit; when a CPU is executing a program that calls for a floating-point operation, there are three ways to carry it out: A floating-point unit emulator Add-on FPU Integrated FPU Historically systems implemented floating point via a coprocessor rather than as an integrated unit. This could be an entire circuit board or a cabinet. Where floating-point calculation hardware has not been provided, floating point calculations are done in software, which takes more processor time but which avoids the cost of the extra hardware.
For a particular computer architecture, the floating point unit instructions may be emulated by a library of software functions. Emulation can be implemented on any of several levels: in the CPU as microcode, as an operating system function, or in user space code; when only integer functionality is available the CORDIC floating point emulation methods are most used. In most modern computer architectures, there is some division of floating-point operations from integer operations; this division varies by architecture. CORDIC routines has been implemented in the Intel 8087, 80287, 80387 up to the 80486 coprocessor series as well as in the Motorola 68881 and 68882 for some kinds of floating-point instructions as a way to reduce the gate counts of the FPU sub-system. Floating-point operations are pipelined. In earlier superscalar architectures without general out-of-order execution, floating-point operations were sometimes pipelined separately from integer operations. Since the early 1990s, many microprocessors for desktops and servers have more than one FPU.
The modular architecture of Bulldozer microarchitecture uses a special FPU named FlexFPU, which uses simultaneous multithreading. Each physical integer core, two per module, is single threaded, in contrast with Intel's Hyperthreading, where two virtual simultaneous threads share the resources of a single physical core; some floating-point hardware only supports the simplest operations – addition and multiplication. But the most complex floating-point hardware has a finite number of operations it can support – for example, none of them directly support arbitrary-precision arithmetic; when a CPU is executing a program that calls for a floating-point operation, not directly supported by the hardware, the CPU uses a series of simpler floating-point operations. In systems without any floating-point hardware, the CPU emulates it using a series of simpler fixed-point arithmetic operations that run on the integer arithmetic logic unit; the software that lists the necessary series of operations to emulate floating-point operations is packaged in a floating-point library.
In some cases, FPUs may be specialized, divided between simpler floating-point operations and more complicated operations, like division. In some cases, only the simple operations may be implemented in hardware or microcode, while the more complex operations are implemented as software. In some current architectures, the FPU functionality is combined with units to perform SIMD computation. In the 1980s, it was common in IBM PC/compatible microcomputers for the FPU to be separate from the CPU, sold as an optional add-on, it would only be purchased if needed to enable math-intensive programs. The IBM PC, XT, most compatibles based on the 8088 or 8086 had a socket for the optional 8087 coprocessor; the AT and 80286-based systems were socketed for the 80287, 80386/80386SX based machines for the 80387 and 80387SX although early ones were socketed for the 80287, since the 80387 did not exist yet. Other companies manufactured co-processors for the Intel x86 series; these included Weitek. Coprocessors were available for the Motorola 68000 family, the 68881 and 68882.
These were common in Motorola 68020/68030-based workstations like the Sun 3 series. They were commonly added to higher-end models of Apple Macintosh and Commodore Amiga series, but unlike IBM PC-compatible systems, sockets for adding the coprocessor were not as common in lower end systems. There are add-on FPUs coprocessor units for microcontroller units /single-board computer, which serve to provide floating-point arithmetic capability; these add-on FPUs are host-processor-independent, possess their own programming requirements and are pro
Pin grid array
A pin grid array abbreviated PGA, is a type of integrated circuit packaging. In a PGA, the package is square or rectangular, the pins are arranged in a regular array on the underside of the package; the pins are spaced 2.54 mm apart, may or may not cover the entire underside of the package. PGAs are mounted on printed circuit boards using the through hole method or inserted into a socket. PGAs allow for more pins per integrated circuit than older packages, such as dual in-line package. Plastic pin grid array packaging was used by Intel for late-model Mendocino core Celeron processors based on Socket 370; some pre-Socket 8 processors used a similar form factor, although they were not referred to as PPGA. A flip-chip pin grid array is a form of pin grid array in which the die faces downwards on the top of the substrate with the back of the die exposed; this allows the die to have a more direct contact with other cooling mechanism. The FC-PGA was introduced by Intel with the Coppermine core Pentium III and Celeron processors based on Socket 370, was used for Socket 478-based Pentium 4 and Celeron processors.
FC-PGA processors fit into zero insertion force Socket 370 and Socket 478-based motherboard sockets. It is still used today for mobile Intel processors; the staggered pin grid array is used by Intel processors based on Socket 5 and Socket 7. Socket 8 used a partial SPGA layout on half the processor, it consists of two square arrays of pins, offset in both directions by half the minimum distance between pins in one of the arrays. Put differently: within a square boundary the pins form a diagonal square lattice. There is a section in the center of the package without any pins. SPGA packages are used by devices that require a higher pin density than what a PGA can provide, such as microprocessors. A ceramic pin grid array is a type of packaging used by integrated circuits; this type of packaging uses a ceramic substrate with pins arranged in a pin grid array. Some CPUs that use CPGA packaging are the Duron. A CPGA was used by AMD for Athlon and Duron processors based on Socket A, as well as some AMD processors based on Socket AM2 and Socket AM2+.
While similar form factors have been used by other manufacturers, they are not referred to as CPGA. This type of packaging uses a ceramic substrate with pins arranged in an array. An organic pin grid array is a type of connection for integrated circuits, CPUs, where the silicon die is attached to a plate made out of an organic plastic, pierced by an array of pins which make the requisite connections to the socket. A stud grid array is a short-pinned pin grid array chip scale package for use in surface-mount technology; the polymer stud grid array or plastic stud grid array was developed jointly by the Interuniversity Microelectronics Centre and Laboratory for Production Technology, Siemens AG. The reduced pin grid array was used by the socketed mobile variants of Intel's Core i3/5/7 processors and features a reduced pin pitch of 1 mm, as opposed to the 1.27 mm pin pitch used by contemporary AMD processors and older Intel processors. It is used in the G1, G2, G3 sockets. Thomas, Andrew. "What the Hell is… a flip-chip?".
The Register. Retrieved December 30, 2011. "XSERIES 335 XEON DP-2.4G 512 MB". CNET. October 26, 2002. Retrieved December 30, 2011. "SURFACE MOUNT NOMENCLATURE AND PACKAGING". Intel CPU Processor Identification Ball Grid Arrays: the High-Pincount Workhorses, John Baliga, Associate Editor, Semiconductor International, 9/1/1999 Spot on component packaging, 08/1998, Produktion & Prüftechnik Terminology
The Intel 80486 known as the i486 or 486, is a higher performance follow-up to the Intel 80386 microprocessor. The 80486 was introduced in 1989 and was the first pipelined x86 design as well as the first x86 chip to use more than a million transistors, due to a large on-chip cache and an integrated floating-point unit, it represents a fourth generation of binary compatible CPUs since the original 8086 of 1978. A 50 MHz 80486 executes around 40 million instructions per second on average and is able to reach 50 MIPS peak performance; the 80486 was announced at Spring Comdex in April 1989. At the announcement, Intel stated that samples would be available in the third quarter of 1989 and production quantities would ship in the fourth quarter of 1989; the first 80486-based PCs were announced in late 1989, but some advised that people wait until 1990 to purchase an 80486 PC because there were early reports of bugs and software incompatibilities. The instruction set of the i486 is similar to its predecessor, the Intel 80386, with the addition of only a few extra instructions, such as CMPXCHG which implements a compare-and-swap atomic operation and XADD, a fetch-and-add atomic operation returning the original value.
From a performance point of view, the architecture of the i486 is a vast improvement over the 80386. It has an on-chip unified instruction and data cache, an on-chip floating-point unit and an enhanced bus interface unit. Due to the tight pipelining, sequences of simple instructions could sustain a single clock cycle throughput; these improvements yielded a rough doubling in integer ALU performance over the 386 at the same clock rate. A 16-MHz 80486 therefore had a performance similar to a 33-MHz 386, the older design had to reach 50 MHz to be comparable with a 25-MHz 80486 part. An 8 KB on-chip SRAM cache stores the most used instructions and data; the 386 supported a slower off-chip cache. An enhanced external bus protocol to enable cache coherency and a new burst mode for memory accesses to fill a cacheline of 16 bytes within 5 bus cycles; the 386 needed 8 bus cycles to transfer the same amount of data. Coupled pipelining completes a simple instruction like ALU reg,reg or ALU reg,im every clock cycle.
The 386 needed two clock cycles to do this. Integrated FPU with a dedicated local bus. Improved MMU performance. New instructions: XADD, BSWAP, CMPXCHG, INVD, WBINVD, INVLPG. Just as in the 80386, a simple flat 4 GB memory model could be implemented by setting all "segment selector" registers to a neutral value in protected mode, or setting "segment registers" to zero in real mode, using only the 32-bit "offset registers" as a linear 32-bit virtual address bypassing the segmentation logic. Virtual addresses were normally mapped onto physical addresses by the paging system except when it was disabled. Just as with the 80386, circumventing memory segmentation could improve performance in some operating systems and applications. On a typical PC motherboard, either four matched 30-pin SIMMs or one 72-pin SIMM per bank were required to fit the 80486's 32-bit data bus; the address bus used 30-bits complemented by four byte-select pins to allow for any 8/16/32-bit selection. This meant. There are several suffixes and variants..
Other variants include: Intel RapidCAD: a specially packaged Intel 486DX and a dummy floating-point unit designed as pin-compatible replacements for an Intel 80386 processor and 80387 FPU. i486SL-NM: i486SL based on i486SX. I487SX: i486DX with one extra pin sold as an FPU upgrade to i486SX systems. I486 OverDrive: i486SX, i486SX2, i486DX2 or i486DX4. Marked as upgrade processors, some models had different pinouts or voltage-handling abilities from "standard" chips of the same speed stepping. Fitted to a coprocessor or "OverDrive" socket on the motherboard, worked the same as the i487SX; the specified maximal internal clock frequency ranged from 16 to 100 MHz. The 16 MHz i486SX model was used by Dell Computers. One of the few 80486 models specified for a 50 MHz bus had overheating problems and was moved to the 0.8-micrometre fabrication process. However, problems continued when the 486DX-50 was installed in local-bus systems due to the high bus speed, making it rather unpopular with mainstream consumers, as local-bus video was considered a requirement at the time, though it remained popular with users of EISA systems.
The 486DX-50 was soon eclipsed by the clock-doubled i486DX2, which although running the internal CPU logic at twice the external bus speed, was slower due to the external bus running at only 25 MHz. The 486DX2 at 66 MHz was faster than the 486DX-50, overall. More powerful 80486 iterations such as the OverDrive and DX4 were less popular, as they came out after Intel had re